IXDF502 / IXDI502 / IXDN502

Transcription

1 IXDF / IXDI / IXD Ampere Dual Low-Side Ultrafast MOSFET Drivers Features Built using the advantages and compatibility of CMOS and IXYS HDMOS TM processes Latch-Up Protected up to Amps High A Peak Output Current Wide Operating Range:.V to V - C to + C Extended Operating Temperature High Capacitive Load Drive Capability: pf in <ns Matched Rise And Fall Times Low Propagation Delay Time Low Output Impedance Low Supply Current Two Drivers in Single Chip Applications Driving MOSFETs and IGBTs Motor Controls Line Drivers Pulse Generators Local Power O/OFF Switch Switch Mode Power Supplies (SMPS) DC to DC Converters Pulse Transformer Driver Class D Switching Amplifiers Power Charge Pumps General Description The IXDF, IXDI and IXD each consist of two - Amp CMOS high speed MOSFET Gate Drivers for driving the latest IXYS MOSFETs & IGBTs. Each of the Dual Outputs can source and sink Amps of Peak Current while producing voltage rise and fall times of less than ns. The input of each Driver is TTL or CMOS compatible and is virtually immune to latch up. Patented* design innovations eliminate cross conduction and current "shoot-through". Improved speed and drive capabilities are further enhanced by very quick & matched rise and fall times. The IXDF is configured with one Gate Driver Inverting plus one Gate Driver on-inverting. The IXDI is configured as a Dual Inverting Gate Driver, and the IXD is configured as a Dual on-inverting Gate Driver. The IXDF, IXDI and IXD are each available in the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) package, and the -Lead DF (D) package, (which occupies less than % of the board area of the 8-Pin SOIC). *United States Patent,9, Ordering Information Part umber Description Package Type Packing Style Pack Qty IXDFPI A Low Side Gate Driver I.C. 8-Pin PDIP Tube IXDFSIA A Low Side Gate Driver I.C. 8-Pin SOIC Tube 9 IXDFSIAT/R A Low Side Gate Driver I.C. 8-Pin SOIC Tape and Reel IXDFD A Low Side Gate Driver I.C. -Lead DF x Waffle Pack IXDFDT/R A Low Side Gate Driver I.C. -Lead DF Tape and Reel IXDIPI A Low Side Gate Driver I.C. 8-Pin PDIP Tube IXDISIA A Low Side Gate Driver I.C. 8-Pin SOIC Tube 9 IXDISIAT/R A Low Side Gate Driver I.C. 8-Pin SOIC Tape and Reel IXDID A Low Side Gate Driver I.C. -Lead DF x Waffle Pack IXDIDT/R A Low Side Gate Driver I.C. -Lead DF Tape and Reel IXDPI A Low Side Gate Driver I.C. 8-Pin PDIP Tube IXDSIA A Low Side Gate Driver I.C. 8-Pin SOIC Tube 9 IXDSIAT/R A Low Side Gate Driver I.C. 8-Pin SOIC Tape and Reel IXDD A Low Side Gate Driver I.C. -Lead DF x Waffle Pack IXDDT/R A Low Side Gate Driver I.C. -Lead DF Tape and Reel OTE: All parts are lead-free and RoHS Compliant Configuration Dual, with one Driver Inverting and one Driver on-inverting Dual, with both Drivers Inverting Dual, with both Drivers on- Inverting Copyright IXYS CORPORATIO All rights reserved First Release DS99B(/)

2 IXDF / IXDI / IXD Figure - IXDF Inverting + on-inverting A Gate Driver Functional Block Diagram I A ATI-CROSS CODUCTIO CIRCUIT * * P I B ATI-CROSS CODUCTIO CIRCUIT * * P GD Figure - IXDI Dual Inverting A Gate Driver Functional Block Diagram I A ATI-CROSS CODUCTIO CIRCUIT * * P I B ATI-CROSS CODUCTIO CIRCUIT * * P GD Figure - IXD Dual A on-inverting Gate Driver Functional Block Diagram I A ATI-CROSS CODUCTIO CIRCUIT * P I B ATI-CROSS CODUCTIO CIRCUIT * P GD * United States Patent,9, Copyright IXYS CORPORATIO All rights reserved

3 Absolute Maximum Ratings () Operating Ratings () Parameter Value Supply Voltage V All Other Pins -. V to V CC +.V Junction Temperature C Storage Temperature - C to C Lead Temperature ( Sec) C IXDF / IXDI / IXD Parameter Value Operating Supply Voltage.V to V Operating Temperature Range - C to C Package Thermal Resistance * 8-Pin PDIP (PI) θ J-A (typ) C/W 8-Pin SOIC (SIA) θ J-A (typ) C/W -Lead DF (D) θ J-A (typ) - C/W -Lead DF (D) θ J-C (max). C/W -Lead DF (D) θ J-S (typ). C/W Electrical T A = o C () Unless otherwise noted,.v V CC V. All voltage measurements with respect to GD. IXD_ configured as described in Test Conditions. All specifications are for one channel. Symbol Parameter Test Conditions Min Typ Max Units V IH High input voltage.v V CC 8V. V V IL Low input voltage.v V CC 8V.8 V V I Input voltage range - V CC +. V I I Input current V V I V CC - µa V OH High output voltage V CC -. V V OL Low output voltage. V R OH High state output resistance V CC = V. Ω R OL Low state output resistance V CC = V Ω I PEAK Peak output current V CC = V A I DC Continuous output current A t R Rise time C LOAD =pf V CC =V. ns t F Fall time C LOAD =pf V CC =V. 9 ns t ODLY On-time propagation delay C LOAD =pf V CC =V ns t OFFDLY Off-time propagation delay C LOAD =pf V CC =V ns V CC Power supply voltage. V I CC Power supply current V I =.V V I = V V I = +V CC () ma µa µa IXYS reserves the right to change limits, test conditions, and dimensions.

4 IXDF / IXDI / IXD Electrical temperatures over - o C to o C () Unless otherwise noted,.v V CC V, Tj < o C All voltage measurements with respect to GD. IXD_ configured as described in Test Conditions. All specifications are for one channel. Symbol Parameter Test Conditions Min Typ Max Units V IH High input voltage.v V CC V. V V IL Low input voltage.v V CC V.8 V V I Input voltage range - V CC +. V I I Input current V V I V CC - µa V OH High output voltage V CC -. V V OL Low output voltage. V R OH High state output resistance V CC = V Ω R OL Low state output resistance V CC = V Ω I DC Continuous output current A t R Rise time C LOAD =pf V CC =V ns t F Fall time C LOAD =pf V CC =V ns t ODLY On-time propagation ns C delay LOAD =pf V CC =V t OFFDLY Off-time propagation 8 ns C delay LOAD =pf V CC =V V CC Power supply voltage. V I CC Power supply current V I =.V V I = V V I = + V CC ma µa µa otes:. Operating the device beyond the parameters listed as Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.. The device is not intended to be operated outside of the Operating Ratings.. Electrical Characteristics provided are associated with the stated Test Conditions.. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily to highlight any specific performance limits within which the device is guaranteed to function. * The following notes are meant to define the conditions for the θ J-A, θ J-C and θ J-S values: ) The θ J-A (typ) is defined as junction to ambient. The θ J-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the resistance of the package, and the IXD_XX are typical. The values for these packages are natural convection values with vertical boards and the values would be lower with forced convection. For the -Lead DF package, the θ J-A value supposes the DF package is soldered on a PCB. The θ J-A (typ) is C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance to the die, it is easy to reduce the θ J-A by adding connected copper pads or traces on the PCB. These can reduce the θ J-A (typ) to C/W easily, and potentially even lower. The θ J-A for DF on PCB without heatsink or thermal management will vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management. ) θ J-C (max) is defined as juction to case, where case is the large pad on the back of the DF package. The θ J-C values are generally not published for the PDIP and SOIC packages. The θ J-C for the DF packages are important to show the low thermal resistance from junction to the die attach pad on the back of the DF, -- and a guardband has been added to be safe. ) The θ J-S (typ) is defined as junction to heatsink, where the DF package is soldered to a thermal substrate that is mounted on a heatsink. The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the U.S. or Europe, and not a premium Japanese IMS. A mil dialectric with a thermal conductivity of.w/mc was assumed. The result was given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the DF package. Copyright IXYS CORPORATIO All rights reserved

5 Pin Description IXDF / IXDI / IXD PI PACKAGE SYMBOL FUCTIO DESCRIPTIO SOIC, DIP DF SOIC, DIP DF SOIC, DIP DF SOIC, DIP DF SOIC, DIP DF SOIC, DIP DF I A A Channel Input A Channel Input signal-ttl or CMOS compatible. GD Ground The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance. I B B Channel Input B Channel Input signal-ttl or CMOS compatible. V CC B Channel Output Supply Voltage A Channel Output B Channel Driver output. For application purposes, this pin is connected via a resistor to a gate of a MOSFET/IGBT. Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from.v to V. A Channel Driver output. For application purposes, this pin is connected via a resistor to a gate of a MOSFET/IGBT. CAUTIO: Follow proper ESD procedures when handling and assembling this component. Pin Configuration IXDF IXDI IXD C I A GD C V S 8 IB C I A GD C V S 8 IB C I A GD C V S 8 IB 8 Lead PDIP (PI) 8 Lead PDIP (PI) 8 Lead PDIP (PI) 8 Pin SOIC (SI) (SIA) 8 Pin SOIC (SI) 8 Pin SOIC (SI) (SIA) (SIA) IXDF IXDI IXD Lead DF (D) Lead DF (D) Lead DF (D) (Bottom View) (Bottom View) (Bottom View) I A I A I A GD GD GD I B I B I B Figure - Characteristics Test Diagram OTE: Solder tabs on bottoms of DF packages are grounded uf.uf C C 8 In A Gnd In B Out A Out B Agilent A Current Probe Agilent A Current Probe pf pf IXYS reserves the right to change limits, test conditions, and dimensions.

6 IXDF / IXDI / IXD Fig. 8 Rise Time vs. Supply Voltage Typical Performance Characteristics Fig. Fall Time vs. Supply Voltage Rise Time (ns) pf pf Fall Time (ns) pf pf pf pf pf pf Fig. Rise / Fall Time vs. Temperature V SUPPLY = V C LOAD = pf Fig. 8 Rise Time vs. Capacitive Load 9 8 V Rise / Fall Time (ns) 8 Rise time Fall time Rise Time (ns) V V V - Temperature (C) Load Capacitance (pf) Fig. 9 Fall Time vs. Capacitive Load Fig.. Input Threshold Levels vs. Supply Voltage V Fall Time (ns) V V V Threshold Level (V).. Positive going input egative going Load Capacitance (pf) Copyright IXYS CORPORATIO All rights reserved

7 IXDF / IXDI / IXD Fig. Input Threshold Levels vs. Temperature Fig. Propagation Delay vs. Supply Voltage Rising Input, C LOAD = pf Input Threshold Level (V)... Positive going input egative going input Propagation Delay Time (ns) Inverting on-inverting - Temperature (C) Fig. Propagation Delay vs. Supply Voltage Falling Input, C LOAD = pf Fig. Propagation Delay vs. Temperature V SUPPLY = V C LOAD = pf Propagation Delay Time (ns) Inverting on-inverting Propagation Delay Time (ns) egative going input Positve going input - Temeprature (C) Fig. Quiescent Current vs Supply Voltage Fig. 9 Quiescent current vs Temperature V supply = V Quiescent Current (ua) inverting input=gnd non-inverting input=vcc Quescent Current (ua) 8 inverting input=gnd non-inverting input=vcc V V V V V V V V - - Temperature (C)

8 IXDF / IXDI / IXD Fig. Supply Current vs. Capacitive Load V SUPPLY = V Fig. 8 Supply Current vs. Frequency V SUPPLY = V 9 MHz 9 pf 8 khz 8 Load Capacitance (pf) Supply Current vs. Capacitive Load V SUPPLY = V MHz MHz Fig. 9 Fig. 8 8 Frequency (khz) pf pf pf Supply Current vs. Frequency V SUPPLY = V pf 8 Fig. khz Load Capacitance (pf) Supply Current vs. Capacitive Load V SUPPLY = V MHz MHz 8 Fig. Frequency (khz) pf pf pf Supply Current vs. Frequency V SUPPLY = V pf MHz pf pf khz Load Capacitance (pf) pf Frequency (khz) Copyright IXYS CORPORATIO All rights reserved 8

9 IXDF / IXDI / IXD Supply Current vs. Capacitive Load V SUPPLY = V Fig. Fig. Supply Current vs. Frequency V SUPPLY = V MHz MHz khz Load Capacitance (pf) Frequency (khz) Fig. Fig. pf pf pf pf Output Source Current vs. Supply Voltage Output Sink Current vs. Supply Voltage - Source Current (A) Sink Current (A) Fig. Output Source Current vs. Temperature V SUPPLY = V Fig. 8 Output Sink Current vs. Temperature V SUPPLY = V. Output Source Current (A)... Output Sink Current (A) Temperature (C) -. - Temperature (C) 9

10 IXDF / IXDI / IXD Fig. 9 Fig. High State Output Resistance vs. Supply Voltage Low State Output Resistance vs. Supply Voltage. Output Rsistance (ohms) Output Resistance (ohms).... Copyright IXYS CORPORATIO All rights reserved

11 IXDF / IXDI / IXD Supply Bypassing, Grounding Practices And Output Lead inductance When designing a circuit to drive a high speed MOSFET utilizing the IXD_, it is very important to observe certain design criteria in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. Say, for example, we are using the IXD_ to charge a pf capacitive load from to volts in ns. Using the formula: I = C V/ t, where V=V C=pF & t=ns, we can determine that to charge pf to volts in ns will take a constant current of.a. (In reality, the charging current won t be constant, and will peak somewhere around A). SUPPLY BYPASSIG In order for our design to turn the load on properly, the IXD_ must be able to draw this.a of current from the power supply in the ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is an order of magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected and should have low inductance, low resistance and high-pulse currentservice ratings). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXD_ to an absolute minimum. GROUDIG In order for the design to turn the load off properly, the IXD_ must be able to drain this.a of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path # is between the IXD_ and its load. Path # is between the IXD_ and its power supply. Path # is between the IXD_ and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXD_. OUTPUT LEAD IDUCTACE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and its load as short and wide as possible. If the driver must be placed farther than. (mm) from the load, then the output leads should be treated as transmission lines. In this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load.

12 IXDF / IXDI / IXD A b b b c D D E E e ea eb L E H e B D A A B C D E e H h L M h X L C M.±. [.99±.].9±. [.±.]. [.9] S.^.; o[ S.^.;o]. [.].9 [.].9 [.9].8 [.]. [.8]. [.]. [.] IXYS Corporation Bassett St; Santa Clara, CA 9 Tel: 8-98-; Fax: sales@ixys.net IXYS Semiconductor GmbH Edisonstrasse ; D-8; Lampertheim Tel: +9---; Fax: marcom@ixys.de Copyright IXYS CORPORATIO All rights reserved