TC4467 TC4468 LOGIC-INPUT CMOS QUAD DRIVERS TC4467 TC4468 TC4469 GENERAL DESCRIPTION FEATURES APPLICATIONS ORDERING INFORMATION

Size: px

Start display at page:

Download "TC4467 TC4468 LOGIC-INPUT CMOS QUAD DRIVERS TC4467 TC4468 TC4469 GENERAL DESCRIPTION FEATURES APPLICATIONS ORDERING INFORMATION"

Alexia Perkins
6 years ago
Views:

1 TC TC LOGIC-INPUT CMOS FEATURES High Peak Output Current....A Wide Operating Range.... to V Symmetrical Rise and Fall Times... nsec Short, Equal Delay Times... nsec Latchproof! Withstands ma Inductive Kickback Input Logic Choices AND/NAND/AND+Inv kv ESD Protection on All Pins APPLICATIONS General-Purpose CMOS Logic Buffer Driving All Four MOSFETs in an H-Bridge Direct Small Motor Driver Relay or Peripheral Drivers CCD Driver Pin-Switching Network Driver LOGIC DIAGRAMS GENERAL DESCRIPTION The TCX family of four-output CMOS buffer/drivers are an expansion from our earlier single- and dual-output drivers. Each driver has been equipped with a two-input logic gate for added flexibility. The TCX drivers can source up to ma into loads referenced to ground. Heavily loaded clock lines, coaxial cables, and piezoelectric transducers can all be easily driven with the X series drivers. The only limitation on loading is that total power dissipation in the IC must be kept within the power dissipation limits of the package. The TCX series will not latch under any conditions within their power and voltage ratings. They are not subject to damage when up to V of noise spiking (either polarity) occurs on the ground line. They can accept up to half an amp of inductive kickback current (either polarity) into their outputs without damage or logic upset. In addition, all terminals are protected against ESD to at least V. ORDERING INFORMATION Part No. Package Temp. Range TC*COE -Pin SOIC (Wide) to + C TC*CPD -Pin Plastic DIP to + C TC*EJD -Pin CerDIP to + C TC*MJD -Pin CerDIP to + C *A digit must be added in this position to define the device input configuration: TCX NAND AND AND with INV TC TC TCX VDD A B Y A B Y A B Y A B Y A B Y A B Y OUTPUT A B Y A B Y A B Y A B Y A B Y A B Y TC//- // TelCom Semiconductor reserves the right to make changes in the circuitry and specifications of its devices.

2 TC TC ABSOLUTE MAXIMUM RATINGS* Supply Voltage... +V Input Voltage... ( V) to ( +.V) Maximum Chip Temperature Operating... + C Storage... to + C Maximum Lead Temperature (Soldering, sec)... + C Operating Ambient Temperature Range C Device... to + C E Device... to + C M Device... to + C Package Power Dissipation (T A C) -Pin CerDIP...mW -Pin Plastic DIP...mW -Pin Wide SOIC...mW LOGIC-INPUT CMOS Package Thermal Resistance -Pin CerDIP R θj-a... C/W R θj-c... C/W -Pin Plastic DIP R θj-a... C/W R θj-c... C/W -Pin Wide SOIC R θj-a... C/W R θj-c... C/W *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS: Measured at T A = + C with.v V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit Input V IH Logic, High Input Voltage Note. V V IL Logic, Low Input Voltage Note. V I IN Input Current V V IN µa Output V OH High Output Voltage I LOAD = µa (Note ). V V OL Low Output Voltage I LOAD = ma (Note ). V R O Output Resistance I OUT = ma, = V Ω I PK Peak Output Current. A I DC Continuous Output Current Single Output ma Total Package I Latch-Up Protection.V V ma Withstand Reverse Current Switching Time t R Rise Time Figure nsec t F Fall Time Figure nsec t D Delay Time Figure nsec t D Delay Time Figure nsec Power Supply I S Power Supply Current. ma Power Supply Voltage Note. V TRUTH TABLE Part No. TC NAND TC AND AND/INV INPUTS A H H L L H H L L H H L L INPUTS B H L H L H L H L H L H L OUTPUTS TCX L H H H H L L L L H L L H = High L = Low

3 TC TC ELECTRICAL CHARACTERISTICS: Measured throughout operating temperature range with.v V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit Input V IH Logic, High Input Voltage (Note ). V V IL Logic, Low Input Voltage (Note ). V I IN Input Current V V IN µa Output V OH High Output Voltage I LOAD = µa (Note ). V V OL Low Output Voltage I LOAD = ma (Note ). V R O Output Resistance I OUT = ma, = V Ω I PK Peak Output Current. A I Latch-Up Protection.V V ma Withstand Reverse Current Switching Time t R Rise Time Figure nsec t F Fall Time Figure nsec t D Delay Time Figure nsec t D Delay Time Figure nsec Power Supply I S Power Supply Current ma I S Power Supply Voltage Note. V NOTES:. Totem-pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device.. When driving all four outputs simultaneously in the same direction, shall be limited to V. This reduces the chance that internal dv/dt will cause high-power dissipation in the device.. The input threshold has about mv of hysteresis centered at approximately.v. Slow moving inputs will force the device to dissipate high peak currents as the input transitions through this band. Input rise times should be kept below µs to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum or below the minimum input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device. PIN CONFIGURATIONS -Pin SOIC (Wide) -Pin Plastic DIP/CerDIP A B A B A TC// VDD Y Y Y A B A B TC// VDD Y Y Y B Y A Y B B B A A

4 TC TC Supply Bypassing Large currents are required to charge and discharge large capacitive loads quickly. For example, charging a pf load to V in ns requires.a from the device's power supply. To guarantee low supply impedance over a wide frequency range, a µf film capacitor in parallel with one or two low-inductance. µf ceramic disk capacitors with short lead lengths (<. in.) normally provide adequate bypassing. Grounding The TC and contain inverting drivers. Potential drops developed in common ground impedances from input to output will appear as negative feedback and degrade switching speed characteristics. Instead, individual ground returns for input and output circuits, or a ground plane, should be used. Input Stage The input voltage level changes the no-load or quiescent supply current. The N-channel MOSFET input stage transistor drives a. ma current source load. With logic "" outputs, maximum quiescent supply current is ma. Logic "" output level signals reduce quiescent current to. ma maximum. Unused driver inputs must be connected to or V SS. Minimum power dissipation occurs for logic "" outputs. The drivers are designed with mv of hysteresis. This provides clean transitions and minimizes output stage current spiking when changing states. Input voltage thresholds are approximately.v, making any voltage greater than.v up to a logic input. Input current is less than µa over this range. Power Dissipation The supply current versus frequency and supply current versus capacitive load characteristic curves will aid in determining power dissipation calculations. TelCom Semiconductor's CMOS drivers have greatly reduced quiescent DC power consumption. Input signal duty cycle, power supply voltage and load type, influence package power dissipation. Given power dissipation and package thermal resistance, the maximum ambient operating temperature is easily calculated. The - pin plastic package junction-to-ambient thermal resistance is. C/W. At + C, the package is rated at mw maximum dissipation. Maximum allowable chip temperature is + C. LOGIC-INPUT CMOS Three components make up total package power dissipation: () Load-caused dissipation (P L ) () Quiescent power (P Q ) () Transition power (P T ). A capacitive-load-caused dissipation (driving MOSFET gates), is a direct function of frequency, capacitive load, and supply voltage. The power dissipation is: P L = f C V S, where: f = Switching frequency C = Capacitive load V S = Supply voltage. A resistive-load-caused dissipation for ground-referenced loads is a function of duty cycle, load current, and load voltage. The power dissipation is: P L = D (V S V L ) I L, where: D = Duty cycle V S = Supply voltage V L = Load voltage I L = Load current. A resistive-load-caused dissipation for supply-referenced loads is a function of duty cycle, load current, and output voltage. The power dissipation is: P L = D V O I L, where: f = Switching frequency V O = Device output voltage I L = Load current. Quiescent power dissipation depends on input signal duty cycle. Logic HIGH outputs result in a lower power dissipation mode, with only. ma total current drain (all devices driven). Logic LOW outputs raise the current to ma maximum. The quiescent power dissipation is: P Q = V S (D(I H ) + ( D)I L ), where: I H = Quiescent current with all outputs LOW ( ma max) I L = Quiescent current with all outputs HIGH (. ma max) D = Duty cycle V S =Supply voltage.

5 Transition power dissipation arises in the complementary configuration (TCX) because the output stage N-channel and P-channel MOS transistors are ON simultaneously for a very short period when the output changes. The transition power dissipation is approximately: P T = f V S ( ). Maximum operating temperature: T J θ JA (P D ) = C, TC TC where: T J = Maximum allowable junction temperature (+ C) θ JA = Junction-to-ambient thermal resistance (. C/W) -pin plastic package. Package power dissipation is the sum of load, quiescent and transition power dissipations. An example shows the relative magnitude for each term: C = pf capacitive load V S = V D = % f = khz P D = Package Power Dissipation = P L + P Q + P T = mw + mw + mw = mw. NOTE: Ambient operating temperature should not exceed + C for "EJD" device or + C for "MJD" device. µf FILM. µf CERAMIC A B A B A B A B V OUT pf +V INPUT (A, B) V OUTPUT V % % % % t D t D t R t F % % Input: khz, square wave, t RISE = t FALL ns Figure. Switching Time Test Circuit

6 TC TC LOGIC-INPUT CMOS CHARACTERISTICS CURVES pf Rise Time vs Supply Voltage pf Fall Time vs Supply Voltage t (RISE) (nsec) pf pf pf t (FALL) (nsec) pf pf pf pf pf V SUPPLY (V) V SUPPLY (V) Rise Time vs Capacitive Load Fall Time vs Capacitive Load V V t (RISE) (nsec) V V t (FALL) (nsec) V V, C LOAD (pf), C LOAD (pf) TIME (nsec) Rise/Fall Times vs Temperature V SUPPLY =.V C LOAD = pf t (FALL) t (RISE) DELAY TIME (nsec) Propagation Delay Time vs Supply Voltage C LOAD = pf t D t D TEMPERATURE ( C) V SUPPLY (V)

7 TC TC CHARACTERISTICS CURVES (Cont.) DELAY TIME (nsec) Input Amplitude vs Delay Times INPUT RISING td INPUT FALLING td = V DELAY TIME (nsec) Propagation Delay Times vs Temperature =.V C LOAD = pf t D V IN =, V td V DRIVE (V) TEMPERATURE ( C) Quiescent Supply Current vs Supply Voltage Quiescent Supply Current vs Temperature I QUIESCENT (ma)..... OUTPUTS = OUTPUTS = I QUIESCENT (ma) V =.V DD OUTPUTS HIGH OUTPUTS LOW V SUPPLY (V) T JUNCTION ( C) High-State Output Resistance Low-State Output Resistance R DS(ON) ( Ω ) T J = + C T J = + C R DS(ON) ( Ω ) T = + C J T J = + C V (V) SUPPLY V SUPPLY (V)

8 TC TC LOGIC-INPUT CMOS SUPPLY CURRENT CHARACTERISTICS (Load on Single Output Only) = V Supply Current vs Capacitive Load khz, C LOAD (pf) MHz MHz khz khz = V Supply Current vs Frequency FREQUENCY (khz) pf pf pf, Supply Current vs Capacitive Load Supply Current vs Frequency V DD = V MHz V DD = V pf MHz khz pf khz khz pf, C LOAD (pf) FREQUENCY (khz), Supply Current vs Capacitive Load = V Supply Current vs Frequency = V MHz khz khz khz, C LOAD (pf) MHz FREQUENCY (khz) pf pf pf,

9 TC TC TYPICAL APPLICATIONS Stepper Motor Drive +V Quad Driver for H-Bridge Motor Control +V TO +V A B RED GRAY YEL AIRPAX #M-P. /STEP MOTOR V DIRECTION REV FWD PWM SPEED MOTOR BLK -Volt, -Phase Brushless Output Stage V A+ B+ C+ A B C D N V C µf R. kω W R. kω R. kω R. kω B A B A B A B Y D D D R R (FLOAT AT V) Q V. kω R N R R V Q DD A. kω N B Y R A Q B Y. kω N U A B Y A B Y A Y Y U Y MOTOR MOTOR MOTOR PHASE A PHASE B PHASE C

10 TC TC LOGIC-INPUT CMOS PACKAGE DIMENSIONS -Pin CerDIP PIN. (.). (.). (.) MAX.. (.) MIN.. (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.) MIN.. (.). (.) MIN.. (.). (.). (.). (.). (.). (.). (.). (.) PIN -Pin Plastic DIP. (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.). (.) MIN.. (.). (.). (.). (.). (.). (.). (.). (.) Dimensions: inches (mm)

11 TC TC PACKAGE DIMENSIONS (Cont.) -Pin SOIC (Wide) PIN. (.). (.). (.). (.). (.). (.). (.) TYP.. (.). (.). (.). (.). (.). (.) MAX.. (.). (.). (.). (.) Dimensions: inches (mm) Sales Offices TelCom Semiconductor Terra Bella Avenue P.O. Box Mountain View, CA - TEL: -- FAX: -- liter@csmtp.telcom-semi.com TelCom Semiconductor Austin Product Center Burnet Rd. Suite Austin, TX TEL: -- FAX: -- TelCom Semiconductor H.K. Ltd. Sam Chuk Street, Ground Floor San Po Kong, Kowloon Hong Kong TEL: -- FAX: -- Printed in the U.S.A.

TC4427 TC A DUAL HIGH-SPEED POWER MOSFET DRIVERS 1.5A DUAL HIGH-SPEED POWER MOSFET DRIVERS TC4426 TC4426 GENERAL DESCRIPTION FEATURES

TC4427 TC A DUAL HIGH-SPEED POWER MOSFET DRIVERS 1.5A DUAL HIGH-SPEED POWER MOSFET DRIVERS TC4426 TC4426 GENERAL DESCRIPTION FEATURES FEATURES High Peak Output Current....A Wide Operating Range....V to V High Capacitive Load Drive Capability... pf in nsec Short Delay Time... < nsec Typ. Consistent Delay Times With Changes in Supply Voltage