AC & DC Characteristics Over Guaranteed Operating Temperature Range
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- Primrose Nicholson
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1 V2 / Data Sheet The most important thing we build is trust Description: The MADRMA0001 family of quad bias drivers can either be configured to translate TTL signals into the negative voltages required for GaAs FET switches or attenuators or they can be used to produce up to ±40 ma per channel for biasing series or shunt PIN diode switches. Each channel contains Inverting and Non-Inverting Outputs for logic flexibility. Designed with high-speed CMOS technology, the drivers achieve high performance with very low power dissipation. Features: Propagation Delay less than 25 ns Complementary Outputs High positive and negative output currents True TTL Inputs Low Quiescent Power Dissipation Available in DIE and QFN-20 Surface Mount Package formats Available in Pb-free RoHS compliant package or Sn/Pb plated package for Military applications (No Pure Sn) MADRMA0001: DIE MADRMA0002: QFN-20, Tin Plating (Sn, 100%) MADR DR0002: QFN-20, Tin-Lead Plating (Sn/Pb, 85%/15%) AC & DC Characteristics Over Guaranteed Operating Temperature Range Symbol Parameter Test Conditions Units Min Typ Max V IH Input HIGH Voltage V 2.0 V cc V IL Input LOW Voltage V V OH Output HIGH Voltage No Load V V OL Output LOW Voltage No Load V I IN Input Current V IN = V CC or GND µa Rout Output Resistance Ω I OH DC Output Current HIGH Set by external resistors, R2 or R3 ma 40 I OL DC Output Current LOW Set by external resistors, R2 or R3 ma -40 I CC Quiescent Supply Current V CC = Max, V in = V cc or GND µa 400 T PHL, T PLH Propagation Delay 40 C to + 85 C ns T THL, T TLH Output Transition Time 40 C to + 85 C ns 3 6 Delay Skew, Output A to Output B 40 C to + 85 C ns 3 6 Minimum Pulse Width ns 30 Maximum PRF MHz 15 For further information, please contact: This data sheet/brochure has been released into the public domain in accordance with International Traffic in Arms Regulations (ITAR) 22 CFR (6). Ref: 13-S-1833 Approved May 3, 2013 Cobham Electronics Systems 5300 Hellyer Avenue, San Jose, California USA Tel. +1 (877) Fax +1 (978) CESComponents@Cobham.com 1
2 Absolute Maximum Rating Guaranteed Input Operating Ranges Parameter V CC V CC V IN V OUT I in I out Storage Temperature QFN Operating Temperature DIE Operating Temperature Absolute Maximum -.5V to V V to 0.0 V Equal to Vcc 12 V -0.5 V to VCC +0.5 V VEE to Vcc ± 25 ma ± 50 ma -65 C to +150 C -40 C to +85 C -55 C to +125 C Symbol Parameter Unit Min Typical Max V C Positive DC Supply V V Negative DC Supply V V O Output DC Supply V 0.0 Vcc T A Operating Temperature C TTL Input Rise or Fall Time 10% to 90%, 90% to 10% ѳj-c DIE QFN ns 500 C/W C/W QFN C/W 30 Note: The TTL interface is a CMOS structure. Without V CC applied, the input will be low impedance. Once V CC is applied, the driver will function as specified without latching-up. Note: All voltages are relative to GND. Switching Waveforms Logic Diagram INPUT C VIN 90% TF TR LOGIC 1 C 1 A 1 B1 1.3 V A 2 10% LOGIC 0 C2 TPLH TPHL B2 OUTPUT A VOUT OUTPUT B 50% 90% GND 10% TTLH TTHL C4 A 4 C 3 A 3 B3 B4 Note: See Switching Wave Forms for the definition of the switching terms. Supplies must be by-passed with 0.1µF Capacitors. Unused inputs must be tied to Ground. Truth Table Input - CX Outputs - AX Output - BX 0 1 This data sheet/brochure has been released into the public domain in accordance with International Traffic in Arms Regulations (ITAR) 22 CFR (6). Ref: 13- S-1833 Approved May 3,
3 MADRMA001 Outline: While die pad and package pin numbers are different, the functions remain the same. The back of the die is internally connected to Vee. It must remain isolated from other Voltages. B4 V CC A4 C4 C3 C2 C1 B3 A3 B2 A2 GND B1 A1 Die Size: 48 x 64 mils Die Thickness: 10 mils max Pads: 4 x 4 mils Assembly Instructions: Die attach: Use non-conductive epoxy. Wirebonding: 160 C using standard ball or thermal compression wedge bond technique. This data sheet/brochure has been released into the public domain in accordance with International Traffic in Arms Regulations (ITAR) 22 CFR (6). Ref: 13-S-1833 Approved May 3,
4 MADRMA0002 / MADR DR0002 Outline: Symbols Dimensions in Millimeters Min Nom Max A A A REF - b D D E E e L Pin Configuration (QFN-20) Pin Function Pin Function Pin Function Pin Functions 1 GND 6 A2 11 A4 16 C4 2 N/C 7 B2 12 B4 17 C3 3 N/C 8 N/C C2 4 A1 9 A3 14 N/C 19 C1 5 B1 10 B3 15 V CC 20 Note: The center paddle on the back of the package should be left floating. The paddle Does not require a thermal or electrical connection. Absolute Maximum Rating Part Number Description Available Packaging Marking Code MADRMA0001 Die Waffle Pack (100 die per pack) - MADRMA0002 QFN-20, Tin Plating Bulk or Tape & Reel (1K Reel) S014 MADR DR0002 QFN-20, Tin-Lead Plating Bulk or Tape & Reel (1K Reel) S028 Note: Packaging choices will be noted as a service line item on any quotation or sales order. This data sheet/brochure has been released into the public domain in accordance with International Traffic in Arms Regulations (ITAR) 22 CFR (6). Ref: 13- S-1833 Approved May 3,
5 Application Information The input logic voltage (V in) cannot exceed the positive supply (Vcc) by more than 0.5 V nor go below GND by more than 0.5 V. The input current should not exceed ± 25 ma. This device should be treated as any TTL CMOS circuit. Pull-up/down resistors should tie to Vcc or GND. Nonused inputs must be tied to GND. Decoupling caps (0.1 uf) should be used on Vcc and Vee and the output current should be limited to ±40 ma. Logic 0 sets J0 to J1 to low loss state Limiting Resistors (R2, R3) set for +/-20 ma output current The value of the limiting resistors (R2, R3) is determined by the following: R L = [(Vcc-Vdiode)/I desired]-rout Driving PIN Diode Switches: Driving FET Switches: This data sheet/brochure has been released into the public domain in accordance with International Traffic in Arms Regulations (ITAR) 22 CFR (6). Ref: 13-S-1833 Approved May 3,
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PI5C Bit Bus Switch with Individual Enables A 1 B 1 GND. Features. Description. Pin Configuration. Block Diagram.
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74HCT138. Description. Pin Assignments. Features. Applications 3 TO 8 LINE DECODER DEMULTIPLEXER 74HCT138
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LMS75LBC176 Differential Bus Transceivers
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SY89297U. General Description. Features. Applications. Markets. 2.5/3.3V, 3.2Gbps Precision CML Dual-Channel Programmable Delay
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74LVCE1G00 SINGLE 2 INPUT POSITIVE NAND GATE. Description. Pin Assignments NEW PRODUCT. Features. Applications
Description Pin Assignments The is a single 2-input positive NAND gate with a standard totem pole output. The device is designed for operation with a power supply range of 1.4V to 5.5V. The inputs are
3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER
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FST Bit Bus Switch
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SY89540U. General Description. Features. Typical Performance. Applications. Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
HIGH SPEED- MBit/s DESCRIPTION The, /6 single-channel and /6 dual-channel optocouplers consist of a 5 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable
ISOCOM ICPL2630 / ICPL2631 COMPONENTS DESCRIPTION FEATURES SOLUTE MAXI- MUM RATINGS APPLICATIONS ORDER INFORMATION
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TC4421/TC A High-Speed MOSFET Drivers. General Description. Features. Applications. Package Types (1)
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UNISONIC TECHNOLOGIES CO., LTD
U74CBT3257 4-BIT 1-OF-2 FET MULTIPLEXER/ DEMULTIPLEXER UNISONIC TECHNOLOGIES CO., LTD CMOS IC DESCRIPTION The U74CBT3257 is a 4-bit 1-of-2 high-speed TTL-compatible FET multiplexer/demultiplexer. The low
8 PIN DIP WIDE BODY HIGH SPEED 10MBit/s LOGIC GATE PHOTOCOUPLER ELW137 ELW26XX Series
Schematic 1 8 2 7 Features High speed 10Mbit/s Guaranteed performance from -40 to 85 Logic gate output High isolation voltage between input and output (Viso =5000 V rms ). Compliance with EU REACH The
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NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear
TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear General Description The NC7SZ175 is a single positive edge-triggered D-type CMOS Flip-Flop with Asynchronous Clear from Fairchild s Ultra High Speed
Low Power Octal ECL/TTL Bi-Directional Translator with Latch
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3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX
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MM74HC86 Quad 2-Input Exclusive OR Gate
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Low Power Quint 2-Input OR/NOR Gate
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NOT RECOMMENDED FOR NEW DESIGNS. 3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER
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