IXD611S1 IXD611S7. 600V, 600 ma High & Low-side Driver for N-Channel MOSFETs and IGBTs. Features. General Description

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1 IXD V, ma High & Low-side Driver for N-Channel MOSFETs and IGBTs IXD Features Floating High Side Driver with boot-strap Power supply along with a Low Side Driver. Fully operational to V ± V/ns dv/dt immunity Gate drive power supply range: - V Undervoltage lockout for both output drivers Outputs are in phase with inputs Built using the advantages and compatibility of CMOS and IXYS HDMOS TM processes Latch-Up protected over entire operating range High peak output current: ± ma Matched propagation delay for both outputs Low output impedance Low power supply current Immune to negative voltage transients Applications Driving MOSFETs and IGBTs in half-bridge circuits High voltage, high side and low side drivers Motor Controls Switch Mode Power Supplies (SMPS) DC to DC Converters Class D Switching Amplifiers General Description The IXD, with its two inputs referenced to ground, has high speed low side and high side gate ouptuts to drive either a pair of N-channel MOSFETs or IGBTs in a half-bridge totem pole configuration. The High Side driver can control a MOSFET or IGBT connected to a positive high voltage up to V. The logic input stages are compatible with TTL or CMOS, have built-in hysteresis and are fully immune to latch up over the entire operating range. The IXD can withstand dv/dt on the output side up to ± V/ns. The IXD comes in either the -PIN PDIP (IXDP), -PIN SOIC (IXDS), -PIN PDIP (IXDP), or the -PIN SOIC (IXDS) packages. Ordering Information Part Number Package Type IXDP IXDP IXDS IXDS -PIN DIP -PIN DIP -PIN SOIC -PIN SOIC Warning: The IXD is ESD sensitive. Figure A. Typical Circuit for IXDP/S Figure B. Typical Circuit for IXDP/S Up to V Up to V VCC VCL VCH To Load VCC VCL VCH To Load GND DG GND IXYS CORPORATION All rights reserved First Release DS999A(/)

2 IXD Figure. IXD Functional Block Diagram Pin Description And Configuration SYMBOL FUTION DESCRIPTION VCL Supply Voltage Low side power supply. Input High side Input signal, TTL or CMOS compatible; in phase Input Low side Input signal, TTL or CMOS compatible; in phase DG Ground Logic reference ground (Not available for IXDP, IXDS) VCH Supply Voltage High side floating power supply, referenced to Output High side driver output Return High side floating ground Output Low side driver output Ground Low side ground IXYS reserves the right to change limits, test conditions, and dimensions.

3 IXD Figure A. Pin configuration for IXDP ( pin DIP) and IXDS ( pin SOIC) VCL VCH VCL VCH IXDP IXDS pin DIP pin SOIC Figure B. Pin configuration for IXDP ( pin DIP) and IXDS ( pin SOIC) VCL VCL VCH VCH DG IXDP DG IXDS 9 9 pin DIP pin SOIC IXYS CORPORATION All rights reserved

4 Absolute Maximum Ratings Symbol Definition Min Max Units V High side floating supply offset voltage - V High side floating absolute voltage -. V V High side floating output voltage V V V CL Low side fixed supply voltage -. V V Low side output voltage -. V CL +. V V DG Logic supply offset voltage (P, S only) V -. V +. V V IN Logic input voltage( & ) -. V CL +. V dv /dt Allowable offset supply voltage transient V/ns P D Package power dissipation@ T A C pin PDIP. W pin SOIC. W pin PDIP. W pin SOIC. W R THJA Thermal resistance, junction-to-ambient pin PDIP o C/W pin SOIC o C/W pin PDIP o C/W pin SOIC o C/W T J Junction Temperature o C T S Storage temperature - o C T L Lead temperature (soldering, s) o C IXD Recommended Operating Conditions Symbol Definition Min Max Units V High side floating supply offset voltage - V High side floating supply absolute voltage V V High side floating output voltage V V V CL Low side fixed supply voltage V V Low side output voltage V CL V V DG Logic supply offset voltage (P, S only) V -. V +. V V IN Logic input voltage(, ) V DG or V CL V T A Ambient Temperature - o C IXYS reserves the right to change limits, test conditions, and dimensions.

5 IXD Dynamic Electrical Characteristics Symbol Definition Test Conditions Min Typ Max Units t on Turn-on propagation delay V CL = = V, C LOAD = nf ns t off Turn-off propagation delay V CL = = V, C LOAD = nf 9 ns t r Turn-on rise time V CL = = V, C LOAD = nf ns t f Turn-off fall time V CL = = V, C LOAD = nf ns t dm Delay matching, & turn-on/off C LOAD = nf ns Static Electrical Characteristics Symbol Definition Test Conditions Min Typ Max Units V INH Logic input voltage V CL = = V. V V INL Logic input voltage V CL = = V. V V H / / V H High level output voltage, I O = ma.. V -V or V CL -V V L / / V L Low level output voltage, I O = ma.. V V or V I HL to bias current. V = V.. ma I Q Quiescent supply current = V V IN = V or V IN = V.. ma I Q Quiescent V CL supply current V CL = V V IN = V or V IN = V.. ma I IN + Logic input bias current V IN = V SUPPLY = V ua I IN - Logic input bias current V IN = V ua UV + supply undervoltage positive going threshold... V UV - supply undervoltage negative going threshold.. V V CLUV + V CL supply undervoltage positive going threshold.. V V CLUV - V CL supply undervoltage negative going threshold.. V UVH, V CLUVH Undervoltage Hysteresis.. V I GO + or Output high short circuit current; V GO = V, V IN = V, PW<us.. A I GO - or Output low short circuit current; V GO = V, V IN = V, PW<us A Precaution : When performing the high voltage tests, adequate safety precautions should be taken. IXYS CORPORATION All rights reserved

6 IXD Timing Waveform Definitions Figure. INPUT/OUPUT Timing Diagram tdon % % tr tdoff 9% 9% tf % % 9% tdm % % tdm % Outgoing Signal Figure. Definitions of Switching Time Waveforms Figure. Definitions of Delay Matching Waveforms V++ Buss (V ) V V V ~ ~ ~ Sample Tested for Operation khz khz MHz f PWM Figure. Device operating range: Buss voltage vs. Frequency Tested in typical circuit configuration (refer to Figure 9 & ) IXYS reserves the right to change limits, test conditions, and dimensions.

7 NDYC uf/v IXDS /W /W IXD V DC_DC Boost V Vout+ uf Low ESR NDYC GND Vout- uf V Low ESR.k W Up to V V VCL VCH nf TX : Out uf.uf IXD N/C uf kv x.uf kv Measure dv/dt Drive Input dv/dt slope adjustment IXDN ohm multi turn Figure. Test circuit for allowable offset supply voltage transient. V CL VIN+ uf/v MLCC VOUT- VOUT+ GND VOUT- VOUT+ k Up to V IXCP M9S. N V CL uf/v k k uf/v MLCC V CL. N IXTHNP uh.uf IXTHNP.uF.uF/kV Figure 9. Test circuit for high frequency, khz, operation., V CL = V IXYS CORPORATION All rights reserved

8 NDYC uf/v IXDS IXD V CL uf/v MLCC VIN+ VOUT- VOUT+ GND VOUT- VOUT+ k Up to V IXCP M9S. N V CL uf/v k k uf/v MLCC V CL. N IXTHNP.uF/kV IXTHNP Figure. Test circuit for low frequency, khz, operation., V CL = V IXYS reserves the right to change limits, test conditions, and dimensions.

9 IXD Fig. Rise Times vs. Supply Voltage Fig. Fall Times vs. Supply Voltage Rise Time (ns) pf Fall Time (ns) pf pf pf Rise / Fall Times (ns) Fig. Rise / Fall Times vs. Temperature V IN = V SUPPLY = V C LOAD = pf Rise Fall - Fig. Propagation Delay (ns) Propagation Delay vs. Supply Voltage C L = pf V IN = V SUPPLY Low side positive going Low side negative going High side positive going High side negative going Fig. Propagation Delay(ns) 9 Propagation Delay vs. Temperature V IN = V SUPPLY = V C LOAD = pf Pos. going input Neg. going input Fig. Under Voltage Lock Out vs. Temperature Lock Out Threshold (V) 9. 9 Pos. going supply voltage.. Neg. going supply voltage IXYS CORPORATION All rights reserved 9

10 IXD Fig. Fig. Input Threshold Level vs. Supply Voltage. Input Threshold Level vs. Temperature V SUPPLY = V. Threshold Level (V)... Positve going Negative going Threshold Level (V).. Pos. going input Neg. going input... - Fig.9 Fig. Quiescent Current vs. Temperature Quiescent Supply Current vs. Supply Voltage V IN = "" V SUPPLY = V Both Drivers Combined V IN = "".. Quiescent Current (ma).... High side Low side Quiescent Current (ma) Fig. / Bias Current vs. Supply Voltage V IN = Supply Voltage. Fig. - / Bias Current vs. Temperature V SUPPLY = V Input Bias Current (ua) Logic "" either input pin Logic "" ua max. Input Bias Current (ua) V IN = V V IN = V - IXYS reserves the right to change limits, test conditions, and dimensions.

11 Fig. Fig. Low Level Output Voltage vs. Supply Voltage Io = ma IXD High Level Ouput Voltage vs. Supply Voltage I o = ma Low Level Output Voltage (mv) Low Side High Side Fig. Output Source Current vs. Supply Voltage High Level Ouput Voltage (mv) Fig. Low Side High Side Output Sink Current vs. Supply Voltage Output Source Current (A) Output Sink Current (A) Fig..9. Output Source Current vs. Temperature V SUPPLY = V Fig Output Sink Current vs. Temeprature V SUPPLY = V Source Current (A) Sink Current (A) IXYS CORPORATION All rights reserved -.9 -

12 Supply Current vs. Supply Voltage C LOAD = pf V IN = V SUPPLY % Duty Cycle Fig. 9 Fig. IXD Supply Current vs. Supply Voltage C LOAD = pf V IN = V SUPPLY % Duty Cycle MHz MHz Supply Current (ma) MHz MHz High side KHz Low side KHz High side KHz Low side KHz Supply Current (ma) KHz High SideKHz Low SideKHz. Fig. Leakage Current (ma) High To Low Side Leakage Current vs.high Side V OFFSET Fig. High to Low Side Leakage Current vs. Temperature V OFFSET = V V CL = = V Leakage Current (ua) Fig. Fig. Output Resistance vs. Supply Voltage High Side Offset Voltage (V) - Pulse Width Stability vs. Temperature V CL = = V Input PW = ns Output Resistance (Ohms) High State / Low Side High State / High Side Low State / Low Side Low State / High Side Pulse Width Out (ns) 9 9 High Side Low Side IXYS reserves the right to change limits, test conditions, and dimensions. -

13 IXD Fig. Fig. Normalized PW Out vs. PW In (Low Side) Normalized PW Out vs. PW In (High Side) V IN = V SUPPLY = V, V, V C LOAD = pf V IN = V SUPPLY = V, V, V C LOAD = pf.. V V Normalized PW Out.... Normalized PW Out.... V Pulse Width In (ns) Pulse Width In (ns) IXYS CORPORATION All rights reserved

14 IXD IXDP Package IXDS Package IXDP Package IXDS Package 9 SYM A A IHES MIN MAX MILLIMETERS MIN MAX BSC BSC NOTE: This drawing will meet all dimensions requirement of JEDEC MS- AB. IXYS Corporation Bassett St; Santa Clara, CA 9 Tel: -9-; Fax: sales@ixys.net IXYS Semiconductor GmbH Edisonstrasse ; D-; Lampertheim Tel: +9---; Fax: marcom@ixys.de IXYS reserves the right to change limits, test conditions, and dimensions.