FAN7391 High-Current, High & Low-Side, Gate-Drive IC

Transcription

1 FAN7391 High-Current, High & Low-Side, Gate-Drive IC Features Floating Channels for Bootstrap Operation to +6 V Typically 4.5 A / 4.5 A Sourcing / Sinking Current Driving Capability Common-Mode dv/dt Noise-Canceling Circuit Built-in Under-Voltage Lockout for Both Channels Built-in Advanced Input Filter Matched Propagation Delay for Both Channels Logic (V SS ) and Power (COM) Ground ±5 V Offset 3.3 V and 5 V Input Logic Compatible Output In-Phase with Input Applications Plasma Display Panel (PDP) Sustain Driver High-Intensity Discharge (HID) Lamp Ballast Switching Mode Power Supply (SMPS) Motor Driver Related Resources AN-676 Design and Application Guide of Bootstrap Circuit for High-Voltage Gate-Drive IC AN-952 Design Guide for Selection of Bootstrap Components AN-812 Recommendations to Avoid Short Pulse Width Issues in HVIC Gate Driver Applications Description June 214 The FAN7391 is a monolithic high- and low-side gatedrive IC, which can drive high-speed MOSFETs and IGBTs that operate up to +6 V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Fairchild s high-voltage process and common-mode noise-canceling techniques provide stable operation of the high-side driver under high-dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to V S =-9.8 V (typical) for V BS =15 V. The advanced input filter of provides protection against short-pulsed input signals caused by noise. The UV circuit prevents malfunction when V DD and V BS are lower than the specified threshold voltage. The high-current and low-output voltage-drop feature makes this device suitable for the PDP sustain pulse driver, motor driver, switching mode power supply, and high-power DC-DC converter applications. 14-SOP Ordering Information Part Number Package Operating Temperature Range Packing Method FAN7391MX 14-SOP -4 C ~ 125 C Tape & Reel FAN7391 Rev. 1..

2 Typical Application Circuit Controller V SS LIN 15V RBOOT DBOOT FAN7391 LIN V SS 4 NC COM NC 14 V B V S 11 NC 1 NC 9 V DD NC 8 CBOOT Up to 6V R1 Q1 R2 OUTPUT C1 R3 Q2 R4 Figure 1. Application Circuit for Half-Bridge Load FAN7391 Rev.1 Internal Block Diagram FAN V B UV PULSE GENERATOR 1 Advanced Input Filter NOISE CANCELLER 2K R R S Q DRIVER V S 7 V DD UV LIN 2 DELAY VSS/COM LEVEL SHIFT DRIVER 6 2K V SS 3 5 COM Pin 4, 8, 9, 1 and 14 are no connection FAN7391 Rev.1 Figure 2. Functional Block Diagram FAN7391 Rev

3 Pin Configurations 1 14 NC LIN 2 13 V SS NC 4 COM 5 6 V B 3 12 FAN V S NC NC V DD 7 8 NC FAN7391 Rev.1 Figure 3. Pin Assignments (Top View) Pin Definitions 14-Pin Name Description 1 Logic Input for High-Side Gate Driver Output 2 LIN Logic Input for Low-Side Gate Driver Output 3 V SS Logic Ground 5 COM Low-Side Driver Return 6 Low-Side Driver Output 7 V DD Low-Side and Logic Part Supply Voltage 11 V S High-Voltage Floating Supply Return 12 High-Side Driver Output 13 V B High-Side Floating Supply 4, 8, 9, 1, 14 NC No Connect FAN7391 Rev

4 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T A =25 C, unless otherwise specified. Symbol Characteristics Min. Max. Unit V S High-Side Floating Supply Offset Voltage V B -V SHUNT V B +.3 V V B High-Side Floating Supply Voltage V V High-Side Floating Output Voltage, Pin V S -.3 V B +.3 V V DD Low-Side and Logic Fixed Supply Voltage -.3 V SHUNT V V Low-Side Output Voltage, Pin -.3 V DD +.3 V V IN Logic Input Voltage ( and LIN) V SS -.3 V DD +.3 V V SS Logic Ground V DD -25 V DD +.3 V dv S /dt Allowable Offset Voltage Slew Rate 5 V/ns (1)(2)(3) P D Power Dissipation 1. W JA Thermal Resistance, Junction-to-Ambient 11 C/W T J Junction Temperature +15 C T STG Storage Temperature +15 C Notes: 1. Mounted on 76.2 x x 1.6 mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection; and JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. 3. Do not exceed P D maximum under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit V B High-Side Floating Supply Voltage V S +1 V S +2 V V S High-Side Floating Supply Offset Voltage 6-V DD 6 V V High-Side Output Voltage V S V B V V DD Low-Side and Logic Supply Voltage 1 2 V V Low-Side Output Voltage COM V DD V V IN Logic Input Voltage ( and LIN) V SS V DD V T A Operating Ambient Temperature C PW Pulse Width of Logic Input for High-Side Gate Driver 1 ns FAN7391 Rev

5 Electrical Characteristics V BIAS (V DD, V BS )=15. V, V S =V SS =COM, T A =25 C, unless otherwise specified. The V IL, V IH, and I IN parameters are referenced to V SS /COM and are applicable to the respective input signals and LIN. The V O and I O parameters are referenced to COM and V S is applicable to the respective output signals and. Symbol Characteristics Condition Min. Typ. Max. Unit POWER SUPPLY SECTION (V DD AND V BS ) V DDUV+ V BSUV+ V DDUV- V BSUV- V DDUVH V BSUVH V DD and V BS Supply Under-Voltage Positive-Going Threshold V DD and V BS Supply Under-Voltage Negative-Going Threshold V DD and V BS Supply Under-Voltage Lockout Hysteresis Voltage I LK Offset Supply Leakage Current V B =V S =6 V 5 I QBS Quiescent V BS Supply Current V IN = V or 5 V 45 8 I QDD Quiescent V DD Supply Current V IN = V or 5 V I PBS Operating V BS Supply Current f IN =2 khz, rms value I PDD Operating V DD Supply Current f IN =2 khz, rms value SHUNT REGULATOR SECTION V V DD and V BS Shunt Regulator Clamping SHUNT Voltage GIC INPUT SECTION (, LIN) V DD =Sweep or V BS =Sweep, I SHUNT =5 ma.5 V µa µa V V IH Logic "1" Input Voltage 2.5 V IL Logic "" Input Voltage 1.2 V I IN+ Logic "1" Input Bias Current V IN =5 V 25 5 I IN- Logic "" Input Bias Current V IN = V µa R IN Input Pull-Down Resistance 1 2 k GATE DRIVER OUTPUT SECTION (, ) V OH High-Level Output Voltage, V BIAS -V O No Load 1. V V OL Low-Level Output Voltage, V O No Load 35 mv I O+ Output High, Short-Circuit Pulsed Current (4) V O = V, V IN =5 V,PW<1 µs I O- Output Low, Short-Circuit Pulsed Current (4) V O =15 V, V IN = V,PW<1 µs A Allowable Negative V V S Pin Voltage for S Signal Propagation to V V SS - COM V SS -COM/COM-V SS Voltage Endurability -5 5 V Note: 4. This parameter guaranteed by design. Dynamic Electrical Characteristics V BIAS (V DD, V BS )=15. V, V S =V SS =COM= V, C L =1 pf, and T A =25 C unless otherwise specified. Symbol Characteristics Test Condition Min. Typ. Max. Unit t on Turn-On Propagation Delay V S = V t off Turn-Off Propagation Delay V S = V MT Delay Matching, HS & LS Turn-On/Off 15 5 t r Turn-On Rise Time 25 5 t f Turn-Off Fall Time 2 45 ns FAN7391 Rev

6 Typical Characteristics t ON t R Figure 4. Turn-On Propagation Delay t OFF t F Figure 5. Turn-Off Propagation Delay 1 1 Figure 6. Turn-On Rise Time Figure 7. Turn-Off Fall Time MT ON 3 2 MT OFF Figure 8. Turn-On Delay Matching Figure 9. Turn-Off Delay Matching FAN7391 Rev

7 Typical Characteristics (Continued) I QDD [ A] I PDD [ma] [A] Figure 1. Quiescent V DD Supply Current I QBS [ A] I PBS [ma] [A] Figure 11. Quiescent V BS Supply Current Figure 12. Operating V DD Supply Current Figure 13. Operating V BS Supply Current V DDUV+ 8.5 V DDUV Figure 14. V DD UV+ Figure 15. V DD UV- FAN7391 Rev

8 Typical Characteristics (Continued) V BSUV+ V OH [mv] Figure 16. V BS UV+ V BSUV- V OL [mv] Figure 17. V BS UV Figure 18. High-Level Output Voltage Figure 19. Low-Level Output Voltage V IH V IL Figure 2. Logic HIGH Input Voltage Figure 21. Logic W Input Voltage FAN7391 Rev

9 Typical Characteristics (Continued) T FLT I IN+ [ A] Figure 22. Logic Input High Bias Current V S Figure 23. Allowable Negative V S Voltage Figure 24. Input Filtering Time of FAN7391 Rev

10 Switching Time Definitions LIN COM Figure 25. Switching Time Test Circuit (Referenced 14-SOP) LIN 1nF 1 1nF Figure 26. Input / Output Timing Diagram V B 2 LIN 12 1µF 1nF VSS V S 13 V DD 7 FAN7391 Rev V 15V 1µF 1nF FAN739 Rev.1 LIN 5% 5% t on t r t off t f 9% 9% 1% 1% FAN739 Rev.1 Figure 27. Switching Time Waveform Definitions LIN 5% 5% 1% 1% MT MT 9% FAN739 Rev.1 9% Figure 28. Delay Matching Waveform Definitions FAN7391 Rev

11 Applications Information 1. Advanced Input Noise Filter Figure 29 shows the input noise filter method, which has symmetry duration between the input signal (t INPUT ) and the output signal (t OUTPUT ) and helps to reject noise spikes and short pulses. This input filter is applied to the. The upper pair of waveforms (Example A) shows an input signal duration (t INPUT ) much longer than input filter time (t FLT ); it is approximately the same duration between the input signal time (t INPUT ) and the output signal time (t OUTPUT ). The lower pair of waveforms (Example B) shows an input signal time (t INPUT ) slightly longer than input filter time (t FLT ); it is approximately the same duration between input signal time (t INPUT ) and the output signal time (t OUTPUT ). Example A Example B t FLT t FLT t INPUT t INPUT toutput toutput Output duration is same as input duration Figure 29. Input Noise Filter Definition Example A Example B Figure 3. Noise Rejecting Input Filter Definition Figure 31 shows the characteristics of the input filters while receiving narrow ON and OFF pulses. If input signal pulse duration, PW, is less than input filter time, t FLT ; the output pulse, PW, is zero. The input signal is rejected by input filter. Once the input signal pulse duration, PW, exceeds input filter time, t FLT, the output pulse durations, PW, matches the input pulse durations, PW. FAN7391 input filter time, t FLT, is about 5ns for the high-side outputs. Output Pulse Width (W) (HIGH) t FLT t FLT t FLT t FLT t FLT t FLT Input Pulse Output Pulse 2. Short-Pulsed Input Noise Rejection Method The Advanced input filter circuitry provides protection against short-pulsed input signals caused by noise. If the input signal duration is less than input filter time (t FLT ), the output does not change states. Example A and B of the Figure 3 show the input and output waveforms with short-pulsed noise spikes with a duration less than input filter time; the output does not change states Input Pulse Width Figure 31. Input Filter Characteristic of Narrow ON FAN7391 Rev

12 Package Dimensions 6. PIN ONE INDICATOR 1.75 MAX (.33) A.25 M.25.1 B C B A C.1 C LAND PATTERN RECOMMENDATION SEE DETAIL A R.1 R X 45 GAGE PLANE.36 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-12, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P6X145-14M E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV (1.4) DETAIL A SCALE: 2:1 SEATING PLANE Figure Lead, Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Always visit Fairchild Semiconductor s online packaging area for the most recent packing drawings: FAN7391 Rev

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