ADVANCE DATA DCP1 VCC 1 COM 2 FMIN 3 VB 8 HO 7 VS 6 IR2520D CVCC RFMIN CVCO

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1 ADVANCE DATA Data Sheet No. PD0 IR0D(S) ADAPTIVE BALLAST CONTROL IC Features 00V Driver Integrated Bootstrap Diode Adaptive zero-voltage switching (Z) Internal Crest Factor Over-Current Protection 0 to VDC Voltage Controlled Oscillator Programmable minimum frequency Micropower Startup Current (0uA) Internal.V zener clamp on Vcc Small DIP/SO Package Packages -Lead PDIP Lead SOIC Description The IR0D is a complete adaptive ballast controller and 00V half-bridge driver integrated into a single IC for fluorescent lighting applications. The IC includes adaptive zero-voltage switching (Z), internal crest factor over-current protection, as well as an integrated bootstrap diode. The heart of this IC is a voltage controlled oscillator with externally programmable minimum frequency. All of the necessary ballast features are integrated in a small -pin DIP or SOIC package. Typical Application Diagram L RSUPPLY C BR DCP F C C RFMIN FMIN 3 IR0D LO M CBOOT M LRES CCP CFL LAMP CRES C DCP C3 Please note that this data sheet contains advance information which could change before product is released to production.

2 IR0D(S) ADVANCE DATA Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V B High side floating supply voltage -0.3 V S High side floating supply offset voltage V B - V B V High side floating output voltage V S V B V V LO Low side output voltage -0.3 V CC I OMAX Maximum allowable output current (,LO) due to external ma power transistor miller effect V Voltage controlled oscillator input voltage -0.3 V CC V I CC Supply current (Note ) -0 0 ma dv S /dt Allowable offset voltage slew rate -0 0 V/ns P D Package power T A + C -Lead PDIP PD=(T JMAX -T A )Rth JA -Lead SOIC 0. W Rth JA Thermal resistance, junction to ambient -Lead PDIP -Lead SOIC 00 C/W T J Junction temperature - 0 T S Storage temperature - 0 C T L Lead temperature (soldering, 0 seconds) 300 Note : This IC contains a zener clamp structure between the chip and, which has a nominal breakdown voltage of.v. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol Definition Min. Max. Units V BS High side floating supply voltage V CC - 0. V CLAMP V S Steady state high side floating supply offset voltage - 00 V V CC Supply voltage V CCUV+ V CLAMP I CC Supply current Note 0 ma R FMIN Minimum frequency setting resistance 0 00 kω V pin voltage 0 V T J Junction temperature - C Note : Enough current should be supplied into the pin to keep the internal.v zener clamp diode on this pin regulating its voltage, VCLAMP.

3 ADVANCE DATA IR0D(S) Electrical Characteristics V CC = V BS = V BIAS = V +/- 0.V, C LO =C =000pF and T A = C unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions Supply Characteristics V CCUV+ V CC and V BS supply undervoltage positive going 3. V CC rising from OV threshold V CCUV- V CC and V BS supply undervoltage negative going 0. V threshold V UVHYS V CC supply undervoltage lockout hysteresis. I QCCUV UVLO quiescent current V CC = V µa I QCCFLT Fault mode quiescent current 0 I QCC Quiescent V CC supply current. V CC = V ma I CC0k Current, f = 0kHz. V CLAMP V CC Zener clamp voltage... V I CC = 0mA Floating Supply Characteristics I QBS 0 Quiescent V BS supply current - 0 V = V S µa I QBS Quiescent V BS supply current V = V B V BSMIN Minimum required V BS voltage for proper. V ILK Offset supply leakage current 0 µa V B = V S = 00V Oscillator I/O Characteristics F (min) Minimum oscillator frequency 3 V CO =V,R FMIN=K khz F (max) Maximum oscillator frequency 00 V CO =0V,R FMIN=K D Oscillator duty cycle 0 % T DLO LO output deadtime. T D output deadtime. I PH Preheat mode & frequency sweep mode.0 I ADPT Adaptive mode lead changing current.0 V FLT Fault mode & UVLO mode lead voltage 0 V Gate Driver Output Characteristics V OL Low level output voltage ( or LO) 00 V HL High level output voltage ( or LO) 00 T RISE Turn on rise time 0 T FALL Turn off fall time 00 µs µa mv mv 3

4 IR0D(S) ADVANCE DATA Electrical Characteristics V CC = V BS = V BIAS = V +/- 0.V, C LO =C =000pF and T A = C unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions Protection Characteristics V CSCF Crest factor peak-to-average fault factor 3 Minimum Frequency Setting Characteristics V FMIN FMIN lead voltge during normal operation. V V FMINFLT FMIN lead voltge during fault mode 0.0 V Block Diagram Integrated Bootstrap Diode FMIN 3 Voltage Controlled Oscillator High- & Low Side - Driver Fault Logic LO Adaptive Z & MCS Sensing

5 ADVANCE DATA IR0D(S) Lead Definitions Lead Assignments Symbol Description V CC FMIN LO V S Supply voltage IC power and signal ground Minimum frequency setting Voltage controlled oscillator input Low side gate driver output High side floating return High side gate driver output FMIN 3 IR0D(S) LO High side gate driver floating supply

6 IR0D(S) ADVANCE DATA State Diagram Power Turned On < 0.V (UVLO-) UVLO Mode / - Off I QCC 0µA = 0V FMIN = 0V Crest Factor > 3 (for 0 cycles of LO) FAULT Mode / - Off = 0V IQCC 0µA FMIN = 0V > 3.V (UVLO+) Frequency Sweep Mode FMIN =.V ramps up, frequency ramps down Crest Factor > V Z > V < 0.V (UVLO-) Lamp Ignites RUN Mode =.V, Frequency = fmin or If non-z detected then decreases and frequency increases to maintain Z

7 ADVANCE DATA IR0D(S) Functional Description Under-voltage Lock-Out Mode The under-voltage lockout mode (UVLO) is defined as the state the IR0D is in when is below the turn-on threshold of the IC. The IR0D under voltage lock-out is designed to maintain an ultra low supply current (<00uA), and to guarantee that the IR0D is fully functional before the high and low side output drivers are activated. The start-up capacitor, C, is charged by current through supply resistor, R SUPPLY, minus the start-up current drawn by the IR0D. This resistor is chosen to provide sufficient current to supply the IR0D from the DC bus. C should be large enough to hold the voltage at Vcc above the UVLO threshold for one half cycle of the line voltage as it will only be charged at the peak. Once the capacitor voltage on V CC reaches the start-up threshold, the IR0D turns on and then and LO start oscillating. An internal bootstrap diode between Vcc and and external supply capacitor, C BOOT, determine the supply voltage for the high side driver circuitry. An external charge pump circuit consisting of a capacitor, C CP, and two diodes, D CP and D CP, supplies the voltage for the low side driver circuitry. To guarantee that the high-side supply is charged up before the first pulse on pin, the first pulse from the output drivers comes from the LO pin. LO may oscillate several times until - exceeds US+ (9 Volts) and the high-side driver is enabled. During UVLO mode, the high and low-side driver outputs, and LO, are both low and pin is pulled down to for resetting the starting frequency to the maximum. Frequency Sweep Mode When exceeds UVLO+ threshold, the IR0D enters frequency sweep mode. An internal current source charges the external capacitor on pin, C, and the voltage on pin starts ramping up linearly. The frequency ramps down towards the resonance frequency of the high-q ballast output stage causing the lamp voltage and load current to increase. When the voltage on pin exceeds V, the crest factor detection and zero-voltage switching (Z) are both enabled. The voltage on pin continues to increase and the frequency keeps decreasing until the lamp ignites, or, the internal crest factor threshold is reached (see Fault Mode section). If the lamp ignites successfully, the voltage on pin continues to increase until it internally limits at.v. The frequency stops decreasing and stays at the minimum frequency as programmed by an external resistor, RFMIN, on pin FMIN. The minimum frequency should be set below the high-q resonance frequency of the ballast output stage to ensure that the frequency ramps through resonance for lamp ignition. The desired preheat time can be set by adjusting the slope of the ramp with the external capacitor, C. US (+) BU V (+) S DCP RSUPPLY C C CLAMP DBOOT Driver DCP LO M CBOOT M Output I LOA D CCP C FMIN 3 RFMIN C. V O DBOOT Fault Logic Driver Sensing M CBOOT LO M Output CCP I LOAD US (-) DCP Load Return V BU (-) S DCP Load Return Figure, Frequency sweep circuitry Figure, Start-up circuitry

8 IR0D(S) ADVANCE DATA Run Mode Fault Mode The frequency decreases during the frequency sweep mode until the lamp ignites and the ballast output stage becomes a low-q RCL circuit. The frequency then deceases further until the pin voltage limits at.v and the minimum frequency is reached. The resonant inductor, resonant capacitor, DC bus voltage and minimum frequency determine the running lamp power. The IC stays at this minimum frequency unless non-zero-voltage switching (non-z) is detected at the pin. If the voltage has not slewed entirely to during the deadtime such that there is voltage across the external low-side switch before LO turns-on, then the system is operating too close to resonance and destructive non-z capacitive mode switching occurs. To correct for this, a pulse of current is sinked from the pin to discharge the external capacitor, C, slightly causing the frequency to increase. The capacitor then charges up during the rest of the cycle slowly due to an internal current source. The frequency is therefore trying to decrease towards resonance by charging the capacitor and the adaptive Z circuit nudges the frequency back up slightly above resonance when non-z occurs. The circuit then remains in this closed-loop adaptive Z mode during running and maintains Z operation with changing line conditions, component tolerance variations and lamp/load variations. The 00V fabrication process used in the development of this IC allows for the pin to be accurately measured with an internal high-voltage MOSFET for zero volts during the nonoverlapping deadtime, while withstanding the high DC bus voltage during other portions of the switching cycle when the high-side MOSFET is turned on and is at the DC bus potential. BUS V (+) C C O O.V Fault Logic DBOOT Driver DCP M CBOOT LO M Output CCP I LOAD Should a lamp non-strike condition occur where the filaments are intact but the lamp does not ignite, the lamp voltage and output stage current will increase during the ignition ramp until the resonant inductor saturates or capacitive mode switching occurs. To detect this, the IC performs a measurement of the pin during the on-time of the LO pin. The voltage at the pin during the on-time of pin LO is determined by the current flowing through the on-resistance (RDSon) of the external low-side MOSFET. The RDSon of the external low-side MOSFET therefore serves as the current-sensing resistor and serves as the current sensing pin on the IC. Sensing the half-bridge current in this way eliminates the need for an external current-sensing resistor and an additional current-sensing pin on the IC. An internal high-voltage MOSFET is turned on when is low (when the external low-side MOSFET is on ) for performing the current sensing, and is turned off during the rest of the switching cycle for withstanding the high-voltage when is equal to the DC bus voltage (when the external high-side MOSFET is on ). Since the RDSon has a positive temperature coefficient, the IC performs an internal crest factor measurement for detecting excessive dangerous currents or inductor saturation which can occur during a lamp non-strike fault condition. Performing the crest factor measurement provides a relative current measurement which cancels temperature and/or tolerance variations of the RDSon of the external low-side half-bridge MOSFET. Should the peak current during the on-time of LO exceed a threshold of 3 times the average current for approximately 0 switching cycles of LO, the IC will enter Fault Mode and both gate driver outputs will be latched low. To reset the IC back to frequency sweep mode must be recycled below and above the internal UVLO thresholds. Should an open filament lamp fault occur, hard-switching will occur at the half-bridge. The crest factor circuit will detect this condition as well and after approximately 0 cycles of the fault occurance the IC will enter Fault Mode and both gate driver outputs will be latched low. To reset the IC back to frequency sweep mode must be recycled below and above the internal UVLO thresholds V BUS (-) Adaptive ZVMCS Logic Sensing Figure 3, Z circuitry DCP Load Return

9 ADVANCE DATA IR0D(S) Case outlines -Lead PDIP (MS-00AB) 9

10 IR0D(S) ADVANCE DATA A E X D 3 e B H 0. [.00] A. [.] 3X. [.00] FOOTPRINT X 0. [.0] X. [.00] DIM INC HES MILLIMETERS MIN MAX MIN MAX A A b c D E e.00 BASIC. BASIC e.0 BASIC 0.3 BASIC H K L y e A C y K x X b A 0. [.00] C A B 0.0 [.00] X L X c NOTES:. DIMENSIONING & TOLERANCING PER ASME Y.M-99.. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SWN IN MILLIMETERS [INCHES].. OUTLINE CONFORMS TO JEDEC OUTLINE MS-0AA. Lead SOIC DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0. [.00]. DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0. [.00]. DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE (MS-0AA) IR WORLD HEADQUARTERS: 33 Kansas St., El Segundo, California 90 Tel: (30) -0 Data and specifications subject to change without notice. 3/9/