FAN7392 High-Current, High- and Low-Side, Gate-Drive IC

Transcription

1 FAN7392 High-Current, High- and Low-Side, Gate-Drive IC Features Floating Channel for Bootstrap Operation to +6V 3A/3A Sourcing/Sinking Current Driving Capability Common-Mode dv/dt Noise Canceling Circuit 3.3V Logic Compatible Separate Logic Supply (V DD ) Range from 3.3V to 2V Under-Voltage Lockout for V CC and V BS Cycle-by-Cycle Edge-Triggered Shutdown Logic Matched Propagation Delay for Both Channels Outputs In-phase with Input Signals Available in 14-DIP and 16-SOP (Wide) Packages Applications High-Speed Power MOSFET and IGBT Gate Driver Server Power Supply Uninterrupted Power Supply (UPS) Telecom System Power Supply Distributed Power Supply Motor Drive Inverter Description July 29 The FAN7392 is a monolithic high- and low-side gate drive IC, that can drive high-speed MOSFETs and IGBTs that operate up to +6V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Fairchild s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to V S =-9.8V (typical) for V BS =15V. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic. The UV circuit prevents malfunction when V CC and V BS are lower than the specified threshold voltage. The high-current and low-output voltage drop feature makes this device suitable for halfand full-bridge inverters, like switching-mode power supply and high-power DC-DC converter applications. 14-PDIP 16-SOP Ordering Information Part Number FAN7392N FAN7392M FAN7392MX Operating Temperature Range -4 C to +125 C Package Eco Status Packing Method 14-PDIP Tube 16-SOP RoHS Tube Tape and Reel For Fairchild s definition of Eco Status, please visit: FAN7392 Rev. 1..2

2 Typical Application Diagrams Up to 6V Q1 15V R1 8 NC 7 Controller SD 9 V DD V B 6 CBOOT V S 5 DBOOT 11 SD NC 4 RBOOT 12 V CC 3 15V C1 13 V SS COM 2 Q2 R2 14 NC 1 Figure 1. Typical Application Circuit (Referenced 14-DIP) Load Up to 6V Q1 15V 9 NC 8 R1 NC V B 7 11 V DD V S 6 CBOOT Load 12 NC 5 DBOOT Controller SD 13 SD NC 4 RBOOT 14 V CC 3 15V 15 V SS COM 2 C1 Q2 16 NC 1 R2 Figure 2. Typical Application Circuit (Referenced 16-SOP) FAN7392 Rev

3 Internal Block Diagram V DD 9 V SS 12 SD SCHMITT TRIGGER INPUT CYCLE-By-CYCLE EDGE TRIGGERED SHUTDOWN HS(ON/OFF) LS(ON/OFF) Pin 4, 8, and 14 are no connection PULSE GENERATOR VSS/COM LEVEL SHIFT NOISE CANCELLER UV UV R R S Q DELAY Figure 3. Functional Block Diagram (Referenced 14-Pin) DRIVER DRIVER V B V S V CC COM 7 V B V DD SCHMITT TRIGGER INPUT HS(ON/OFF) PULSE GENERATOR NOISE CANCELLER UV R R S Q DRIVER 8 6 V S 14 UV 3 V CC SD 13 CYCLE-By-CYCLE EDGE TRIGGERED SHUTDOWN LS(ON/OFF) VSS/COM LEVEL SHIFT DELAY DRIVER 1 V SS 15 2 COM Pin 4, 5, 9, and 16 are no connection Figure 4. Functional Block Diagram (Referenced 16-SOP) FAN7392 Rev

4 Pin Configuration Pin Definitions COM V CC 3 NC 4 V S NC COM V V CC SS FAN NC 4 11 SD NC 5 V S NC 2 15 V SS V V B 6 B 7 9 V DD NC NC 14-Pin 16-Pin Name Description 1 1 Low-Side Driver Output 2 2 COM Low-Side Return 3 3 V CC Low-Side Supply Voltage 5 6 V S High-Voltage Floating Supply Return 6 7 V B High-Side Floating Supply 7 8 High-Side Driver Output 9 11 V DD Logic Supply Voltage 12 Logic Input for High-Side Gate Driver Output SD Logic Input for Shutdown Function Logic Input for Low-Side Gate Driver Output V SS Logic Ground 4,8,14 4, 5, 9,, 16 NC No Connect FAN7392M SD V DD (a) 14-DIP (b) 16-SOP (Wide Body) Figure 5. Pin Configurations (Top View) NC FAN7392 Rev

5 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T A =25 C unless otherwise specified. Symbol Characteristics Min. Max. Unit V B High-Side Floating Supply Voltage V V S High-Side Floating Offset Voltage V B -25. V B +.3 V V High-Side Floating Output Voltage V S -.3 V B +.3 V V CC Low-Side Supply Voltage V V Low-Side Floating Output Voltage -.3 V CC +.3 V V DD Logic Supply Voltage -.3 V SS +25. V V SS Logic Supply Offset Voltage V CC -25. V CC +.3 V V IN Logic Input Voltage (, and SD) V SS -.3 V DD +.3 V dv S /dt Allowable Offset Voltage Slew Rate ±5 V/ns P D Power Dissipation (1, 2, 3) 14-PDIP SOP 1.3 W θ JA Thermal Resistance 14-PDIP SOP 95 C/W T J Maximum Junction Temperature +15 C T STG Storage Temperature C Notes: 1. Mounted on 76.2 x x 1.6mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions, natural convection; and JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. 3. Do not exceed power dissipation (P D ) under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit V B High-Side Floating Supply Voltage V S + V S +2 V V S High-Side Floating Supply Offset Voltage 6-V CC 6 V V High-Side Output Voltage V S V B V V CC Low-Side Supply Voltage 2 V V Low-Side Output Voltage V CC V V DD Logic Supply Voltage V SS +3 V SS +2 V V SS Logic Supply Offset Voltage -5 5 V V IN Logic Input Voltage V SS V DD V T A Operating Ambient Temperature C FAN7392 Rev

6 Electrical Characteristics V BIAS (V CC, V BS, V DD )=15.V, V SS =COM=V and T A =25 C, unless otherwise specified. The V IH, V IL, and I IN parameters are referenced to V SS and are applicable to the respective input leads:,, and SD. The V O and I O parameters are referenced to V S and COM and are applicable to the respective output leads: and. Symbol Characteristics Test Condition Min. Typ. Max. Unit Low-Side Power Supply Section I QCC Quiescent V CC Supply Current V IN =V or V DD 4 8 μa I QDD Quiescent V DD Supply Current V IN =V or V DD μa I PCC Operating V CC Supply Current f IN =2kHz, rms, V IN =15V PP 43 μa I PDD Operating V DD Supply Current f IN =2kHz, rms, V IN =15V PP 3 μa I SD Shutdown Supply Current S D =V DD 12 μa V V CC Supply Under-Voltage CCUV+ Positive-Going Threshold Voltage V IN =V, V CC =Sweep V V V CC Supply Under-Voltage CCUV- Negative-Going Threshold Voltage V IN =V, V CC =Sweep V V V CC Supply Under-Voltage Lockout CCUVH Hysteresis Voltage V IN =V, V CC =Sweep.4 V Bootstrapped Supply Section I QBS Quiescent V BS Supply Current V IN =V or V DD 6 13 μa I PBS Operating V BS Supply Current f IN =2kHz, rms value 5 μa V V BS Supply Under-Voltage BSUV+ Positive-Going Threshold Voltage V IN =V, V BS =Sweep V V V BS Supply Under-Voltage BSUV- Negative-Going Threshold Voltage V IN =V, V BS =Sweep V V V BS Supply Under-Voltage Lockout BSUVH Hysteresis Voltage V IN =V, V BS =Sweep.4 V I LK Offset Supply Leakage Current V B =V S =6V 5 μa Input Locic Section (,, and SD) V IH Logic 1 Input Threshold Voltage V DD =3V 2.4 V V DD =15V 9.5 V V IL Logic Input Threshold Voltage V DD =3V.8 V V DD =15V 6. V I IN+ Logic Input High Bias Current V IN =V DD 2 4 μa I IN- Logic Input Low Bias Current V IN =V 3 μa R IN Logic Input Pull-Down Resistance KΩ Gate Driver Output Section V OH High-Level Output Voltage (V BIAS - V O ) No Load (I O =A) 1.5 V V OL Low-Level Output Voltage No Load (I O =A) 2 mv I O+ Output High, Short-Circuit Pulsed Current (4) V O =V, PW µs A I O- Output Low, Short-Circuit Pulsed Current (4) V O =15V, PW µs A V SS /COM V SS -COM/COM-V SS Voltage Educability V Allowable Negative V - V S Pin Voltage for S Signal Propagation to V FAN7392 Rev

7 Dynamic Electrical Characteristics V BIAS (V CC, V BS, V DD )=15.V, V SS =COM=V, C AD =pf, T A =25 C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit t on Turn-On Propagation Delay Time V S =V ns t off Turn-Off Propagation Delay Time V S =V 15 2 ns t sd Shutdown propagation Delay Time (4) ns t r Turn-On Rise Time 25 5 ns t f Turn-Off Fall Time 2 45 ns MT Delay Matching, & Turn-On/Off 35 ns Note: 4. These parameters guaranteed by design. FAN7392 Rev

8 Typical Characteristics t ON [ns] t R [ns] Figure 6. Turn-On Propagation Delay t OFF [ns] t F [ns] Figure 7. Turn-Off Propagation Delay Figure 8. Turn-On Rise Time Figure 9. Turn-Off Fall Time 3 3 MT ON [ns] 2 MT OFF [ns] 2 Figure. Turn-On Delay Matching Figure 11. Turn-Off Delay Matching FAN7392 Rev

9 Typical Characteristics (Continued) t SD [ns] I QCC [μa] Figure 12. Shutdown Propagation Delay I IN+ [μa] I QBS [μa] Figure 13. Logic Input High Bias Current Figure 14. Quiescent V CC Supply Current Figure 15. Quiescent V BS Supply Current 8 8 I PCC [μa] 6 4 I PBS [μa] Figure 16. Operating V CC Supply Current Figure 17. Operating V BS Supply Current FAN7392 Rev

10 Typical Characteristics (Continued) V BSUV+ [V] V CCUV+ [V] Figure 18. V CC UV V CCUV- [V] V BSUV- [V] Figure 19. V CC UV Figure 2. V BS UV+ Figure 21. V BS UV V OH [V] 1. V OL [mv] Figure 22. High-Level Output Voltage Figure 23. Low-Level Output Voltage FAN7392 Rev. 1..2

11 Typical Characteristics (Continued) V IH [V] V S [V] Figure 24. Logic High Input Voltage V IL [V] Logic Threshold Voltage [V] Figure 25. Logic Low Input Voltage V IH V IL -12 Figure 26. Allowable Negative V S Voltage V DD Logic Supply Voltage [V] Figure 27. Input Logic (& ) Threshold Voltage vs. V DD Supply Voltage. VS [V] V CC =V BS COM=V T A =25 C Supply Voltage [V] Figure 28. Allowable Negative Vs Voltage for Signal Propagation to High Side vs. Supply Voltage FAN7392 Rev

12 Switching Time Definitions SD SD 15V NC V DD SD V SS NC COM Figure 29. Switching Time Test Circuit (Referenced 14-DIP) V B V S NC V CC V 1nF μf 1nF μf nf nf ( to 6V) μf 15V Shutdown Skip Figure 3. Input/Output Timing Diagram 5% 5% t ON t R t OFF t F 9% 9% % % Figure 31. Switching Time Waveform Definitions FAN7392 Rev

13 Switching Time Definitions (Continued) SD 5% t SD 9% Figure 32. Shutdown Waveform Definition 5% 5% % % MT MT 9% 9% Figure 33. Delay Matching Waveform Definitions FAN7392 Rev

14 Application Information Negative V S Transient The bootstrap circuit has the advantage of being simple and low cost, but has some limitations. The biggest difficulty with this circuit is the negative voltage present at the emitter of the high-side switching device when highside switch is turned-off in half-bridge application. If the high-side switch, Q1, turns-off while the load current is flowing to an inductive load, a current commutation occurs from high-side switch, Q1, to the diode, D2, in parallel with the low-side switch of the same inverter leg. Then the negative voltage present at the emitter of the high-side switching device, just before the freewheeling diode, D2, starts clamping, causes load current to suddenly flow to the low-side freewheeling diode, D2, as shown in Figure 34. DC+ Bus Q1 V S Q2 D1 D2 i AD i freewheeling Load Figure 36 and Figure 37 show the commutation of the load current between high-side switch, Q1, and low-side freewheelling diode, D3, in same inverter leg. The parasitic inductances in the inverter circuit from the die wire bonding to the PCB tracks are jumped together in L C and L E for each IGBT. When the high-side switch, Q1, and low-side switch, Q4, are turned on, the V S1 node is below DC+ voltage by the voltage drops associated with the power switch and the parasitic inductances of the circuit due to load current is flows from Q1 and Q4, as shown in Figure 36. When the high-side switch, Q1, is turned off and Q4, remained turned on, the load current to flows the low-side freewheeling diode, D3, due to the inductive load connected to VS1 as shown in Figure 37. The current flows from ground (which is connected to the COM pin of the gate driver) to the load and the negative voltage present at the emitter of the high-side switching device. In this case, the COM pin of the gate driver is at a higher potential than the V S pin due to the voltage drops associated with freewheeling diode, D3, and parasitic elements, L C3 and L E3. DC+ Bus LC1 Q1 VLC1 D1 D2 LC2 Q2 iad ifreewheeling Figure 34. Half-Bridge Application Circuits This negative voltage can be trouble for the gate driver s output stage, there is the possibility to develop an overvoltage condition of the bootstrap capacitor, input signal missing and latch-up problems because it directly affects the source V S pin of the gate driver, as shown in Figure 35. This undershoot voltage is called negative V S transient. LE1 VLE1 VS1 LC3 Load Q3 D3 D4 Figure 36. Q1 and Q4 Turn-On VLC4 LE3 VLE4 LE2 VS2 LC4 Q4 LE4 Q1 DC+ Bus GND LC1 LC2 Q1 Q2 D1 D2 iad ifreewheeling V S LE1 VS1 Load LE2 VS2 GND LC3 VLC3 VLC4 LC4 Freewheeling Q3 D3 D4 Q4 LE3 VLE3 VLE4 LE4 Figure 35. V S Waveforms During Q1 Turn-Off Figure 37. Q1 Turn-Off and D3 Conducting FAN7392 Rev

15 The FAN7392 has a negative V S transient performance curve, as shown in Figure 38. VS [V] Figure 38. Negative V S Transient Chracteristic Even though the FAN7392 has been shown able to handle these negative V S tranient conditions, it is strongly recommended that the circuit designer limit the negative V S transient as much as possible by careful PCB layout to minimized the value of parasitic elements and component use. The amplitude of negative V S voltage is proportional to the parasitic inductances and the turn-off speed, di/dt, of the switching device. General Guidelines Pulse Width [ns] Printed Circuit Board Layout The relayout recommended for minimized parasitic elements is as follows: Direct tracks between switches with no loops or deviation. Avoid interconnect links. These can add significant inductance. Reduce the effect of lead-inductance by lowering package height above the PCB. Consider co-locating both power switches to reduce track length. To minimize noise coupling, the ground plane should not be placed under or near the high-voltage floating side. To reduce the EM coupling and improve the power switch turn-on/off performance, the gate drive loops must be reduced as much as possible. Placement of Components The recommended placement and selection of component as follows: Place a bypass capacitor between the V DD and V SS pins. A ceramic 1µF capacitor is suitable for most applications. This component should be placed as close as possible to the pins to reduce parasitic elements. The bypass capacitor from V CC to COM supports both the low-side driver and bootstrap capacitor recharge. A value at least ten times higher than the bootstrap capacitor is recommended. The bootstrap resistor, R BOOT, must be considered in sizing the bootstrap resistance and the current developed during initial bootstrap charge. If the resistor is needed in series with the bootstrap diode, verify that V B does not fall below COM (ground). Recommended use is typically 5 ~ Ω that increase the V BS time constant. If the votage drop of of bootstrap resistor and diode is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra-fast recovery diode can be used. The bootstrap capacitor, C BOOT, uses a low-esr capacitor, such as ceramic capacitor. It is stongly recommended that the placement of components is as follows: Place components tied to the floating voltage pins (V B and V S ) near the respective high-voltage portions of the device and the FAN7392. NC (not connected) pins in this package maximize the distance between the high-voltage and low-voltage pins (see Figure 5). Place and route for bypass capacitors and gate resistors as close as possible to gate drive IC. Locate the bootstrap diode, D BOOT, as close as possible to bootstrap capacitor, C BOOT. The bootstrap diode must use a lower forward voltage drop and minimal switching time as soon as possible for fast recovery or ultra-fast diode. FAN7392 Rev

16 Physical Dimensions. (1.74) MAX.38 MIN NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-1 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y E) DRAWING FILE NAME: MKT-N14AREV7 Figure Lead Dual In-Line Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FAN7392 Rev

17 Physical Dimensions (Continued)..325 B 7.5±. PIN ONE INDICATOR 2.65 MAX 1.3±.2 A M.2±. C B A C. C 1.75 TYP TYP LAND PATTERN RECOMMENDATION SEE DETAIL A SEATING PLANE TYP X 45 NOTES: UNLESS OTHERWISE SPECIFIED (R.) (R.) 8 GAGE PLANE.25 A) THIS PACKAGE CONFORMS TO JEDEC MS-13, ISSUE E, DATED SEPT 25. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. pdip8_dim.pdf D) LANDPATTERN STANDARD: SOIC127P3X265-16L E) DRAWING FILENAME: MKT-16Brev2.4~1.27 M16BREV2 (1.4) SEATING PLANE DETAIL A SCALE: 2:1 Figure Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FAN7392 Rev

18 FAN7392 Rev