HIGH VOLTAGE HALF BRIDGE

Transcription

1 Preliminary Data Sheet No. PD0-C IR0HDC0U-P HIGH LTAGE HALF BRIDGE Features Output Power IGBT s in half-bridge configuration 00V rated breakdown voltage High side gate drive designed for bootstrap operation Matched propagation delay for both channels Independent high and low side output channels (IR0HDC0U-P) or cross-conduction prevention logic () Undervoltage lockout 5V Schmitt-triggered input logic Metal heatsink back for improved PD Description The IR0HDC0U-P / are high voltage, high speed half bridges. Proprietary HVIC and latch immune CMOS technologies, along with the power IGBT technology, enable ruggedized single package construction. The logic inputs are compatible with standard CMOS or LSTTL outputs. The front-end features an independent high and low side driver in phase with the logic compatible input signals. The output features two IGBT s in a halfbridge configuration. Propagation delays for the high and low side power IGBT s are matched to simplify use. The device can operate up to 00 volts. Product Summary (max) 00V PD (TA = 5 C ).0W VCE(ON) typ.0v Package Pin

2 IR0HDC0U-P Typical Connections HV DC Bus IR0HDC0U-P V IN TO LOAD Please note this info sheet contains advance information which may change before the product is released to production. HV DC Bus V IN TO LOAD Please note this info sheet contains advance information which may change before the product is released to production.

3 IR0HDC0U-P Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to, all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V IN High voltage supply High side floating supply absolute voltage Half-bridge output voltage -0. V IN + 0. V V IH/ V IL Logic input voltage (HIN & ) - 0. V cc + 0. VCC Low side and logic fixed supply voltage V dv/dt Peak diode recovery dv/dt.50 V/ns P D Package power T A +5 C.00 W Rth JA Thermal resistance, junction to ambient 50 Rth Jc Thermal resistance, junction to case (metal) 0 T J Junction temperature T S Storage temperature T L Lead temperature (soldering, 0 seconds) 00 C/W C Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure. For proper operation the device should be used within the recommended conditions. Symbol Definition Min. Max. Units High side floating supply absolute voltage V O + 0 V O + 0 V IN High voltage supply 00 V O Half-bridge output voltage (note ) V IN VCC Low side and logic fixed supply voltage 0 0 V IH/ V IL Logic input voltage (HIN & ) 0 VCC T A Ambient temperature -0 5 I C Continuous collector current (TC = 5 C).0 (TC = 85 C). V A Note : Logic operational for of -5 to 00V. Logic state held for of -5 to -O

4 IR0HDC0U-P Dynamic Electrical Characteristics IAS (V CC, S ) = 5V and T A = 5 C unless otherwise specified. Switching time waveform definitions are shown in figure. Refer to IC data sheets (IR0 and IR08) for further characteristics. TA = 5 o C Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay (see note ) -IR0 0 0 Vo = 0V -IR toff Turn-off propagation delay (see note ) -IR ns Vo = 00V -IR trr Reverse recovery time (FRED Diode) 8 IF = 00mA Qrr Reverse recovery charge (FRED Diode) 0 nc di/dt = 00 A/us Note : Switching times as specified and illustrated in figure are referenced to the output voltage. This is shown as in figure. Static Electrical Characteristics IAS (V CC, S ) = 5V and T A = 5 C unless otherwise specified. The and IIN parameters are referenced to. TA = 5 o C Symbol Definition Min. Typ. Max. Units Test Conditions V CCUV+ SUV+ V CCUV- SUV- V CC supply undervoltage positive going threshold V CC supply undervoltage negative going threshold V V V I QCC Quiescent V CC supply current ma I QBO Quiescent O supply current I LK Offset supply leakage C 00 = 00V I INLK Vin to leakage C C 000 I OLK leakage C C 000 V IH Logic input voltage. V IL Logic 0 input voltage 0.8 I IN+ Logic input bias current 0 0 I IN- Logic 0 input bias current µa V µa V IN = 00V, = 0V V O = 00V V CC = 0V to 0V V IN = 5V V CE (on) Collector-to-Emitter saturation voltage.0 IC = 00mA V EC Diode forward voltage. V IE = 00mA VF Bootstrap Diode forward voltage (D).5 IF = 00mA

5 IR0HDC0U-P Functional Block Diagram IR0HC0U-P IR08HC0U-P D D H O IGBT FRED0 H O IGBT FRED0 IR0 V S IR08 V S L O IGBT FRED0 L O IGBT FRED0 Lead Definitions Lead Symbol Definition V CC HIN V IN Logic and internal gate drive supply voltage. Logic input for high side half bridge output, in phase Logic input for low side half bridge output, in phase (IR0xxx) or out of phase (IR08xxx) High side gate drive floating supply High voltage supply Half bridge output Logic return and half bridge return Lead Assignments HIN V IN 5

6 IR0HDC0U-P Case Outline - pin X 5.08 (.00) X.8 (.5). (.55).8 (.5). (.5) NOTES:. Dimensioning and tolerancing per ANSI Y.5M-8. Controlling dimension: Inch. Dimensions are shown in millimeters (inches)

7 IR0HDC0U-P HIN HIN 0 t on t off Figure. Input/Output Timing Diagram Figure. Switching Time Waveform Definitions IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 05 Tel: (0) 5-05 IR EUROPEAN REGIONAL CENTRE: /5 Godstone Rd., Whyteleafe, Surrey CR 0BL, United Kingdom Tel: ++ (0) IR JAPAN: K&H Bldg., F, 0- Nishi-Ikebukuro -Chome, Toshima-Ku, Tokyo, Japan -00 Tel: IR HONG KONG: Unit 08, #F, New East Ocean Centre, No. Science Museum Road, Tsimshatsui East, Kowloon Hong Kong Tel: (85) Data and specifications subject to change without notice. 5//000