FAN73901 High- and Low-Side, Gate-Drive IC

Transcription

1 FAN7391 High- and Low-Side, Gate-Drive IC Features Floating Channels for Bootstrap Operation to +6 V Typically 2.5 A / 2.5 A Sourcing/Sinking Current Driving Capability Common-Mode dv/dt Noise Canceling Circuit Built-in Under-Voltage Lockout for Both Channels Matched Propagation Delay for Both Channels 3.3 V and 5 V Input Logic Compatible Output In-Phase with Input Applications Half-Bridge Driver HID Lamp Ballast SMPS Motor Driver Description September 213 The FAN7391 is a monolithic high- and low-side gatedrive IC, which can drive high-speed MOSFETs and IGBTs that operate up to +6 V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Fairchild s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to V S =-9.8 V (typical) for V BS =15 V. The UVLO circuit prevents malfunction when V DD and V BS are lower than the specified threshold voltage. The high current and low output voltage drop features mak sfan7391 suitable for switching power supply, motor driver, and high-power DC-DC converter applications. 8-SOP Ordering Information Part Number Package Operating Temperature Range Packing Method FAN7391M Tube 8-SOP -4C ~ 125C FAN7391MX Tape & Reel FAN7391 Rev. 1..1

2 Typical Application Circuit HIN 1 HIN Controller LIN 2 LIN 3 COM 4 LO FAN7391 V B HO V S V DD V RBOOT DBOOT CBOOT C1 R1 R3 R4 Up to 6V Q1 R2 OUTPUT Q2 Load FAN7391 Rev.1 Figure 1. Application Circuit for Half-Bridge Internal Block Diagram FAN V B UVLO HIN PULSE GENERATOR 1 NOISE CANCELLER 2K R R S Q DRIVER 7 6 HO V S 5 V DD UVLO LIN 2 DELAY DRIVER 4 LO 2K 3 COM FAN7391 Rev.1 Figure 2. Functional Block Diagram FAN7391 Rev

3 Pin Configuration Pin Definitions HIN 1 LIN 2 COM 3 LO 4 FAN7391 FAN7391 Rev.1 Figure 3. Pin Assignments (Top View) V S V DD Pin # Name Description 1 HIN Logic Input for High-Side Gate Driver Output 2 LIN Logic Input for Low-Side Gate Driver Output 3 COM Low-Side Driver Return 4 LO Low-Side Driver Output 5 V DD Low-Side and Logic Part Supply Voltage 6 V S High-Voltage Floating Supply Return 7 HO High-Side Driver Output 8 V B High-Side Floating Supply 8 V B 7 HO 6 5 FAN7391 Rev

4 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T A =25 C, unless otherwise specified. Symbol Characteristics Min. Max. Unit V S High-Side Floating Supply Offset Voltage V B -25 V B +.3 V V B High-Side Floating Supply Voltage V V HO High-Side Floating Output Voltage HO V S -.3 V B +.3 V V DD Low-Side and Logic Fixed Supply Voltage V V LO Low-Side Output Voltage LO -.3 V DD +.3 V V IN Logic Input Voltage (HIN and LIN) -.3 V DD +.3 V dv S /dt Allowable Offset Voltage Slew Rate 5 V/ns P D Power Dissipation (1)(2)(3).625 W JA Thermal Resistance, Junction-to-Ambient 2 C/W T J Junction Temperature +15 C T STG Storage Temperature +15 C Notes: 1. Mounted on 76.2 x x 1.6 mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages. 3. Do not exceed P D under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit V B High-Side Floating Supply Voltage V S +1 V S +2 V V S High-Side Floating Supply Offset Voltage 6-V DD 6 V V HO High-Side Output Voltage V S V B V V DD Low-Side and Logic Supply Voltage 1 2 V V LO Low-Side Output Voltage COM V DD V V IN Logic Input Voltage (HIN and LIN) COM V DD V T A Operating Ambient Temperature C FAN7391 Rev

5 Electrical Characteristics V BIAS (V DD, V BS )=15. V, V S =COM, T A =25C, unless otherwise specified. The V IL, V IH, and I IN parameters are referenced to COM and are applicable to the respective input signals HIN and LIN. The V O and I O parameters are referenced to COM and V S is applicable to the respective output signals HO and LO. Symbol Characteristics Test Condition Min. Typ. Max. Unit POWER SUPPLY SECTION (V DD AND V BS ) V DDUV+ V BSUV+ V DDUV- V BSUV- V DDUVH V BSUVH V DD and V BS Supply Under-Voltage Positive-Going Threshold V DD and V BS Supply Under-Voltage Negative-Going Threshold V DD and V BS Supply Under-Voltage Lockout Hysteresis Voltage V V.5 V I LK Offset Supply Leakage Current V B =V S =6 V 5 µa I QBS Quiescent V BS Supply Current V IN =V or 5 V 45 8 µa I QDD Quiescent V DD Supply Current V IN =V or 5 V µa I PBS Operating V BS Supply Current f IN =2 khz, rms value µa I PDD Operating V DD Supply Current f IN =2 khz, rms value µa LOGIC INPUT SECTION (HIN, LIN) V IH Logic "1" Input Voltage 2.5 V V IL Logic "" Input Voltage 1.2 V I IN+ Logic "1" Input Bias Current V IN =5 V 25 5 µa I IN- Logic "" Input Bias Current V IN = V µa R IN Input Pull-Down Resistance 1 2 K GATE DRIVER OUTPUT SECTION (HO, LO) V OH High-Level Output Voltage, V BIAS -V O No Load 1. V V OL Low-Level Output Voltage, V O No Load 35 mv I O+ Output High, Short-Circuit Pulsed Current (4) V O = V, V IN =5 V with PW<1 µs A I O- Output Low, Short-Circuit Pulsed Current (4) V O =15 V, V IN = V with PW<1 µs A Allowable Negative V V S Pin Voltage for S HIN Signal Propagation to HO V Note: 4. This parameter guaranteed by design. Dynamic Electrical Characteristics V BIAS (V DD, V BS )=15. V, V S =COM= V, C L =1 pf and T A =25C unless otherwise specified. Symbol Characteristics Test Condition Min. Typ. Max. Unit t on Turn-on Propagation Delay V S = V 14 2 ns t off Turn-off Propagation Delay V S = V 14 2 ns MT Delay Matching, HS & LS Turn-on/off 5 ns t r Turn-on Rise Time 25 5 ns t f Turn-off Fall Time 2 45 ns FAN7391 Rev

6 Typical Characteristics t ON [ns] Figure 4. Turn-on Propagation Delay t OFF [ns] Figure 5. Turn-off Propagation Delay t R [ns] 2 t F [ns] Figure 6. Turn-on Rise Time Figure 7. Turn-off Fall Time MT ON [ns] 3 2 MT OFF [ns] Figure 8. Turn-on Delay Matching Figure 9. Turn-off Delay Matching FAN7391 Rev

7 Typical Characteristics (Continued) I QDD [A] Figure 1. Quiescent V DD Supply Current 1 I QBS [A] Figure 11. Quiescent V BS Supply Current 8 8 I PDD [A] 6 I PBS [A] Figure 12. Operating V DD Supply Current Figure 13. Operating V BS Supply Current V DDUV+ 8.5 V DDUV Figure 14. V DD UVLO+ Figure 15. V DD UVLO- FAN7391 Rev

8 Typical Characteristics (Continued) V BSUV Figure 16. V BS UVLO+ 15 V BSUV Figure 17. V BS UVLO V OH [mv] 9 6 V OL [mv] Figure 18. High-Level Output Voltage Figure 19. Low-Level Output Voltage V IH V IL Figure 2. Logic High Input Voltage Figure 21. Logic Low Input Voltage FAN7391 Rev

9 Typical Characteristics (Continued) I IN+ [A] Figure 22. Logic Input High Bias Current V S Figure 23. Allowable Negative V S Voltage. FAN7391 Rev

10 Switching Time Definitions HIN LIN HIN LIN HO LO 1nF 1 HIN COM 1nF Figure 24. Switching Time Test Circuit V B 2 LIN HO 7 1µF 1nF 3 4 LO V S 8 V DD 5 FAN7391 Rev V 15V 1µF 1nF FAN7391 Rev.1 Figure 25. Input / Output Timing Diagram HIN LIN 5% 5% t on t r t off t f 9% 9% HO LO 1% 1% FAN7391 Rev.1 Figure 26. Switching Time Waveform Definitions HIN LIN 5% 5% 1% LO 1% HO MT MT 9% LO FAN7391 Rev.1 9% HO Figure 27. Delay Matching Waveform Definitions FAN7391 Rev

11 Mechanical Dimensions. Figure Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FAN7391 Rev

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