IR2112(S) & (PbF) HIGH AND LOW SIDE DRIVER

Transcription

1 Features Floating channel designed for bootstrap operation Fully operational to +6V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from 1 to 2V Undervoltage lockout for both channels 3.3V logic compatible Separate logic supply range from 3.3V to 2V Logic and power ground ±5V offset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Outputs in phase with inputs Also available LEAD-FREE Description HIGH AND LOW SIDE DRIVER Product Summary V OFFSET I O +/- V OUT t on/off (typ.) Delay Matching Packages The IR2112(S) is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs, down to 3.3V logic. 14-Lead PDIP Data Sheet No. PD626 Rev.R IR2112(S) & (PbF) 6V max. 2 ma / 42 ma 1-2V 1 & 15 ns 3 ns 16-Lead SOIC (wide body) (Also abailable LEAD-FREE (PbF)) The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 6 volts. Typical Connection (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. 1

2 Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35. Symbol Definition Units V B High Side Floating Supply Voltage V S High Side Floating Supply Offset Voltage V B - V B +.3 V HO High Side Floating Output Voltage V S -.3 V B +.3 V CC Low Side Fixed Supply Voltage -.3 V LO Low Side Output Voltage -.3 V CC +.3 V DD Logic Supply Voltage -.3 V SS + V SS Logic Supply Offset Voltage V CC - V CC +.3 V IN Logic Input Voltage (HIN, LIN & SD) V SS -.3 V DD +.3 dv s /dt Allowable Offset Supply Voltage Transient (Figure 2) 5 V/ns P D R THJA Package Power T A + C Thermal Resistance, Junction to Ambient (14 Lead DIP) (14 Lead DIP) 1.6 (16 Lead SOIC) (16 Lead SOIC) 1. 1 W C/W T J Junction Temperature 15 T S Storage Temperature T L Lead Temperature (Soldering, 1 seconds) 3 Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figures 36 and 37. Symbol Definition Units V B High Side Floating Supply Absolute Voltage V S + 1 V S + 2 V S High Side Floating Supply Offset Voltage Note 1 6 V C V HO High Side Floating Output Voltage V S V B V CC Low Side Fixed Supply Voltage 1 2 V LO Low Side Output Voltage VCC V DD Logic Supply Voltage V SS + 3 V SS + 2 V SS Logic Supply Offset Voltage -5 (Note 2) 5 V V IN Logic Input Voltage (HIN, LIN & SD) V SS V DD T A Ambient Temperature -4 1 C Note 1: Logic operational for V S of -5 to +6V. Logic state held for V S of -5V to -V BS. (Please refer to the Design Tip DT97-3 for more details). Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD. 2

3 Dynamic Electrical Characteristics V BIAS (V CC, V BS, V DD ) = 15V, C L = 1 pf, T A = C and V SS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3. Symbol Definition Figure Units Test Conditions t on Turn-On Propagation Delay V S = V t off Turn-Off Propagation Delay V S = 6V t sd Shutdown Propagation Delay ns V S = 6V t r Turn-On Rise Time t f Turn-Off Fall Time MT Delay Matching, HS & LS Turn-On/Off 3 Static Electrical Characteristics V BIAS (V CC, V BS, V DD ) = 15V, T A = C and V SS = COM unless otherwise specified. The V IN, V TH and I IN parameters are referenced to V SS and are applicable to all three logic input leads: HIN, LIN and SD. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Definition Figure Units Test Conditions V IH Logic 1 Input Voltage V IL Logic Input Voltage V OH High Level Output Voltage, V BIAS - V O 14 1 I O = A mv V OL Low Level Output Voltage, V O 15 1 I O = A I LK Offset Supply Leakage Current 16 5 V B = V S = 6V I QBS Quiescent V BS Supply Current 17 6 V IN = V or V DD I QCC Quiescent V CC Supply Current V IN = V or V DD µa I QDD Quiescent V DD Supply Current V IN = V or V DD I IN+ Logic 1 Input Bias Current V IN = V DD I IN- Logic Input Bias Current V IN = V V BSUV+ V BS Supply Undervoltage Positive Going Threshold V BSUV- V BS Supply Undervoltage Negative Going Threshold V V CCUV+ V CC Supply Undervoltage Positive Going Threshold V CCUV- V CC Supply Undervoltage Negative Going Threshold I O+ Output High Short Circuit Pulsed Current 26 2 V O = V, V IN = V DD PW 1 µs ma I O- Output Low Short Circuit Pulsed Current V O = 15V, V IN = V PW 1 µs 3 V

4 Functional Block Diagram V B HO V S V CC LO COM Lead Definitions Symbol Description V DD Logic supply HIN Logic input for high side gate driver output (HO), in phase SD Logic input for shutdown LIN Logic input for low side gate driver output (LO), in phase V SS Logic ground V B High side floating supply HO High side gate drive output V S High side floating supply return V CC Low side supply LO Low side gate drive output COM Low side return Lead Assignments 14 Lead DIP 16 Lead SOIC (Wide Body) (Also available LEAD-FREE (PbF) IR2112 IR2112S Part Number 4

5 <5 V/ns Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition Figure 5. Shutdown Waveform Definitions Figure 6. Delay Matching Waveform Definitions 5

6 Turn-On Delay Time (ns) Temperature Turn-On Delay Time (ns) VCC/VBS Supply Voltage (V) Figure 7A. Turn-On Time vs. Temperature Figure 7B. Turn-On Time vs. VCC/VBS Supply Voltage 4 Turn-On Delay Time (ns) Turn-Off Delay Time (ns) VDD Supply Voltage (V) Figure 7C. Turn-On Time vs. VDD Supply Voltage Figure 8A. Turn-Off Time vs. Temperature 4 Turn-Off Delay Time (ns) Turn-OFF Delay Time (ns) VCC/VBS Supply Voltage (V) VDD Supply Voltage (V) Figure 8B. Turn-Off Time vs. VCC/VBS Supply Voltage Figure 8C. Turn-Off Time vs. VDD Supply Voltage 6

7 Shutdown Delay Time (ns) Figure 9A. Shutdown Time vs. Temperature 4 Shutdown Delay Time (ns) VCC/VBS Supply Voltage (V) Figure 9B. Shutdown Delay Time vs. VCC/VBS Supply Voltage Shutdown Delay Tim e (ns) VDD Supply V oltage (V ) Turn-On rise Time (ns) Figure 9C. Shutdown Time vs. VDD Supply Voltage Figure 1A. Turn-On Rise Time vs. Temperature Turn-On Rise Time (ns) VBIAS Supply Voltage (V) Figure 1B. Turn-On Rise Time vs. Voltage Turn-On Fall Time (ns) Figure 11A Turn-On Fall Time vs. Temperature 7

8 Turn-O ff Fall Tim e (ns) VBIA S S upply V oltage (V ) Figure 11B. Turn-Off Fall Time vs. Voltage Logic "1" Input Threshold (V) Figure 12A. Logic I Input Threshold vs. Temperature Logic " 1 " Input Treshold Logic "" Input Threshold (V) VDD Logic S upply V olta g e (V ) Figure 12B. Logic I Input Threshold vs. Voltage Figure 13A. Logic Input Threshold vs. Temperature Logic " " Input Treshold (V) VDD Logic Supply Voltage (V) High LevelO utput V oltage (V ) M ax Tem perature Figure 13B. Logic Input Threshold vs. Voltage Figure 14A. High Level Output vs. Temperature 8

9 High LevelO u tp u t V o lta g e (V ) M ax Low Level Output Voltage (V) VBAIS S upply V otage (V ) Figure 14B. High Level Output vs. Voltage Figure 15A. Low Level Output vs. Temperature Low Level Output Voltage (V) VBIAS Supply Votage (V) Offset Supply Leakage Current (ua) Figure 15B. Low Level Output vs. Voltage Figure 16A. Offset Supply Current vs. Temperature Offset Supply Leakage Current (ua) VB Boost Voltage (v) VBS Supply Current (ua) Figure 16B. Offset Supply Current vs. Voltage Figure 17A. VBS Supply Current vs. Temperature 9

10 1 3 VBS Supply Current (ua) Vcc Supply Current (ua) VBS Floating Supply Voltage (V) Figure 17B. VBS Supply Current vs. Voltage Figure 18A. VCC Supply Current vs. Temperature 3 12 Vcc Supply Current (ua) VDD Supply Current (ua) Vcc Fixed Supply Voltage (V) Figure 18B. VCC Supply Current vs. Voltage Figure 19A. VDD Supply Current vs. Temperature VDD Supply Current (ua) VDD Logic Supply Voltage (V) Logic "1 " Input Bias Current (ua) Figure 19B. VDD Supply Current vs. VDD Voltage Figure 2A. Logic I Input Current vs. Temperature 1

11 Logic " 1" Input Bias Current (ua) VDD Logic S upply V oltage (V ) Figure 2B. Logic 1 Input Current vs. VDD Voltage Logic "" Input Bias Current (ua) Figure 21A. Logic Input Current vs. Temperature Logic "" Input Bias Current (ua) VDD Supply Voltage (V) VBS Undervoltage Lockout +(V) Figure 21B. Logic Input Current vs. VDD Voltage Figure 22. VBS Undervoltage (+) vs. Temperature VBS Undervoltage Lockout -(V) Figure 23. VBS Undervoltage (-) vs. Temperature Temperature ( C) Figure 24. VCC Undervoltage (-) vs. Temperature Vcc Undervoltage Lockout +(V) 11

12 11 5 VCC Undervoltage Lockout - (V) Output source Current (ma) Figure. VCC Undervoltage (-) vs. Temperature Figure 26A. Output Source Current vs. Temperature Output source Current (ma) VBIAS Supply Voltage (V) Output Sink Current (ma) Figure 26B. Output Source Current vs. Voltage Figure 27A. Output Sink Current vs. Temperature Output Sink Current (ma) VBIAS Supply Voltage (V) Figure 27B. Output Sink Current vs. Voltage 12

13 V 1 32V 1 Junction V 1V Junction V 1V 1E+2 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) Figure 28. IR2112 TJ vs. Frequency (IRFBC2) RGATE = 33Ω, VCC = 15V 1E+2 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) Figure 29. IR2112 TJ vs. Frequency (IRFBC3) RGATE = 22Ω, VCC = 15V 15 32V 15 32V 14V 1V V Junction 1 5 1V Junction 1 5 1E+2 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) Figure 3. IR2112 TJ vs. Frequency (IRFBC4) RGATE = 15Ω, VCC = 15V 1E+2 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) Figure 31. IR2112 TJ vs. Frequency (IRFPE5) RGATE = 1Ω, VCC = 15V 15 32V 15 32V 14V 1 1 Junction V 1V Junction 1 5 1V 1E+2 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) Figure 32. IR2112S TJ vs. Frequency (IRFBC2) RGATE = 33Ω, VCC = 15V 1E+2 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) Figure 33. IR2112S TJ vs. Frequency (IRFBC3) RGATE = 22Ω, VCC = 15V 13

14 15 32V 15 32V 14V 1V 1 14V 1V 1 Junction 1 5 Junction 1 5 1E+2 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) 1E+2 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) Figure 34. IR2112S TJ vs. Frequency (IRFBC4) RGATE = 15Ω, VCC = 15V Figure 35. IR2112S TJ vs. Frequency (IRFPE5) RGATE = 1Ω, VCC = 15V. 2. VS Offset Supply Voltage (V) VSS Logic Supply Offset Voltage (V) VBS Floating Supply Voltage (V) Figure 36. Maximum VS Negative Offset vs. VBS Supply Voltage VCC Fixed Supply Voltage (V) Figure 37. Maximum VSS Positive Offset vs. VCC Supply Voltage 14

15 Case outline 14-Lead PDIP (MS-1AC) 16-Lead SOIC (wide body) (MS-13AA) 15

16 LEADFREE PART MARKING INFORMATION Part number IRxxxxxx Date code YWW? IR logo Pin 1 Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 2-2 ORDER INFORMATION Basic Part (Non-Lead Free) 14-Lead PDIP IR2112 order IR Lead SOIC IR2112S order IR2112S Leadfree Part 14-Lead PDIP IR2112 order IR2112PbF 16-Lead SOIC IR2112S order IR2112SPbF IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245 Tel: (31) This product has been qualified per industrial level Data and specifications subject to change without notice. 4/2/