IRS2104(S)PbF HALF-BRIDGE DRIVER. Features. Product Summary. Packages. Description. Typical Connection V OFFSET. 600 V max. 130 ma/270 ma 10 V - 20 V

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1 Features Floating channel designed for bootstrap operation Fully operational to + V Tolerant to negative transient voltage, dv/dt immune Gate drive supply range from V to V Undervoltage lockout. V, V, and V input logic compatible Cross-conduction prevention logic Internally set deadtime High-side output in phase with input Shutdown input turns off both channels Matched propagation delay for both channels RoHS compliant Description The IRS is a high voltage, high speed power MOSFET and IGBT driver with dependent high- and lowside referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to. V Typical Connection Product Summary V OFFSET I O +/- V OUT t on/off (typ.) Deadtime (typ.) Packages Data Sheet No.PD7 HALF-BRIDGE DRIVER 8 Lead SOIC IRSS IRS(S)PbF V max. ma/7 ma V - V 8 ns/ ns ns logic. The output drivers feature a high pulse current buffer stage designed for minimum driver crossconduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates from V to V. up to V 8 Lead PDIP IRS V CC V CC V B COM V S TO AD (Refer to Lead Assignment for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

2 IRS(S) PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Units V B High-side floating absolute voltage -. V S High-side floating supply offset voltage V B - V B +. V High-side floating output voltage V S -. V B +. V CC Low-side and logic fixed supply voltage -. V Low-side output voltage -. V CC +. V Logic input voltage ( & ) -. V CC +. dv s /dt Allowable offset supply voltage transient V/ns P D Package power T A + C Rth JA Thermal resistance, junction to ambient (8 lead PDIP). (8 lead SOIC). (8 lead PDIP) (8 lead SOIC) T J Junction temperature T S Storage temperature - T L Lead temperature (soldering, seconds) V W C/W C Recommended Operating Conditions The input/output logic timing diagram is shown in Fig.. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at a V differential. Symbol Definition Units V B High-side floating supply absolute voltage V S + V S + V S High-side floating supply offset voltage Note V High-side floating output voltage V S V B V CC Low-side and logic fixed supply voltage V V Low-side output voltage V CC V Logic input voltage ( & ) V CC T A Ambient temperature - C Note : Logic operational for V S of - V to + V. Logic state held for V S of - V to -V BS. (Please refer to the Design Tip DT97- for more details).

3 IRS(S) PbF Dynamic Electrical Characteristics V BIAS (V CC, V BS ) = V, C L = pf and T A = C unless otherwise specified. Symbol Definition Units Test Conditions ton Turn-on propagation delay 8 8 V S = V toff Turn-off propagation delay V S = V tsd Shutdown propagation delay tr Turn-on rise time 7 7 tf Turn-off fall time 9 DT Deadtime, LS turn-off to HS turn-on & HS turn-on to LS turn-off MT Delay matching, HS & LS turn-on/off ns Static Electrical Characteristics V BIAS (V CC, V BS ) = V and T A = C unless otherwise specified. The V, V TH, and I parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: or. Symbol Definition Units Test Conditions V IH Logic () & Logic () input voltage. V IL Logic () & Logic () input voltage.8 V,TH+ input positive going threshold. V,TH- input negative going threshold.8 V OH High level output voltage, V BIAS - V O.. V OL Low level output voltage, V O.. I LK Offset supply leakage current V B = V S = V I QBS Quiescent V BS supply current I QCC Quiescent V CC supply current 7 I + Logic input bias current V = V I - Logic input bias current V = V V CCUV+ V CCUV- V CC supply undervoltage positive going threshold V CC supply undervoltage negative going threshold I O+ Output high short circuit pulsed current 9 I O- Output low short circuit pulsed current 7 V µa V ma V CC = V to V I O = ma V = V or V V O = V PW µs V O = V PW µs

4 IRS(S) PbF Functional Block Diagram VB HV LEVEL SHIFT PULSE R Q FILTER S VS PULSE GEN DEAD TIME & SOT-THROUGH PREVENTION UV DETECT VCC COM Lead Definitions Symbol V B V S V CC COM Description Logic input for high-side and low-side gate driver outputs ( and ), in phase with Logic input for shutdown High-side floating supply High-side gate drive output High-side floating supply return Low-side and logic fixed supply Low-side gate drive output Low-side return Lead Assignments V CC V B 8 V CC V B V S V S COM COM 8 Lead PDIP 8 Lead SOIC IRSPbF IRSSPbF

5 IRS(S) PbF () () % % ton t r toff tf 9% 9% % % Figure. Input/Output Timing Diagram Figure. Switching Time Waveform Definitions % % % t sd 9% 9% DT % DT 9% Figure. Shutdown Waveform Definitions % Figure. Deadtime Waveform Definitions () () % % % MT MT 9% Figure. Delay Matching Waveform Definitions

6 IRS(S) PbF Turn-On Delay Time (ns) 8 Turn-On Delay y Time (ns) ( ) Figure A. Turn-On Time Figure B. Turn-On Time vs. Supply Voltage Turn-On Delay Time (ns) 8 Turn-Off Delay Time (ns) Input Voltage (V) Figure C. Turn-On Time vs. Input Voltage Figure 7A. Turn-Off Time Turn-Off Delay Time (ns) Turn-Off Delay Time (ns) 8 Typ Input Voltage (V) Figure 7B. Turn-Off Time vs. Supply Voltage Figure 7C. Turn-Off Time vs. Input Voltage

7 IRS(S) PbF Shutdown Delay Time (ns) M ax Shutdown Delay Time (ns) 8 Figure 8A. Shutdown Time Figure 8B. Shutdown Time vs. Voltage Turn-On Rise Time (ns) MAX Figure 9A. Turn-On Rise Time Turn-On Rise Time (ns) ( 8 VBIAS Supply Voltage (V) Figure 9B. Turn-On Rise Time vs. Voltage Turn-Off Fall Time (ns) Figure A. Turn-Off Fall Time Turn-Off Fall Time (ns) 8 Input Voltage Figure B. Turn-Off Fall Time vs. Input Voltage 7

8 IRS(S) PbF Deadtime (ns) 8 Deadtime (ns) 8 M ax Figure A. Deadtime Figure B. Deadtime vs. Voltage Input Voltage (V) Input Voltage (V) Temperature ( o C) V BAIS Supply Voltage (V) Min FigureA. Logic "" Input Voltage Figure B. Logic "" Input Voltage vs. Supply Voltage Input Voltage (V)....8 Input Voltage (V) Figure A. Logic "" () & Logic () & Active Input Voltage 8 V cc Supply Voltage (V) Figure B. Logic "" () & Logic () & Active Input Voltage vs. Voltage 8

9 IRS(S) PbF High Level Output Voltage (V) Temperature ( o C) Figure A. High Level Output Voltage High Level Output Voltage (V) Figure B. High Level Output Voltage vs. Supply Voltage Low Level Output Voltage (V) Temperature ( o C) Figure A. Low Level Output Voltage Low Level Output Voltage (V) V BIAS Supply Voltage (V) Figure B. Low Level Output Voltage vs. Supply Voltage Offset Supply Leakage Current (µa) Offset Supply Leakage Current (µa) V B Boost Voltage (V) Figure A. Offset Supply Current Figure B. Offset Supply Current vs. Voltage 9

10 IRS(S) PbF V BS Supply Current (µa) 9 V BS Supply Current (µa) V BS Floating Supply Voltage (V) Figure 7A. V BS Supply Current Figure 7B. V BS Supply Current vs. Voltage 7 7 V cc Supply Current (µa) V cc Supply Current (µa) V cc Supply Voltage (V) Figure 8A. Vcc Supply Current Figure 8B. Vcc Supply Current vs. Voltage Logic Input Current (µa) Logic Input Current (µa) V cc Supply Voltage (V) Figure 9A. Logic"" Input Current Figure 9B. Logic"" Input Current vs. Voltage

11 IRS(S) PbF Logic Input Bias Current (µa) Max Temperature ( C) Figure A. Logic "" Input Bias Current Logic "" Input Bias C ur r ent ( µa) Max 8 Supply Voltage (V) Figure B. Logic "" Input Bias Current vs. Voltage V CC UV T hreshold +(V) Figure A. Vcc Undervoltage Threshold(+) V CC UV T hr es hol d - ( V) Figure B. Vcc Undervoltage Threshold(-) Output Source Current (ma) Figure A. Output Source Current Output Source Current (ma) 8 Figure B. Output Source Current vs. Voltage

12 IRS(S) PbF Output Sink Current (ma) 8 Output Sink Current (ma) Figure A. Output Sink Current Figure B. Output Sink Current vs. Supply Voltage Input Threshold (+) (V) Input Threshold (+) (V) Vcc Supply Voltage (V) Figure A. Input Positive Going Threshold (+) Figure B. Input Positive Going Threshold (+) vs. Supply Voltage

13 IRS(S) PbF Case Outline A E X D 8 7 e B H. [.] A. [.] X.7 [.] FOOTPRT 8X.7 [.8] 8X.78 [.7] CHES DIM M MAX A A b.. MILLIMETERS M MAX c D E e. BASIC.7 BASIC e. BASIC. BASIC H K L....7 y 8 8 e A C y K x 8X b A. [.] C A B. [.] 8X L 7 8X c NOTES:. DIMENSIONG & TOLERANCG PER ASME Y.M-99.. CONTROLLG DIMENSION: MILLIMETER. DIMENSIONS ARE SWN MILLIMETERS [CHES].. OUTLE CONFORMS TO JEDEC OUTLE MS-AA. 8 Lead SOIC DIMENSION DOES NOT CLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. DIMENSION DOES NOT CLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERG TO A SUBSTRATE (MS-AA) 8 Lead PDIP - - (MS-AB)

14 IRS(S) PbF Tape & Reel 8-lead SOIC AD ED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLG DIMENSION MM E G CARRIER TAPE DIMENSION FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A B.9... C D E F G. n/a.9 n/a H F D E C B A G H REEL D IMENSIONS FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A B C D E F n /a 8. n /a.7 G H

15 IRS(S) PbF LEADFREE PART MARKG FORMATION Part number Date code IRxxxxxx S YWW? IR logo Pin Identifier? MARKG CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - digit SPN code) Assembly site code Per SCOP - ORDER FORMATION 8-Lead PDIP IRSPbF 8-Lead SOIC IRSSPbF 8-Lead SOIC Tape & Reel IRSSTRPbF The SOIC-8 is MSL qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 9 Tel: () -7 Data and specifications subject to change without notice. /7/

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