IRS2130D/IRS21303D/IRS2132D

Transcription

1 Data Sheet No. PD6256 reva IRS213D/IRS2133D/IRS2132D 3-PHASE BRIDGE DRIER Features Floating channel designed for bootstrap operation Fully operational to +6 Tolerant to negative transient voltage, d/dt immune Gate drive supply range from 1 to 2 Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Three Independent half-bridge drivers Matched propagation delay for all channels 2.5 logic compatible Outputs out of phase with inputs Cross-conduction prevention logic All parts are LEAD-FREE Integrated bootstrap diode function Product Summary OFFSET I O +/- (min.) OUT t on/off (typ.) Deadtime (typ.) 6 max. 2 ma / 42 ma Applications: *Motor Control *Air Conditioners/ Washing Machines *General Purpose Inverters *Micro/Mini Inverter Drives 1 2 (IRS213(,2)D) 13 2 (IRS2133D) 5 ns 2. µs (IRS213D).7 µs (IRS213(2,3)D) Description Packages The IRS213(, 3, 2)D are high voltage, high speed power MOSFET and IGBT drivers with three independent high and low side referenced output channels. Proprietary HIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 2.5 logic. A ground-referenced operational amplifier provides analog feedback of bridge current via an external current sense resistor. A current trip function which terminates all six outputs is also derived from this resistor. An open drain FAULT signal indicates if an over-current or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation 28-Lead SOIC 28-Lead PDIP delays are matched to simplify use at high frequencies. The 44-Lead PLCC w/o 12 Leads floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which operates up to 6. Typical Connection 1

2 IRS213D/IRS2133D/IRS2132D (J&S)PbF Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to SO. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Zener clamps are included between CC & SO (25 ), CC & SS (2), and Bx & Sx (2 ). Symbol Definition Min. Max. Units B1,2,3 High side floating supply voltage S1,2,3 High side floating offset voltage B1,2,3-2 B1,2,3 +.3 HO1,2,3 High side floating output voltage S1,2,3 -.3 B1,2,3 +.3 CC Low side and logic fixed supply voltage SS Logic ground CC - 2 CC +.3 LO1,2,3 Low side output voltage -.3 CC +.3 ( SS + 15) or IN Logic input voltage ( HIN1,2,3, LIN1,2,3 & ITRIP) ( SS -.3 CC +.3), whichever is lower FLT FAULT output voltage SS -.3 CC +.3 CAO Operational amplifier output voltage SS -.3 CC +.3 CA- Operational amplifier inverting input voltage SS -.3 CC +.3 d S /dt Allowable offset supply voltage transient 5 /ns (28 lead PDIP) 1.5 P D Package power T A +25 C (28 lead SOIC) 1.6 W (44 lead PLCC) 2. (28 lead PDIP) 83 R th,ja Thermal resistance, junction to ambient (28 lead SOIC) 78 C/W (44 lead PLCC) 63 T J Junction temperature 15 T S Storage temperature C T L Lead temperature (soldering, 1 seconds) 3 2

3 Recommended Operating Conditions IRS213D/IRS2133D/IRS2132D (J&S)PbF The input/output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltage referenced to SO. The S offset rating is tested with all supplies biased at a 15 differential. Symbol Definition Min. Max. Units B1,2,3 High side floating supply voltage IRS213(,2)D S1,2,3 +1 IRS2133D S1,2,3 +13 S1,2,3 +2 S1,2,3 High side floating offset voltage Note 1 6 HO1,2,3 High side floating output voltage S1,2,3 B1,2,3 CC Low side and logic fixed supply voltage IRS213(,2)D 1 IRS2133D 13 2 SS Logic ground -5 5 LO1,2,3 Low side output voltage CC IN Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP) SS SS + 5 FLT FAULT output voltage SS CC CAO Operational amplifier output voltage SS SS + 5 CA- Operational amplifier inverting input voltage SS SS + 5 T A Ambient temperature C Note 1: Logic operational for S of ( SO - 8 ) to ( SO + 6 ). Logic state held for S of ( SO - 8 ) to ( SO BS ). (Please refer to the Design Tip DT97-3 for more details). Note 2: The CAO pin and all input pins (except CA-) are internally clamped with a 5.2 zener diode. 3

4 Static Electrical Characteristics IRS213D/IRS2133D/IRS2132D (J&S)PbF BIAS ( CC, BS1,2,3 ) = 15, SO1,2,3 = SS and T A = 25 C unless otherwise specified. The IN, TH, and I IN parameters are referenced to SS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The O and I O parameters are referenced to SO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol Definition Min. Typ. Max. Units Test Conditions IH Logic input voltage (OUT = LO) 2.2 IL Logic 1 input voltage (OUT = HI).8 IT,TH+ ITRIP input positive going threshold m OH High level output voltage, BIAS - O 1 IN =, Io= 2 ma OL Low level output voltage, O 4 m IN = 5, Io= 2 ma I LK Offset supply leakage current 5 B = S = 6 µa I QBS Quiescent BS supply current 3 7 I QCC Quiescent CC supply current 4 6 ma IN = I IN+ Logic 1 input bias current (OUT = HI) 3 4 I IN- Logic input bias current (OUT = LO) 22 3 µa IN = 5 I ITRIP+ High ITRIP bias current 5 1 ITRIP = 5 I ITRIP- Low ITRIP bias current 1 na ITRIP = BSU+ BS supply undervoltage IRS213(,2)D positive going threshold IRS2133D BSU- BS supply undervoltage IRS213(,2)D negative going threshold IRS2133D 9 11 CCU+ CC supply undervoltage IRS213(,2)D positive going threshold IRS2133D CCU- CC supply undervoltage IRS213(,2)D negative going threshold IRS2133D 9 11 CCUH Hysteresis IRS213(,2)D.3 IRS2133D 2 BSUH Hysteresis IRS213(,2)D.4 IRS2133D 2 R on, FLT FAULT low on-resistance Ω I O+ Output high short circuit pulsed current 2 25 O =, IN = PW 1 µs ma I O- Output low short circuit pulsed current 42 5 O = 15, IN = 5 PW 1 µs R BS Integrated bootstrap diode resistance 2 Ω OS Operational amplifier input offset voltage 1 m SO = CA- =.2 I CA- CA- input bias current 5 na CA- = 2.5 Operational amplifier common mode CMRR TBD 8 SO = CA- =.1 & rejection ratio 1.1 db Operational amplifier power supply PSRR TBD 75 SO = CA- =.2 rejection ratio CC = 1 & 2 OH,AMP Operational amplifier high level output voltage CA- =, SO =1 OL,AMP Operational amplifier low level output voltage 3 m CA- = 1, SO = Note: Please refer to Feature Description section for integrated bootstrap functionality information. 4

5 IRS213D/IRS2133D/IRS2132D (J&S)PbF Static Electrical Characteristics - (Continued) BIAS ( CC, BS1,2,3 ) = 15, SO1,2,3 = SS and T A = 25 C unless otherwise specified. The IN, TH, and I IN parameters are referenced to SS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The O and I O parameters are referenced to SO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol Definition Min. Typ. Max. Units Test Conditions I SRC,AMP Operational amplifier output source current 4 7 CA- =, SO =1 CAO = 4 I SNK,AMP Operational amplifier output sink current CA- = 1, SO = CAO = 2 ma Operational amplifier output high short circuit I O+,AMP 1 CA- =, SO =5 current CAO = Operational amplifier output low short circuit I O-,AMP 4 CA- = 5, SO = current CAO = 5 Dynamic Electrical Characteristics BIAS ( CC, BS1,2,3 ) = 15, SO1,2,3 = SS, C L = 1 pf, T A = 25 C unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions t on Turn-on propagation delay t off Turn-off propagation delay t r Turn-on rise time t f Turn-off fall time S1,2,3 = to 6 t itrip ITRIP to output shutdown propagation delay t bl ITRIP blanking time 4 t flt ITRIP to FAULT indication delay ns t flt, in Input filter time (all six inputs) 325 LIN1,2,3 to FAULT clear time IRS213(,2)D t fltclr LIN1,2,3 & HIN1,2,3 to FAULT clear time IRS2133D DT Deadtime IRS213D IRS213(2,3)D SR+ Operational amplifier slew rate (+) 5 1 SR- Operational amplifier slew rate (-) /µs 1 input step NOTE: For high side PWM, HIN pulse width must be > 1.5 µs. 5

6 IRS213D/IRS2133D/IRS2132D (J&S)PbF Fig. 1. Input/Output Timing Diagram Fig. 2. Deadtime Waveform Definitions Fig. 3. Input/Output Switching Time Waveform Definitions 6

7 IRS213D/IRS2133D/IRS2132D (J&S)PbF Fig. 4. Overcurrent Shutdown Switching Time Waveform Definitions Fig. 5. Input Filter Function Fig. 6. Diagnostic Feedback Operational Amplifier Circuit 7

8 IRS213D/IRS2133D/IRS2132D (J&S)PbF Lead Definitions Symbol HIN1,2,3 LIN1,2,3 FAULT CC ITRIP CAO CA- SS B1,2,3 HO1,2,3 S1,2,3 LO1,2,3 SO Description Logic input for high side gate driver outputs (HO1,2,3), out of phase Logic input for low side gate driver output (LO1,2,3), out of phase Indicates over-current or undervoltage lockout (low side) has occurred, negative logic Low side and logic fixed supply Input for over-current shutdown Output of current amplifier Negative input of current amplifier Logic ground High side floating supply High side gate drive output High side floating supply return Low side gate drive output Low side return and positive input of current amplifier Lead Assignments 8

9 IRS213D/IRS2133D/IRS2132D (J&S)PbF Functional Block Diagram 9

10 IRS213D/IRS2133D/IRS2132D (J&S)PbF Functional Block Diagram 1

11 IRS213D/IRS2133D/IRS2132D (J&S)PbF 1 Features Description 1.1 Integrated Bootstrap Functionality The IRS213(,3,2)D family embeds an integrated bootstrap FET that allows an alternative drive of the bootstrap supply for a wide range of applications. There is one bootstrap FET for each channel and it is connected between each of the floating supply ( B1, B2, B3 ) and CC (see Fig. 7). The bootstrap FET of each channel follows the state of the respective low side output stage (i.e., bootfet is ON when LO is high, it is OFF when LO is low), unless the B voltage is higher than approximately 1.1( CC ). In that case the bootstrap FET stays off until the B voltage returns below that threshold (see Fig. 8). - at a very high PWM duty cycle due to the bootstrap FET equivalent resistance (R BS, see page 4). In these cases, better performances can be achieved by using the IRS213(,3,2) non D version with an external bootstrap network. 2 PCB Layout Tips 2.1 Distance from H to L oltage The IRS213(,3,2)J package lacks some pins (see page 8) in order to maximizing the distance between the high voltage and low voltage pins. It s strongly recommended to place the components tied to the floating voltage in the respective high voltage portions of the device ( B1,2,3, S1,2,3 ) side. 2.2 Ground Plane To minimize noise coupling ground plane must not be placed under or near the high voltage floating side. 2.3 Gate Drive Loops Current loops behave like an antenna able to receive and transmit EM noise (see Fig. 9). In order to reduce EM coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-togate parasitic capacitance. The parasitic autoinductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. th~17 cc=15 Phase voltage Fig. 7. Simplified BootFet Connection BX ( CC) HO X (LO X ) gate resistance Gate Drive Loop I GC GE CGC LO SX ( s ) Bootstrap FET state BootFet ON BootFet OFF Fig. 8. State Diagram BootFet ON Bootstrap FET is suitable for most PWM modulation schemes and can be used either in parallel with the external bootstrap network (diode + resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of the external bootstrap network may have some limitations in the following situations: - when used in non-complementary PWM schemes (typically 6-step modulations) Fig. 9. Antenna Loops 2.4 Supply Capacitors Supply capacitors must be placed as close as possible to the device pins ( CC and SS for the ground tied supply, B and S for the floating supply) in order to minimize parasitic inductance/resistance. 11

12 IRS213D/IRS2133D/IRS2132D (J&S)PbF 2.5 Routing and Placement Power stage PCB parasitic may generate dangerous voltage transients for the gate driver and the control logic. In particular it s recommended to limit phase voltage negative transients. In order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector distance and low side emitter to negative bus rail stray inductance. See DT4-4 at for more detailed information. 12

13 IRS213D/IRS2133D/IRS2132D (J&S)PbF Figures 1-4 provide information on the experimental performance of the IRS2132DS HIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three temperatures (-4 ºC, 25 ºC, and 125 ºC) in order to generate the experimental () curve. The line labeled consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). Turn-on Propagation Delay (ns) Turn-off Propagation Delay (ns) Fig. 1. Turn-On Propagation Delay vs. Temperature Fig. 11. Turn-Off Propagation Delay vs. Temperature Turn-On Rise Time (ns) Turn-Off fall Time (ns) Fig. 12. Turn-On Rise Time vs. Temperature Fig. 13. Turn-Off Fall Time vs. Temperature 13

14 IRS213D/IRS2133D/IRS2132D (J&S)PbF DT Propagation Delay (ns) TiTRIP Propagation Delay (ns) Fig. 14. DT Propagation Delay vs. Temperature Fig. 15. T ITRIP Propagation Delay vs. Temperature ITRIP to FAULT Propagation Delay (ns) FAULT Low On Resistance ( Ohm) Fig. 16. ITRIP to FAULT Propagation Delay vs. Temperature Fig.17. FAULT Low On Resistance vs. Temperature CC Quiescent Supply Current (ma) BS Quiescent Supply Current (ua) Fig. 18. CC Quiescent Current vs. Temperature Fig. 19. BS Quiescent Current vs. Temperature 14

15 IRS213D/IRS2133D/IRS2132D (J&S)PbF CCU+ Threshold () CCU- Threshold () Fig. 2. CCU+ Threshold vs. Temperature Fig. 21. CCU- Threshold vs. Temperature BSU+ Threshold () BSU- Threshold () Fig. 22. BSU+ Threshold vs. Temperature Fig. 23. BSU- Threshold vs. Temperature ITRIP Positive Going Threshold (m) 75 EXP ITRIP Negative Going Threshold (m) Fig. 24. ITRIP Positive Going Threshold vs. Temperature Fig. 25. ITRIP Negative Going Threshold vs. Temperature 15

16 IRS213D/IRS2133D/IRS2132D (J&S)PbF Output High Short Circuit Pulsed Current (ma) Output Low Short Circuit Current (ma) Fig. 26. Output High Short Circuit Pulsed Current vs. Temperature Fig. 27. Output Low Short Circuit Current vs. Temperature "HIGH" ITRIP Bias Current (ua) "LOW" ITRIP Bias Current (na) Fig. 28. "High" ITRIP Bias Current vs. Temperature Fig. 29. "Low" ITRIP Bias Current vs. Temperature OH,AMP () 4 2 OL,AMP (m) Fig. 3. OH,AMP vs. Temperature Fig. 31. OL,AMP vs. Temperature 16

17 IRS213D/IRS2133D/IRS2132D (J&S)PbF 2 5 SR+,AMP (/us) SR-,AMP (/us) Fig. 32. SR+,AMP vs. Temperature Fig. 33. SR-,AMP vs. Temperature ISNK,AMP (ma) ISRC,AMP (ma) Fig. 34. I SNK,AMP vs. Temperature Fig. 35. I SRC,AMP vs. Temperature IO-,AMP (ma) IO+,AMP (ma) Fig. 36. I O-,AMP vs. Temperature Fig. 37. I O+,AMP vs. Temperature 17

18 IRS213D/IRS2133D/IRS2132D (J&S)PbF OS,AMP (m) PSRR (db) Fig. 38. OS,AMP vs. Temperature Fig. 39. PSRR vs. Temperature CMRR (db) Fig. 4. CMRR vs. Temperature 18

19 IRS213D/IRS2133D/IRS2132D (J&S)PbF Case Outlines 19

20 IRS213D/IRS2133D/IRS2132D (J&S)PbF Case Outlines 2

21 IRS213D/IRS2133D/IRS2132D (J&S)PbF LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIMENSION IN MM E G CARRIER TAPE DIMENSION FOR 28SOICW Metric Imperial Code Min Max Min Max A B C D E F G 1.5 n/a.59 n/a H F D E C B A G H REEL DIMENSIONS FOR 28SOICW Metric Imperial Code Min Max Min Max A B C D E F n/a 3.4 n/a G H

22 IRS213D/IRS2133D/IRS2132D (J&S)PbF LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIMENSION IN MM E G CARRIER TAPE DIMENSION FOR 44PLCC Metric Imperial Code Min Max Min Max A B C D E F G 2. n/a.78 n/a H F D E C B A G H REEL DIMENSIONS FOR 44PLCC Metric Imperial Code Min Max Min Max A B C D E F n/a 38.4 n/a G H

23 IRS213D/IRS2133D/IRS2132D (J&S)PbF ORDER INFORMATION 28-Lead PDIP IRS213DPbF 28-Lead PDIP IRS2133DPbF 28-Lead PDIP IRS2132DPbF 28-Lead SOIC IRS213DSPbF 28-Lead SOIC IRS2133DSPbF 28-Lead SOIC IRS2132DSPbF 44-Lead PLCC IRS2132DJPbF 44-Lead PLCC IRS2133DJPbF 44-Lead PLCC IRS2132DJPbF 28-Lead SOIC Tape & Reel IRS213DSTRPbF 28-Lead SOIC Tape & Reel IRS2133DSTRPbF 28-Lead SOIC Tape & Reel IRS2132DSTRPbF 44-Lead PLCC Tape & Reel IRS213DJTRPbF 44-Lead PLCC Tape & Reel IRS2133DJTRPbF 44-Lead PLCC Tape & Reel IRS2132DJTRPbF WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 9245 Tel: (31) This part has been qualified per industrial level Data and specifications subject to change without notice.5/19/