IR2105 HALF BRIDGE DRIVER. Features. Product Summary. Packages. Description. Typical Connection

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1 Features Floating channel designed for bootstrap operation Fully operational to +6V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from to 2V Undervoltage lockout V Schmitt-triggered input logic Cross-conduction prevention logic Internally set deadtime High side output in phase with input Match propagation delay for both channels Description The IR2 is a high voltage, high speed power MOSFET and IGBT driver with dependent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL outputs. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates from to 6 volts. Typical Connection Data Sheet No. PD639J IR2 HALF BRIDGE DRIVER Product Summary V OFFSET 6V max. I O +/- 3 ma / 27 ma V OUT - 2V t on/off (typ.) 68 & ns Deadtime (typ.) 2 ns Packages 8 Lead PDIP 8 Lead SOIC up to 6V V CC IN V CC IN COM V B V S TO AD

2 IR2 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Units V B High side floating absolute voltage V S High side floating supply offset voltage V B - 2 V B +.3 V High side floating output voltage V S -.3 V B +.3 V CC Low side and logic fixed supply voltage V Low side output voltage -.3 V CC +.3 V IN Logic input voltage -.3 V CC +.3 dv s /dt Allowable offset supply voltage transient V/ns P D Package power T A +2 C (8 Lead DIP). (8 Lead SOIC).62 W Rth JA Thermal resistance, junction to ambient (8 Lead DIP) 2 C/W (8 Lead SOIC) 2 T J Junction temperature T S Storage temperature - C T L Lead temperature (soldering, seconds) 3 V Recommended Operating Conditions The input/output logic timing diagram is shown in figure. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at V differential. Symbol Definition Units V B High side floating supply absolute voltage V S + V S + 2 V S High side floating supply offset voltage Note 6 V High side floating output voltage V S V B V CC Low side and logic fixed supply voltage 2 V V Low side output voltage V CC V IN Logic input voltage V CC T A Ambient temperature - 2 C Note : Logic operational for V S of - to +6V. Logic state held for V S of -V to -V BS. 2

3 IR2 Dynamic Electrical Characteristics V BIAS (V CC, V BS ) = V, C L = pf and T A = 2 C unless otherwise specified. Symbol Definition Units Test Conditions t on Turn-on propagation delay V S = V toff Turn-off propagation delay 22 V S = 6V t r Turn-on rise time 7 t f Turn-off fall time 9 DT Deadtime, LS turn-off to HS turn-on & 2 6 HS turn-on to LS turn-off MT Delay matching, HS & LS turn-on/off 6 ns Static Electrical Characteristics V BIAS (V CC, V BS ) = V and T A = 2 C unless otherwise specified. The V IN, V TH and I IN parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: or. Symbol Definition Units Test Conditions V IH Logic () & Logic () Input Voltage 3 V CC = V to 2V V IL Logic () & Logic () Input Voltage.8 V V CC = V to 2V V OH High Level Output Voltage, V BIAS - V O I O = A mv V OL Low Level Output Voltage, V O I O = A I LK Offset Supply Leakage Current V B = V S = 6V I QBS Quiescent V BS Supply Current 3 V IN = V or V I QCC Quiescent V CC Supply Current 27 µa V IN = V or V I IN+ Logic Input Bias Current 3 V IN = V I IN- Logic Input Bias Current V IN = V V CCUV+ V CC Supply Undervoltage Positive Going Threshold V CCUV- V CC Supply Undervoltage Negative Going V Threshold I O+ Output High Short Circuit Pulsed Current 3 2 V O = V ma PW µs I O- Output Low Short Circuit Pulsed Current V O = V PW µs 3

4 IR2 Functional Block Diagram V B IN DEAD TIME PULSE GEN HV LEVEL SHIFT PULSE FILTER R S Q V S UV DETECT V CC DEAD TIME COM Lead Definitions Lead Symbol Description IN V B V S V CC COM Logic input for high and low side gate driver outputs ( and ), in phase with High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return Lead Assignments COM COM 8 Lead PDIP 8 Lead SOIC IR2 IR2S

5 IR2 8 Lead PDIP Lead SOIC -2 8

6 IR2 IN IN() IN() % % t on t r t off t f 9% 9% % % Figure. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions IN () IN % % IN () % % 9% DT 9% % DT MT % 9% MT % Figure 3. Deadtime Waveform Definitions Figure. Delay Matching Waveform Definitions 6

7 IR2 Turn-On Delay Time (ns) Turn-On Delay Time (ns) Figure 6A. Turn-On Time Figure 6B. Turn-On Time vs Voltage Turn-Off Delay Time (ns) 3 2 Max. Ty p. Turn-Off Delay Time (ns) Figure 7A. Turn-Off Time Figure 7B. Turn-Off Time vs Voltage Turn-On Rise Time (ns) Turn-On Rise Time (ns) Figure 9A. Turn-On Rise Time Figure 9B. Turn-On Rise Time vs Voltage 7

8 IR2 2 2 Turn-Off Fall Time (ns) Turn-Off Fall Time (ns) Max Figure A. Turn Off Fall Time Figure B. Turn Off Fall Time vs Voltage Deadtime (ns) Figure A. Deadtime Deadtime (ns) Figure B. Deadtime vs Voltage Input Voltage (V) Input Voltage (V) Figure2A. Logic "" () & Logic "" () Input Voltage Figure 2B. Logic "" () & Logic "" () Input Voltage vs Voltage 8

9 IR2 Input Voltage (V) Input Voltage (V) Max Vcc Supply Voltage (V) Figure 3A. Logic ""() & Logic ""() Input Voltage Figure 3B. Logic ""() & Logic ""() Input Voltage vs Voltage Low Level Output Voltage (V) High Level Output Voltage (V) Figure A. High Level Output Figure A. Low Level Output High Level Output Voltage (V) Low Level Output Voltage (V) Vcc Supply Voltage (V) Figure B. High Level Output vs Voltage Vcc Supply Voltage (V) Figure B. Low Level Output vs Voltage 9

10 IR2 Offset Supply Leakge Current (µa) Offset Supply Leakge Current (µa) VB Boost Voltage (V) Figure 6A. Offset Supply Current Figure 6B. Offset Supply Current vs Voltage VBS Supply Current (µa) Ty p VBS Supply Current (µa) VBS Floating Supply Voltage (V) Figure 7A. VBS Supply Current Figure 7B. VBS Supply Current vs Voltage VCC Supply Current (µa) VCC Supply Current (µa) Vcc Supply Voltage (V) Figure 8A. Vcc Supply Current Figure 8B. Vcc Supply Current vs Voltage

11 IR2 3 3 Logic Input Current (µa) 2 2 Max Ty p Logic Input Current (µa) Vcc Supply Voltage (V) Figure 9A. Logic "" Input Current Figure 9B. Logic "" Input Current vs Voltage Logic Input Current (µa) Figure 2A. Logic "" Input Current vs Temperature Logic Input Current (µa) 3 2 Max Vcc Supply Voltage (V) Figure 2B. Logic "" Input Current vs Voltage VCC UV Threshold +(V) Ty p VCC UV Threshold -(V) Figure 2A. Vcc Undervoltage Threshold(+) Figure 2B. Vcc UndervoltageThreshold (-)

12 IR2 Output Source Current (ma) 3 Ty p Output Source Current (ma) Figure 22A. Output Source Current Figure 22B. Output Source Current vs Voltage Output Sink Current (ma) Figure 23A. Output Sink Current Output Sink Current (ma) Figure 23B. Output Sink Current vs Voltage WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 92 Tel: (3) IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR JAPAN: K&H Bldg., 2F, 3- Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 7-2 Tel: IR NG KONG: Unit 38, #F, New East Ocean Centre, No. 9 Science Museum Road, Tsimshatsui East, Kowloon, Hong Kong Tel: (82) Data and specifications subject to change without notice. /29/99 2