200V HO V DD V B HIN SD HIN SD V S TO LOAD LIN V CC V SS LIN COM LO

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1 Data Sheet No. PD6195-E Features Floating channel designed for bootstrap operation Fully operational to Tolerant to negative transient voltage, dv/dt immune Gate drive supply range from 1 to V Undervoltage lockout for both channels 3.3V logic compatible Separate logic supply range from 3.3V to V Logic and power ground ±5V offset CMOS Schmitt-triggered inputs with pull-down Shut down input turns off both channels Matched propagation delay for both channels Outputs in phase with inputs Also available LEAD-FREE Applications Audio Class D amplifiers High power DC-DC SMPS converters Other high frequency applications HIGH AND LOW SIDE DRIVER Product Summary V OFFSET I O +/- V OUT t on/off Delay Matching Description The IR1 is a high power, high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels, ideal for Audio Class D and DC-DC converter applications. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to volts. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Typical Connection. 3.A / 3.A. 1 - V 95 & 65 ns. 15 ns. Packages 14-Lead PDIP 16-Lead SOIC HO V DD V DD V B HIN SD HIN SD V S TO LOAD LIN LIN V CC V SS V SS COM V CC LO (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. 1

2 Absolute Maximum Ratings Absolute imum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V B High side floating supply voltage V S High side floating supply offset voltage V B - 25 V B +.3 V HO High side floating output voltage V S -.3V B +.3 V CC Low side fixed supply voltage V LO Low side output voltage -.3V CC +.3 V DD Logic supply voltage -.3V SS + 25 V SS Logic supply offset voltage V CC - 25 V CC +.3 V IN Logic input voltage (HIN, LIN & SD) V SS -.3V DD +.3 dv s /dt Allowable offset supply voltage transient (figure 2) V/ns P D R THJA Package power T A +25 C Thermal resistance, junction to ambient (14 lead DIP) (14 lead DIP) (16 lead SOIC) (16 lead SOIC) 1.25 W C/W T J Junction temperature T S Storage temperature -55 T L Lead temperature (soldering, 1 seconds) 3 Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in figures 24 and 25. Symbol Definition Min. Max. Units V B High side floating supply absolute voltage V S + 1 V S + V S High side floating supply offset voltage Note 1 V C V HO High side floating output voltage V S V B V CC Low side fixed supply voltage 1 V LO Low side output voltage VCC V DD Logic supply voltage V SS + 3V SS + V SS Logic supply offset voltage -5 (Note 2) 5 V V IN Logic input voltage (HIN, LIN & SD) V SS V DD T A Ambient temperature C Note 1: Logic operational for V S of -4 to +. Logic state held for V S of -4V to -V BS. Note 2: When V DD < 5V, the minimum V SS offset is limited to -V DD. (Please refer to the Design Tip DT97-3 for more details). 2

3 Dynamic Electrical Characteristics V BIAS (V CC, V BS, V DD ) = 15V, C L = pf, T A = 25 C and V SS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3. Symbol Definition Figure Min. Typ. Max. Units Test Conditions t on Turn-on propagation delay V S = V t off Turn-off propagation delay V S = t sd Shutdown propagation delay V S = ns t r Turn-on rise time 1 1 t f Turn-off fall time MT Delay matching, HS & LS turn-on/off 6 15 Static Electrical Characteristics V BIAS (V CC, V BS, V DD ) = 15V, T A = 25 C and V SS = COM unless otherwise specified. The V IN, V TH and I IN parameters are referenced to V SS and are applicable to all three logic input leads: HIN, LIN and SD. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Definition Figure Min. Typ. Max. Units Test Conditions V IH Logic 1 input voltage V IL Logic input voltage V IH Logic 1 input voltage 12 2 V IL Logic input voltage 13 1 V OH High level output voltage, V BIAS - V O I O = A V OL Low level output voltage, V O 15.1 I O = A I LK Offset supply leakage current 16 V B =V S = I QBS Quiescent V BS supply current V IN = V or V DD I QCC Quiescent V CC supply current V IN = V or V DD I QDD Quiescent V DD supply current µa V IN = V or V DD I IN+ Logic 1 input bias current 4 V IN = V DD I IN- Logic input bias current V IN = V V BSUV+ V BS supply undervoltage positive going threshold V BSUV- V BS supply undervoltage negative going threshold V V CCUV+ V CC supply undervoltage positive going threshold V CCUV- V CC supply undervoltage negative going threshold I O+ Output high short circuit pulsed current V O = V, V IN = V DD PW 1 µs A I O- Output low short circuit pulsed current V O = 15V, V IN = V PW 1 µs V V DD = 15V V DD = 3.3V 3

4 Functional Block Diagram V B V DD HIN V SS /COM LEVEL SHIFT LEVEL SHIFT CIRCUIT UV DETECT UV S R Q HO V S SD V CC LIN V SS /COM LEVEL SHIFT UV DETECT DELAY LO V SS COM Lead Definitions Symbol Description V DD Logic supply HIN Logic input for high side gate driver output (HO), in phase SD Logic input for shutdown LIN Logic input for low side gate driver output (LO), in phase V SS Logic ground V B High side floating supply HO High side gate drive output V S High side floating supply return V CC Low side supply LO Low side gate drive output COM Low side return Lead Assignments 14 Lead PDIP 16 Lead SOIC (Wide Body) IR1 IR1S Part Number 4

5 HV =1 to HIN LIN SD < V/ns HO LO Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit HIN LIN % % ( to ) ton t r toff tf 9% 9% HO LO 1% 1% Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition HIN LIN % % SD % LO HO HO LO t sd 9% MT 1% 9% MT LO HO Figure 5. Shutdown Waveform Definitions Figure 6. Delay Matching Waveform Definitions 5

6 Turn-on Time (ns) 1 Turn-on Time (ns) Temperature(C) Figure 7A. Turn-on Time vs. Temperature V CC/V BS Supply Voltage (V) Figure 7B. Turn-on Time vs. VCC/VBS Voltage 3 Turn-on Time (ns) Turn-off Time (ns) VDD Supply Voltage (V) Figure 7C. Turn-on Time vs VDD Voltage Figure 8A. Turn-off Time vs. Temperature 3 Turn-off Time (ns) Turn-off Time (ns) V CC/V BS Supply Voltage (V) Figure 8B. Turn-off Time vs. VCC/VBS Voltage Vdd Supply Voltage (V) Figure 8C. Turn-off Time vs. VDD Voltage 6

7 Shutdown Time (ns) Shutdown Time (ns) Figure 9A. Shutdown Time vs. Temperature VCC/VBS Supply Voltage (V) Figure 9B. Shutdown Time vs. VCC/VBSVoltage 3 4 Shutdown Time (ns) Turn-on Rise Time (ns) VDD Supply Voltage (V) Figure 9C. Shutdown Time vs VDD Voltage Figure 1A. Turn-on Rise Time vs. Temperature Turn-on Rise Time (ns) 3 1 Turn-off Fall Time (ns) VBIAS Supply Voltage (V) Figure 1B. Turn-on Rise Time vs. VBIAS (V CC =V BS =V DD ) Voltage Figure 11A. Turn-off Fall Time vs. Temperature 7

8 ) 4 15 Turn-off Fall Time (ns) 3 1 Logic 1 Input Threshold (V) min V BIAS Supply Voltage (V) Figure 11B. Turn-Off Fall Time vs. VBIAS (V CC =V BS =V DD ) Voltage Figure 12A. Logic 1 Input Threshold vs. Temperature 15 Logic 1 Input Threshold (V) min Logic Input Threshold (V) V DD Logic Supply Voltage (V) Figure 12B. Logic 1 Input Threshold vs. VDD Voltage Figure 13A. Logic Input Threshold vs. Temperature 15 5 Logic Input Threshold (V High Level Output (V) V DD Logic Supply Voltage (V) Figure 13B. Logic Input Threshold vs. VDD Voltage Figure 14A. High Level Output vs. Temperature 8

9 5 1. High Level Output (V) Low Level Output (V) VBIAS Supply Voltage (V) Figure 14B. High Level Output vs. VBIAS Voltage Figure 15A. Low Level Output vs. Temperature 1. 3 Low Level Output (V) Offset Supply Current (ua) V BIAS Supply Voltage (V) Figure 15B. Low Level Output vs. VBIAS Voltage Figure 16A. Offset Supply Current vs. Temperature Offset Supply Current (ua) Offset Supply Voltage (V) Figure 16B. Offset Supply Current vs. Offset Voltage VBS Supply Current (ua) Figure 17A. Vbs Supply Current vs. Temperature 9

10 VBS Supply Current (ua) 4 3 VCC Supply Current (ua) VBS Floating Supply Voltage (V) Figure 17B. Vbs Supply Current vs. VBS Voltage Figure 18A. Vcc Supply Current vs. Temperature VCC Supply Current (ua) 4 3 VDD Supply Current (ua) VCC Voltage (V) Figure 18B. Vcc Supply Current vs. VCC Voltage Figure 19A. Vdd Supply Current vs. Temperature 1 VDD Supply Current (ua) VDD Voltage (V) Figure 19B. Vdd Supply Current vs. VDD Voltage Logic 1 Input Current (ua) Figure A. Logic 1 Input Current vs. Temperature 1

11 5. Logic Input Current (ua) Logic 1 Input Current (ua) VDD Voltage (V) Figure B. Logic 1 Input Current vs. VDD Voltage Logic Input Current (ua) Figure 21A. Logic Input Current vs. Temperature VBS Undervoltage Lockout + (V) Max. Typ. Min VDD Voltage (V) Figure 21B. Logic Input Current vs. VDD Voltage Temperature ( C) Figure 22. VBS Undervoltage (+) vs. Temperature VBS Undervoltage Lockout - (V) Max. Typ. Min. VCC Undervoltage Lockout + (V) Max. Typ. Min Temperature ( C) Figure 23. VBS Undervoltage (-) vs. Temperature Temperature ( C) Figure 24. VCC Undervoltage (+) vs. Temperature 11

12 Vcc Undervoltage Lockout - (V) Max. Typ. Min. Output Source Current (ua) min Temperature ( C) Figure 25. VCC Undervoltage (-) vs. Temperature Figure 26A. Output Source Current vs. Temperature 5. Output Source Current (ua) min Output Sink Current (ua) min Vbias Supply Voltage (V) Figure 26B. Output Source Current vs. VBIAS Voltage Figure 27A. Output Sink Current vs. Temperature. Output Sink Current (ua) min Junction V 1V Vbias Supply Voltage (V) Figure 27B. Output Sink Current vs. VBIAS Voltage. 1.E+3 1.E+4 1.E+5 1.E+6 Frequency (Hz) Figure 28. IR1 Tj vs Frequency R GATE = 1 Ohm, Vcc = 15V with IRFPE 12

13 .. Junction V 1V Junction V 1V. 1.E+3 1.E+4 1.E+5 1.E+6 Frequency (Hz) Figure 29. IR1 Tj vs Frequency R GATE = 16 Ohm, Vcc = 15V with IRFBC4. 1.E+3 1.E+4 1.E+5 1.E+6 Frequency (Hz) Figure 3. IR1 Tj vs Frequency R GATE = 22 Ohm, Vcc = 15V with IRFBC3.. V Junction V 1V Junction V. 1.E+3 1.E+4 1.E+5 1.E+6 Frequency (Hz) Figure 31. IR1 Tj vs Frequency R GATE = 33 Ohm, Vcc = 15V with IRFBC. 1.E+3 1.E+4 1.E+5 1.E+6 Frequency (Hz) Figure 32. IR1S Tj vs Frequency R GATE = 1 Ohm, Vcc = 15V with IRFPE 13

14 Junction Junction E+3 1.E+4 1.E+5 1.E Frequency (Hz) Figure 33. IR1S Tj vs Frequency R GATE = 16 Ohm, Vcc = 15V with IRFBC4 V 1V V 1V Junction E+3 1.E+4 1.E+5 1.E+6 Frequency (Hz) Figure 34. IR1S Tj vs Frequency R GATE = 22 Ohm, Vcc = 15V with IRFBC3 V 1V. 1.E+3 1.E+4 1.E+5 1.E+6 Frequency (Hz) Figure 35. IR1S Tj vs Frequency R GATE = 33 Ohm, Vcc = 15V with IRFBC 14

15 Case Outlines 14 Lead PDIP (MS-1AC) 16 Lead SOIC (wide body) (MS-13AA) 15

16 Tape and Reel Details: SOIC8N LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIMENSION IN MM E G CARRIER TAPE DIMENSION FOR 8SOICN Metric Imperial Code Min Max Min Max A B C D E F G 1. n/a.59 n/a H F D E C B A G H REEL DIMENSIONS FOR 8SOICN Metric Imperial Code Min Max Min Max A B C D E F n/a 18.4 n/a.724 G H

17 LEADFREE PART MARKING INFORMATION Part number Date code IRxxxxxx YWW? IR logo Pin 1 Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP -2 ORDER INFORMATION Basic Part (Non-Lead Free) 14-Lead PDIP IR1 order IR1 16-Lead SOIC IR1S order IR1S Leadfree Part 14-Lead PDIP IR1 order IR1PbF 16-Lead SOIC IR1S order IR1SPbF 16-Lead SOIC IR1STR order IR1STRPbF IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245 Tel: (31) This product has been qualified per industrial level Data and specifications subject to change without notice. 9/12/4 17

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