FAN7371 High-Current High-Side Gate Drive IC

Transcription

1 FAN1 High-Current High-Side Gate Drive IC Features! Floating Channel for Bootstrap Operation to +V! A/A Sourcing/Sinking Current Driving Capability! Common-Mode dv/dt Noise Canceling Circuit!.V and V Input Logic Compatible! Output In-phase with Input Signal! Under- Voltage Lockout for V BS! V Shunt Regulator on V DD and V BS! 8-Lead Small Outline Package (SOP) Applications! High-Speed Gate Driver! Sustaine Switch Driver in PDP Application! Energy-Recovery Circuit Switch Driver in PDP Application! High-Power Buck Converter! Motor Drive Inverter Description November 9 The FAN1 is a monolithic high-side gate drive IC, which can drive high-speed MOSFETs and IGBTs that operate up to +V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Fairchild s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to V S =-9.8V (typical) for V BS =1V. The UVLO circuit prevents malfunction when V BS is lower than the specified threshold voltage. The high-current and low-output voltage drop feature makes this device suitable for sustaine switch driver and energy recovery switch driver in the Plasma Display Panel application, motor drive inverter, switching power supply, and high-power DC-DC converter applications. 8-SOP Ordering Information Part Number Package Operating Temperature Range Eco Status FAN1M (1) 8-SOP - C ~ 1 C RoHS FAN1MX (1) Packing Method Tube Tape & Reel Note: 1. These devices passed wave soldering test by JESDA-111. For Fairchild s definition of Eco Status, please visit: FAN1 Rev. 1..

2 Typical Application Diagrams 1V IN1 IN C1 RBOOT1 DBOOT1 FAN1 1 VDD VB IN HO VS GND FAN1 1 VDD VB IN HO GND VS 8 CBOOT1 D1 R1 DBOOT R Q1 8 R CBOOT R C Q D D D L1 VS Q Q R DBOOT RBOOT FAN1 8 VB VDD R HO IN CBOOT VS GND To Pannel FAN1 R R8 8 VB VDD HO VS IN GND 1 1 1V C IN IN Energy Recovery Circuit Part Sustain Drive Part FAN1 Rev. Figure 1. Floated Bidirectional Switch and Half-Bridge Driver: PDP application 1V V IN R BOOT D BOOT FAN1 1 V DD V B 8 PWM C1 IN HO V S C BOOT R1 R L1 GND D1 C V OUT FAN1 Rev.1 Figure. Step-Down (Buck) DC-DC Converter Application FAN1 Rev. 1..

3 Internal Block Diagram V DD GND IN 1 V 11K V DD Pin Configuration PULSE GENERATOR Pins and are no connection. NOISE CAELLER R S UVLO Figure. Functional Block Diagram R Q Shoot-through current compensated gate driver V FAN1 Rev. 8 V B HO V S V DD 1 8 V B IN FAN1 HO V S GND FAN1 Rev.1 Figure. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 V DD Supply Voltage IN Logic Input for High-Side Gate Driver Output No Connection GND Ground No Connection V S High-Voltage Floating Supply Return HO High-Side Driver Output 8 V B High-Side Floating Supply FAN1 Rev. 1..

4 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T A = C unless otherwise specified. Symbol Characteristics Min. Max. Unit V S High-Side Floating Offset Voltage V B -V SHUNT V B +. V V B High-Side Floating Supply Voltage () -.. V V HO High-Side Floating Output Voltage V S -. V B +. V V DD Low-Side and Logic Supply Voltage () -. V SHUNT V V IN Logic Input Voltage -. V DD +. V dv S /dt Allowable Offset Voltage Slew Rate ± V/ns P D Power Dissipation (,, ). W θ JA Thermal Resistance C/W T J Junction Temperature - +1 C T STG Storage Temperature - +1 C T A Operating Ambient Temperature - +1 C Notes: This IC contains a shunt regulator on V DD and V BS with a normal breakdown voltage of V. Please note that this supply pin should not be driven by a low-impedance voltage source greater than the V SHUNT specified in the Electrical Characteristics section Mounted on. x 11. x 1.mm PCB (FR- glass epoxy material). Refer to the following standards: JESD1-: Integral circuits thermal test method environmental conditions, natural convection, and JESD1-: Low effective thermal conductivity test board for leaded surface mount packages. Do not exceed power dissipation (P D ) under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit V BS High-Side Floating Supply Voltage V S +1 V S + V V S High-Side Floating Supply Offset Voltage -V DD V V HO High-Side Output Voltage V S V B V V IN Logic Input Voltage GND V DD V V DD Supply Voltage 1 V FAN1 Rev. 1..

5 Electrical Characteristics V BIAS (V DD, V BS )=1.V, T A = C, unless otherwise specified. The V IN and I IN parameters are referenced to GND. The V O and I O parameters are relative to V S and are applicable to the respective output HO. Symbol Characteristics Test Condition Min. Typ. Max. Unit POWER SUPPLY SECTION I QDD Quiescent V DD Supply Current V IN =V or V μa I PDD Operating V DD Supply Current f IN =KHz, No Load 1 μa BOOTSTRAPPED SUPPLY SECTION V V BS Supply Under-Voltage Positive Going BSUV+ Threshold Voltage V BS =Sweep V V V BS Supply Under-Voltage Negative Going BSUV- Threshold Voltage V BS =Sweep V V V BS Supply Under-Voltage Lockout BSHYS Hysteresis Voltage V BS =Sweep. V I LK Offset Supply Leakage Current V B =V S =V 1 μa I QBS Quiescent V BS Supply Current V IN =V or V 1 μa C I PBS Operating V BS Supply Current LOAD =1nF, f IN =KHz, rms Value 1..8 ma SHUNT REGULATOR SECTION V V DD and V BS Shunt Regulator Clamping SHUNT Voltage I SHUNT =ma V INPUT LOGIC SECTION V IH Logic 1 Input Voltage. V V IL Logic Input Voltage.8 V I IN+ Logic Input High Bias Current V IN =V μa I IN- Logic Input Low Bias Current V IN =V μa R IN Input Pull-down Resistance 11 KΩ GATE DRIVER OUTPUT SECTION V OH High Level Output Voltage (V BIAS - V O ) No Load 1. V V OL Low Level Output Voltage No Load mv I O+ Output High, Short-Circuit Pulsed Current () V HO =V, V IN =V, PW 1µs.. A I O- Output Low, Short-Circuit Pulsed Current () V HO =1V,V IN =V, PW 1µs.. A Allowable Negative V V S pin Voltage for IN S Signal Propagation to HO Note: These parameters guaranteed by design V Dynamic Electrical Characteristics V DD =V BS =1V, GND=V, C LOAD =1pF, T A = C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit t on Turn-on Propagation Delay Time V S =V 1 1 ns t off Turn-off Propagation Delay Time V S =V 1 1 ns t r Turn-on Rise Time ns t f Turn-off Fall Time 1 ns. FAN1 Rev. 1..

6 Typical Characteristics t ON [ns] 1 1 Figure. Turn-on Propagation Delay t OFF [ns] 1 1 Figure. Turn-off Propagation Delay t R [ns] t F [ns] 1 1 Figure. Turn-on Rise Time Figure 8. Turn-off Fall Time I PDD [μa] I PBS [ma] 1... Figure 9. Operating V DD Supply Current Figure 1. Operating V BS Supply Current FAN1 Rev. 1..

7 Typical Characteristics (Continued) V BSUV Figure 11. V BS UVLO+. V BSUV Figure 1. V BS UVLO-.. V IH. 1. V IL Figure 1. Logic High Input Voltage Figure 1. Logic Low Input Voltage R IN [kω] 1 1 V OH Figure 1. Input Pull-Down Resistance vs.temperature. Figure 1. High-Level Output Voltage FAN1 Rev. 1..

8 Typical Characteristics (Continued) I O+ [A] Figure 1. Output High, Short-Circuit Pulsed Current I O- [A] Figure 18. Output Low, Short-Circuit Pulsed Current I O+ [A] I O- [A] V BS V BS Figure 19. Output High, Short-Circuit Pulsed Current vs. Supply Voltage Figure. Output Low, Short-Circuit Pulsed Current vs. Supply Voltage I QDD [μa] - C C 1 C I QBS [μa] 8 C 1 C - C Supply Voltage Supply Voltage Figure 1. Quiescent V DD Supply Current vs. Supply Voltage Figure. Quiescent V BS Supply Current vs. Supply Voltage FAN1 Rev

9 Switching Time Definitions Timing Diagram 1V % % V DD V B 1nF 1µF 1µF.1µF V S GND FAN1 1V ton tr toff tf 1pF 9% 9% IN HO OUT 1% (A) (B) Figure. Switching Time Test Circuit and Waveform Definitions IN 1% FAN1 Rev

10 Physical Dimensions..8 PIN ONE INDICATOR (.) A B..8. M C BA LAND PATTERN RECOMMENDATION 1. MAX R.1 R (1.) DETAIL A SCALE: :1 C.1.. x. SEATING PLANE.1 C GAGE PLANE. SEE DETAIL A OPTION A - BEVEL EDGE OPTION B - NO BEVEL EDGE..19 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-1, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT ILUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC1PX1-8M. E) DRAWING FILENAME: M8AREV1 Figure. 8-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FAN1 Rev

11 FAN1 Rev

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