FAN7384 Half-Bridge Gate-Drive IC

Transcription

1 FAN7384 Half-Bridge Gate-Drive IC Features Floating Channel for Bootstrap Operation to +6V Typically 25mA/5mA Sourcing/Sinking Current Driving Capability for Both Channels Extended Allowable Negative V S Swing to -9.8V for Signal Propagation at V DD =V BS =15V Matched Propagation Delay Below 5ns Output In-Phase with Input Signal 3.3V and 5V Input Logic Compatible Built-in Shoot-Through Prevention Logic Built-in Common Mode dv/dt Noise Canceling Circuit Built-in UV Functions for Both Channels Built-in Cycle-by-Cycle Shutdown Function Built-in Soft-Off Function Built-in Bi-Directional Fault Function Built-in Short-Circuit Protection Function Description October 29 The FAN7384 is a monolithic half-bridge gate-drive IC designed for high voltage, high speed driving MOSFETs and IGBTs operating up to +6V. Fairchild s high-voltage process and common-mode noise canceling technique provide stable operation of high-side drivers under high-dv/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to V S = -9.8V (typical) for V BS =15V. The UV circuits prevent malfunction when V DD and V BS are lower than the specified threshold voltage. Output drivers typically source/sink 25mA/5mA, respectively, which is suitable for half-bridge and fullbridge applications in motor drive systems. Applications Motor Inverter Driver Normal Half-Bridge and Full-Bridge Driver Switching Mode Power Supply 14-SOP 1 Ordering Information Operating Temperature Part Number Package Range FAN7384M (1) 14-Lead, Small Outline Integrated FAN7384MX (1) Circuit (SOIC), Non-JEDEC,.15-4 C to +125 C Inch Narrow Body, 225SOP Note: 1. These devices passed wave soldering test by JESD22A-111. Eco Status RoHS Packing Method Tube Tape & Reel For Fairchild s definition of Eco Status, please visit: FAN7384 Rev. 1..7

2 Typical Application Diagrams V DC V CC 3-Phase Motor Controller UU UL VU UL WU WL VDD VB HO VS U HIN VB LIN HIN VS V LIN VB HIN LIN VS FO FO FO SD SD SD CSC CSC CSC GND GND GND FAN7384 VSL VDD FAN7384 VSL HO VDD FAN7384 VSL HO W U V W FAN7384 Rev.3 Figure 1. 3-Phase Motor Drive Application V DC V CC RPULLUP VDD VB VDD VB HO HO PHA PHB FAULT SHUTDOWN HIN HIN FO SD 3K FAN7384 VS LIN HIN FO SD 3K FAN7384 VS Forward Reverse M DC Motor Controller GND VSL CSC GND VSL CSC FAN7384 Rev.2 Figure 2. DC Motor Drive Application FAN7384 Rev

3 Internal Block Diagram LIN HIN SD HS(ON/OFF) SCHMITT TRIGGER INPUT SHOOT-THROUGH PREVENTION CONTROL GIC PULSE GENERATOR LS(ON/OFF) V DD _UV NOISE CANCELLER UV GND/V SL LEVEL SHIFTER UV R R Q S DELAY DRIVER DRIVER V B HO V S V DD 8 V SL FAULT GIC SOFT-OFF CSC 6 ONE-SHOT TRIGGER ONE-SHOT TRIGGER I SOFT.5V V DD _UV 5 FO GND 7 FAN7384 Rev.3 Figure 3. Functional Block Diagram FAN7384 Rev

4 Pin Configuration LIN SD HIN V DD FO CSC GND FAN V B HO V S NC NC V SL FAN7384 Rev. Figure 4. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 LIN Logic Input for low-side gate driver 2 SD Shutdown control input with active low 3 HIN Logic Input for high-side gate driver 4 V DD Low-side power supply voltage 5 FO Bi-direction fault pin with open drain 6 CSC Short-circuit current detection input 7 GND Ground 8 V SL Low-side supply offset voltage 9 Low-side gate driver output 1 NC Not connection 11 NC Not connection 12 V S High-side floating supply offset voltage 13 HO High-side gate driver output 14 V B High-side floating supply voltage FAN7384 Rev

5 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T A =25 C, unless otherwise specified. Symbol Parameter Min. Max. Unit V S High-side offset voltage V S V B -25 V B +.3 V V B High-side floating supply voltage V B V V HO High-side floating output voltage V S -.3 V B +.3 V V DD Low-side and logic-fixed supply voltage V V IN Logic input voltage (HIN, LIN, SD) -.3 V DD +.3 V V CSC Current sense input voltage -.3 V DD +.3 V V FO Fault output voltage -.3 V DD +.3 V dv S /dt Allowable offset voltage slew rate 5 V/ns (2)(3)(4) P D Power dissipation 1. W θ JA Thermal resistance, junction-to-ambient 11 C/W T J Junction temperature +15 C T S Storage temperature C Notes: 2. Mounted on 76.2 x x 1.6mm PCB (FR-4 glass epoxy material). 3. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 4. Do not exceed P D under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Condition Min. Max. Unit V B High-side floating supply voltage V S +13 V S +2 V V S High-side floating supply offset voltage 6-V DD 6 V V DD Supply voltage 13 2 V V HO High-side output voltage V S V B V V Low-side output voltage GND V DD V V IN Logic input voltage (HIN, LIN, SD) GND V DD V V FO Fault output voltage -.3 V DD +.3 V T A Ambient temperature C FAN7384 Rev

6 Electrical Characteristics V BIAS (V DD, V BS ) = 15.V, T A = 25 C, unless otherwise specified. The V IN and I IN parameters are referenced to GND. The V O and I O parameters are referenced to V S and GND and are applicable to the respective outputs HO and. Symbol Characteristics Condition Min. Typ. Max. Unit W SIDE POWER SUPPLY SECTION I QDD Quiescent V DD supply current V LIN =V or 5V 6 8 μa I PDD Operating V DD supply current f LIN =2kHz, rms value μa V V DD supply under-voltage positive going DDUV+ threshold V DD =Sweep V V V DD supply under-voltage negative going DDUV- threshold V DD =Sweep V V V DD supply under-voltage lockout DDHYS hysteresis V DD =Sweep.5 V BOOTSTRAPPED POWER SUPPLY SECTION V V BS supply under-voltage positive going BSUV+ threshold V BS =Sweep V V V BS supply under-voltage negative going BSUV- threshold V BS =Sweep V V V BS supply under-voltage lockout BSHYS hysteresis V BS =Sweep.5 V I LK Offset supply leakage current V B =V S =6V 1 μa I QBS Quiescent V BS supply current V HIN =V or 5V 5 9 μa I PBS Operating V BS supply current f HIN =2kHz, rms value 4 6 μa GATE DRIVER OUTPUT SECTION V OH High-level output voltage, V BIAS -V O I O =ma (No Load) 1 mv V OL Low-level output voltage, V O I O =ma (No Load) 1 mv I O+ Output HIGH short-circuit pulse current V O =V, V IN =5V with PW<1µs 2 25 ma I O- Output W short-circuit pulsed current V O =15V, V IN =V with PW<1µs 42 5 ma V S Allowable negative V S pin voltage for IN signal propagation to H O V V SL -GND V SL -GND/GND-V SL voltage educability V SHUTDOWN CONTROL SECTION (SD) SD+ Shutdown "1" input voltage 1.2 V SD- Shutdown "" input voltage 2.5 V GIC INPUT SECTION (HIN, LIN) V IH Logic "1" input voltage 2.5 V V IL Logic "" input voltage 1.2 V V INHYS Logic input hysteresis voltage.5 V I IN+ Logic "1" input bias current V IN =5V μa I IN- Logic "" input bias current V IN =V 2. μa FAN7384 Rev

7 Electrical Characteristics (Continued) V BIAS (V DD, V BS ) = 15.V, T A = 25 C, unless otherwise specified. The V IN and I IN parameters are referenced to GND. The V O and I O parameters are referenced to GND and V S is applicable to HO and. Symbol Characteristics Condition Min. Typ. Max. Unit SHORT-CIRCUIT PROTECTION V CSCREF Short-circuit detector reference voltage V I CSCIN Short-circuit input current V CSCIN =1V, R CSCIN =1KΩ μa I SOFT Soft turn-off source current V DD =15V ma -V CSC Negative CSC pin immunity (5) Voltage on CSC pin up to -12V, Time<2μs -2 V FAULT DETECTION SECTION V FINH Fault input high level voltage 2.5 V V FINL Fault input low level voltage 1.2 V V FINHYS Fault input hysteresis voltage (5).5 V V FOH Fault output high level voltage V CSC =V, R PULL-UP =4.7KΩ 4.7 V V FOL Fault output low level voltage V CSC =1V, I FO =2mA.8 V t FO Fault output pulse width V CSCIN =1V 6 1 µs Note: 5. These parameters guaranteed by design. Dynamic Electrical Characteristics T A =25 C, V BIAS (V DD, V BS ) = 15.V, V S = GND, C Load = 1pF unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit t on Turn-on propagation delay V S =V ns t off Turn-off propagation delay V S =V or 6V (5) ns t r Turn-on rise time 5 1 ns t f Turn-off fall time 3 8 ns MT Delay matching 5 ns DT Dead-time ns t UVFLT Under-voltage filtering time (5) 16 µs t CSCFLT CSC pin filtering time (5) 3 ns t CSCFO Time from CSC triggering to FO (5) 35 ns t CSC Time from CSC triggering to low-side gate output (5) Note: 5. These parameters guaranteed by design. From V CSC =1V to starting gate turn-off 6 ns t SDFO Shutdown to FO propagation delay (5) 6 ns t SDOFF Shutdown to HIGH/W-side gate off (5) 1 ns FAN7384 Rev

8 Typical Characteristics V DDUV V DDUV Figure 5. V DD UV (+) vs. Temperature Figure 6. V DD UV (-) vs. Temperature V DDHYS.6.4 V BSUV Figure 7. V DD UV Hysteresis vs. Temperature Figure 8. V BS UV (+) vs. Temperature V BSUV V BSHYS Figure 9. V BS UV (-) vs. Temperature Figure 1. V BS UV Hysteresis vs. Temperature FAN7384 Rev

9 Typical Characteristics (Continued) I QDD [μa] I QBS [μa] Figure 11. V DD Quiescent Current vs. Temperature Figure 12. V BS Quiescent Current vs. Temperature I PDD [μa] I PBS [μa] Figure 13. V DD Operating Current vs. Temperature Figure 14. V BS Operating Current vs. Temperature I IN + [μa] I CSCIN [μa] Figure 15. Logic Input Current vs. Temperature Figure 16. I CSCIN vs. Temperature FAN7384 Rev

10 Typical Characteristics (Continued) I SOFT [ma] t r [nsec] Figure 17. I SOFT vs. Temperature Figure 18. Turn-on Rising Time vs. Temperature t f [nsec] 6 4 t on [nsec] Figure 19. Turn-off Falling Time vs. Temperature Figure 2. Turn-on Delay Time vs. Temperature t off [nsec] 2 15 V IH Figure 21. Turn-off Delay Time vs. Temperature Figure 22. Logic Input High Voltage vs. Temperature FAN7384 Rev

11 Typical Characteristics (Continued) V IL V INHYS Figure 23. Logic Input Low Voltage vs. Temperature Figure 24. Logic Input Hysteresis vs. Temperature SD BAR SD BAR Figure 25. SD Positive Threshold vs. Temperature Figure 26. SD Negative Threshold vs. Temperature V CSCREF.55.5 V FINH Figure 27. V CSCREF vs. Temperature Figure 28. Fault Input High Voltage vs. Temperature FAN7384 Rev

12 Typical Characteristics (Continued) V FOH V FOL Figure 29. Fault Output High Voltage vs. Temperature Figure 3. Fault Output Low Voltage vs. Temperature V S DT [nsec] Figure 31. Allowable Negative V S Voltage for Signal Propagation to High Side vs. Temperature Figure 32. Dead Time vs. Temperature FAN7384 Rev

13 Switching Time Definitions The overall switching timing waveforms definition of FAN7384 as shown Figure 33. LIN SD V DD.5V V CSC FO t UVFLT t CSCFO UV- t FO Low-Side Output Disable Shutdown Disable Skip t CSCFO t FO Low-Side Output Disable t CSC t CSC Under-Voltage Detection Point Soft-Off Operating Shutdown Enable Point Shutdown Disable Point Short-Circuit Detection Point Soft-Off Operating FAN7384 Rev.3 Figure 33. Switching Timing Waveforms Definition FAN7384 Rev

14 Typical Application Information 1. Protection Function 1.1 Under-Voltage Lockout (UV) The high- and low-side drivers include under-voltage lockout (UV) protection circuitry that monitors the supply voltage (V DD ) and bootstrap capacitor voltage (V BS ) independently. It can be designed to prevent malfunction when V DD and V BS are lower than the specified threshold voltage. Moreover, the UV hysteresis prevents chattering during power supply transitions. If the supply voltage (V DD ) maintains an under-voltage condition over under-voltage filtering times (typically 16µs), the fault and soft-off circuits are activated, as shown Figure 34. LIN HIN/LIN LIN/HIN HO/ /HO Shoot-Through Prevent After DT FAN7384 Rev.1 Figure 36. Waveforms for Shoot-Through Prevention V DD FO FAN7384 Rev.1 t UVFLT t CSCFO t CSC t 1 t 2 t 3 9% Figure 34. Waveforms for Under-Voltage Lockout 1.2 Shoot-Through Prevention Function The FAN7384 has a shoot-through prevention circuitry that monitors the high- and low-side inputs. It can be designed to prevent outputs of high- and low-side turning on at same time, as shown Figure 35 and 36. UV+ UVt FO 1.3 Over-Current Protection Function The FAN7384 has over-current detection circuitry that monitors the current-by-current sensing resistor connected from the low-side switch source (V SL ) to ground. It is a built-in time-filler from the over-current event to prevent malfunction from a noise source, such as leading-edge pulse in inductive load application, as shown Figure 37. The sensing current is calculated as follows: I where, V CSCREF : Reference voltage of current sense comparator R CS : Current sensing resistor V CS = CSCREF RCS [A] (1) HIN/LIN LIN LIN/HIN Low-Side Output Disable Shoot-Through Prevent V CSC.5V HO/ After DT FO t CSCFO t FO t CSC /HO After DT FAN7384 Rev.1 Soft-Off Short-Circuit Operating Detection Point FAN7384 Rev.3 Figure 35. Waveforms for Shoot-Through Prevention Figure 37. Waveforms for Short-Circuit Protection FAN7384 Rev

15 2. Layout Considerations For optimum performance, considerations must be taken during printed circuit board (PCB) layout. 2.1 Supply Capacitors If the output stages are able to quickly turn on a switching device with a high value of current, the supply capacitors must be placed as close as possible to the device pins (V DD and GND for the ground-tied supply, V B and V S for the floating supply) to minimize parasitic inductance and resistance. 2.2 Gate-Drive Loop Current loops behave like antennae, able to receive and transmit noise. To reduce the noise coupling/emission and improve the power switch turn-on and off performance, gate-drive loops must be reduced as much as possible. 2.3 Ground Plane To minimize noise coupling, the ground plane should not be placed under or near the high-voltage floating side. FAN7384 Rev

16 Package Dimensions 6. B PIN ONE INDICATOR (.27) 14 # TOP VIEW 8 7 A B B C B A # LAND PATTERN RECOMMENDATION 1.8 MAX C (R.2) SEE DETAIL A MIN B SIDE VIEW.1 MAX C END VIEW NOTES: A) THIS DRAW ING COMPLIES W ITH JEDEC MS-12 EXCEPT AS NOTED. B) THIS DIMENSION IS OUTSIDE THE JEDEC MS-12 VALUE. C) ALL DIMENSIONS ARE IN MILLIMETERS. D) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. E) LANDPATTERN STANDARD: SOIC127P6X145-14M F) DRAWING FILE NAME AND REVISION : M14CREV1.36 GAGE PLANE SEATING PLANE 8 Æ (R.1).9.5 DETAIL A Figure Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC,.15 Inch Narrow Body, 225SOP Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FAN7384 Rev

17 FAN7384 Rev