IX2120BTR. 1200V High and Low Side Gate Driver INTEGRATED CIRCUITS DIVISION. Description. Driver Characteristics. Features. Ordering Information

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1 IX High and Low Side Gate Driver Driver Characteristics Parameter Rating Units OFFSET I O +/- (Source/Sink) / A OUT - t on /t off / ns Features Floating Channel for Bootstrap Operation to + Outputs Capable of Sourcing and Sinking A Gate Drive Supply Range From to Enhanced Robustness due to SOI Process Tolerant to Negative oltage Transients: d/dt Immune. Logic Compatible Undervoltage Lockout for Both High-Side and Low-Side Outputs Description The IX is a high voltage integrated circuit that can drive high speed MOSFETs and IGBTs that operate at up to +. The IX is configured with independent high-side and low-side referenced output channels, both of which can source and sink A. The floating high-side channel can drive an N-channel power MOSFET or IGBT from the common reference. Manufactured on IXYS Integrated Circuits Division's proprietary high-voltage BCDMOS on SOI (silicon on insulator) process, the IX is extremely robust, and is virtually immune to negative transients. The U circuit prevents turn-on of the MOSFET or IGBT until there is sufficient BS or supply voltage. The IX is available in a -pin SOIC package. Ordering Information Part IXB IXBTR Description -Pin SOIC (/Tube) -Pin SOIC (/Reel) IX Functional Block Diagram B HIN SD Input Control Logic & Cycle-by-Cycle Edge-Triggered Shutdown Level Shift / / COM Pulse Generator Mid oltage Level Shift High oltage Level Shift U C R Q S Buffer S BM SM LIN Level Shift / / COM LS Delay Control U Buffer COM DS-IX-R

2 IX. Specifications Package Pinout: -Pin SOIC Package Pin Description: -Pin SOIC Package Absolute Maximum Ratings Thermal Characteristics Recommended Operating Conditions Dynamic Electrical Characteristics Static Electrical Characteristics Test Waveforms IX Typical Application Typical Performance Data Manufacturing Information Moisture Sensitivity ESD Sensitivity Soldering Profile Board Wash Mechanical Dimensions R

3 IX Specifications Typical values are characteristic of the device at + C, and are the result of engineering evaluations. They are provided for information purposes only, and are not part of the manufacturing testing requirements.. Package Pinout: -Pin SOIC Package. Pin Description: -Pin SOIC Package S - B HIN - SD - LIN SM - BM - SM COM - Pin# Name Description S High-Side Floating Supply Return B High-Side Floating Supply - No Connection High-Side Gate Drive Output - No Connection - No Connection 7 - Internal Connection, Do Not Use - No Connection - Internal Connection, Do Not Use Logic Supply Logic Input for High-Side Gate Drive HIN Output (), In-Phase SD Logic Input for Shutdown LIN Logic Input for Low-Side Gate Driver Output (), In-Phase Logic Ground Low-Side Gate Drive Output - No Connection 7 COM Low-Side Return - No Connection Low-Side Supply - Internal Connection, Do Not Use - No Connection SM Middle Floating Return BM Middle Floating Supply SM Middle Floating Return - No Connection - No Connection 7 - No Connection - No Connection R

4 IX. Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. Parameter Symbol Min Max Units High-Side Floating Supply oltage B -. High-Side Floating Supply Offset oltage S B - B +. High-Side Floating Output oltage S -. B +. Middle Floating Supply oltage BM -. 7 Middle Floating Supply Offset oltage SM BM - BM +. Low-Side Fixed Supply oltage -. Low-Side Output oltage Logic Supply oltage -. + Logic Supply Offset oltage - +. Logic Input oltage (HIN, LIN, SD) IN Allowable Offset Supply oltage Transient d S /dt - /ns Package Power C P D -. W Junction Temperature T J - + C Storage Temperature T S - + C. Thermal Characteristics Parameter Symbol Rating Units Thermal Impedance, Junction to Ambient JA 7 C/W. Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. The S, SM, and offset ratings are tested with all supplies biased at a differential. Parameter Symbol Min Max Units High-Side Floating Supply Absolute oltage B S + S + High-Side Floating Supply Offset oltage S - High-Side Floating Output oltage S B Middle Floating Supply Absolute oltage BM SM + SM + Middle Floating Supply Offset oltage SM - Low-Side Fixed Supply oltage Low-Side Output oltage Logic Supply oltage + + Logic Supply Offset oltage - + Logic Input oltage (HIN, LIN, SD) IN R

5 IX. Dynamic Electrical Characteristics, =; BS, BMSM =.; C L = pf; and =COM unless otherwise specified. See Test Waveforms on page. Parameter Conditions Symbol Min Typ Max Units Turn-On propagation Delay S = t on - - Turn-Off propagation Delay SM = t off - - Shutdown propagation Delay S = t SD Turn-On Rise Time - t r -. - Turn-Off Fall Time - t f Delay Matching, HS & LS Turn-On/Off - MT - - ns.7 Static Electrical Characteristics, BMSM, BS, =, and =COM unless otherwise specified. The IN, TH, and I IN parameters are referenced to and are applicable to all three logic input leads: HIN, LIN, and SD. The O and I O parameters are referenced to COM and are applicable to the respective output leads: or. Parameter Conditions Symbol Min Typ Max Units Logic Input oltage = IH. - - Logic Input oltage IL - - Logic Input oltage = IH. - - Logic Input oltage IL - -. High-Level Output oltage, BIAS - O I O =A OH -.. Low-Level Output oltage, O I O =ma OL - -. High Offset Supply Leakage Current B = S = I HLK - Middle Offset Supply Leakage Current BM = SM = I MLK - Quiescent BS Supply Current IN = or I QBS - 7 Quiescent BMSM Supply Current IN = or I QBMSM A Quiescent Supply Current IN = or I QCC - Quiescent Supply Current IN = or I QDD - - Logic Input Bias Current IN = I IN+ - Logic Input Bias Current IN = I IN- - - BS Supply Undervoltage Positive Going Threshold - BSU BS Supply Undervoltage Negative Going Threshold - BSU Supply Undervoltage Positive Going Threshold - U A Supply Undervoltage Negative Going Threshold - U Output High Short Circuit Pulsed Current O =, IN =, PW s I O+ - - Output Low Short Circuit Pulsed Current O =, IN =, PW s I O- - - A R

6 IX. Test Waveforms.. Switching Time Test Circuit = µf.µf HIN B S C L.µF µf µf B +. - S ( to /) SD LIN BM SM SM.µF µf µf BM +. - SM ( to /) COM C L 7.. Input/Output Timing Waveform.. Shutdown Waveform Definitions HIN LIN SD SD % t sd %.. Switching Time Waveform Definition.. Delay Matching Waveform Definitions HIN LIN % % HIN LIN % % t on t r t off t f % % % % MT % % MT R

7 IX. IX Typical Application H R 7 M HIN SD LIN C µf 7 IX S N/C B N/C 7 N/C N/C N/C N/C SM N/C BM N/C SM N/C N/C N/C N/C HIN N/C SD COM 7 LIN N/C CB.µF DB C µf RB DB RB RD M CB.µF RD M DD DD R.7 R.7 R 7 DG DG M DR DR COM The IX is a half bridge gate driver for high voltage IGBTs and MOSFETs. Three input signals (HIN, LIN, and SD) determine the state of the gate driver outputs ( and ). HIN controls via a high voltage interface. The high voltage interface is integrated into the bootstrap supply by using two diodes (DD and DD). A two-stage bootstrap supplies current to the high side and mid level circuitry. The two bootstrap circuits are identical, and careful board layout and positioning of the bootstrap components are required. Resistors RD and RD form a resistive divider to keep the mid supply very near the center of the high voltage supply range. High value resisters (M ) are recommended to minimize power dissipation. The two-stage bootstrap supply reduces the high side gate drive voltage ( B - S ) by two diode forward voltage drops ( F ). Therefore, the supply range for the application circuit shown is: The high side bootstrap capacitor selection is a function of the switching frequency and the on-time (t ONTIME ) of the high side source driver. The quiescent BS current (I QBS ) is supplied by bootstrap capacitor CB, and the quiescent BMSM supply current (I QBMSM ) is supplied by bootstrap capacitor CB. To insure adequate supply current: and: t ONTIME CB I QBS BSU+ + F + CE sat M t ONTIME CB I QBMSM BSU+ + F + CE sat M BSU+ + F + CE sat M Where CE(sat) M is the saturation voltage of IGBT, M. R 7

8 IX Typical Performance Data Turn-On Delay Time (ns) Turn-On Delay Time Turn-Off Delay Time (ns) Turn-Off Delay Time Turn-On Delay Time (ns) Turn-On Delay Time vs. Supply oltage Turn-Off Delay Time (ns) Turn-Off Delay Time vs. Supply oltage Shutdown Delay Time (ns) Shutdown Delay Time Shutdown Delay Time (ns) Shutdown Delay Time vs. Supply oltage Turn-On Rise Time (ns) Turn-On Rise Time Turn-Off Fall Time (ns) Turn-Off Fall Time Turn-On Rise Time (ns) Turn-On Rise Time vs. oltage Turn-Off Fall Time (ns) Turn-Off Fall Time vs. oltage Logic Input Threshold () Logic Input Threshold vs. () Logic Input Threshold () Logic Input Threshold vs. () R

9 IX Logic "" Input Threshold () Logic "" Input Threshold Logic "" Input Threshold () Logic "" Input Threshold Logic "" Input Current (µa) Logic "" Input Current Logic "" Input Current (µa) Logic "" Input Current Supply Current Supply Current BS BS Supply Current BMSM BMSM Supply Current Supply Current vs. oltage Supply Current vs. oltage BS Supply Current vs. oltage BMSM Supply Current vs. oltage BS BMSM BS Floating BMSM R

10 IX High/Middle Supply Leakage Current High/Middle Supply Leakage Current vs. B / BM oltage U+ Leakage Current (µa) Leakage Current (µa) U+ () Boost oltage () Uvs. Temperature BSU+ BSUvs. Temperature U- () BSU+ () BSU- () High Level Output oltage () High Level Output oltage (I O =ma) Low Level Output oltage ()..... Low Level Output oltage (I O =ma) Output Source Current (A) Output Source Current Output Sink Current (A) Output Sink Current Output Source Current (A) Output Source Current vs. oltage Output Sink Current (A) Output Sink Current vs. oltage R

11 IX High Level Output oltage () High Level Output oltage vs. Supply oltage Low Level Output oltage (m) Low Level Output oltage vs. Supply oltage R

12 IX Manufacturing Information. Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-. Device Moisture Sensitivity Level (MSL) Classification IXB MSL. ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-.. Soldering Profile Provided in the table below is the Classification Temperature (T C ) of this product and the maximum dwell time the body temperature of this device may be above (T C - )ºC. The classification temperature sets the Maximum Body Temperature allowed for this device during lead-free reflow processes. For through hole devices, and any other processes, the guidelines of J-STD- must be observed. Device Classification Temperature (T C ) Dwell Time (t p ) Max Reflow Cycles IXB C seconds. Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. Board washing to reduce or remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to the device. These precautions include, but are not limited to: using a low pressure wash and providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature and duration necessary to remove the moisture trapped within the package is the responsibility of the user (assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based. R

13 IX. Mechanical Dimensions.. IX: -Pin SOIC Package 7.7 to. (.7 to.7) See Note Recommended PCB Land Pattern 7. to 7. (. to.) See Note. to. (. to.). (.). (.7) Pin Identifier. to. (. to.). to. x (. to.) x DIMENSIONS MIN to MAX mm (MIN to MAX inches). to. (. to.). to.7 x º (. to.) x º See Note.7 (.). (.). to. (. to.) See Note. (.).7 x (.) x.. IX Tape & Reel Information Seating Plane º to º x. to.7 (. to.) º to º Notes:. All dimensions are in mm / (inches).. This package conforms to JEDEC Standard MS-, variation AE issue C.. Dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed.mm per end.. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed.mm per side.. This chamfer is optional. If it is not present, then a Pin identifier must be located as shown.. The dimension applies to the flat section of the lead between.mm to.mm from the lead tip.. DIA. (. DIA) Top Cover Tape Thickness. MAX (. MAX) P=. (.7) A =. (.) B =. (.7) W=.+./-. (.+./-.) Embossed Carrier Embossment K =. (.) K =.7 (.) Dimensions mm (inches) Notes:. Unless otherwise specified, all dimensional tolerances per EIA standard. Unless otherwise specified, all dimensions ±. (.) For additional information please visit our website at: IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-IX-R Copyright, IXYS Integrated Circuits Division All rights reserved. Printed in USA. // R