FST Bit Bus Switch
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1 Features 4Ω Switch Connection between Two Ports Minimal Propagation Delay through the Switch Low I CC Zero Bounce in Flow-through Mode Control Inputs Compatible with TTL Level Description March 2008 Fairchild switch FST3125 provides four high-speed CMOS TTL-compatible bus switches. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The device is organized as four one1-bit switches with separate /OE inputs. When /OE is LOW, the switch is ON and port A is connected to port B. When /OE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports. Ordering Information Part Number Operating Temperature Range FST3125M -40 to 85 C FST3125MX -40 to 85 C FST3125QSC -40 to 85 C FST3125QSCX -40 to 85 C FST3125MTC -40 to 85 C FST3125MTCX -40 to 85 C Package 14-Lead, Small Outline Integrated Circuit (SOIC) inch Narrow 14-Lead, Small Outline Integrated Circuit (SOIC) inch Narrow 16-Lead, Quarter Size Outline Package (QSOP) MO inch Wide 16-Lead, Quarter Size Outline Package (QSOP) MO inch Wide 14-Lead, Thin Shrink Small Outline Package (TSSOP) MO-153, 4mm Wide 14-Lead, Thin Shrink Small Outline Package (TSSOP) MO-153, 4mm Wide Packing Method Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel All packages are lead free per JEDEC: J-STD-020B standard. The Fairchild switch family derives from and embodies Fairchild s proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product. Figure 1. Logic Diagram FST3125 Rev
2 Pin Configurations /OE 1 1 1A 2 1B 3 /OE V CC /OE 4 4A 4B NC /OE 1 1A 1B V CC /OE 4 4A 4B 2A 5 10 /OE 3 /OE /OE 3 2A A 2B 6 9 3A 2B B GND 7 8 3B Figure 2. SOIC and TSSOP Pin Assignments GND 8 9 NC Figure 3. QSOP Pin Assignments Pin Descriptions Truth Table Pin Names Description /OE 1, /OE 2, /OE 3, /OE 4 Bus Switch Enables 1A, 2A, 3A, 4A Bus A 1B, 2B, 3B, 4B Bus B NC Not Connected V CC GND Supply Voltage Ground Inputs /OE LOW HIGH Inputs/Outputs A, B A = B High Impedance FST3125 Rev
3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC Supply Voltage V V S DC Switch Voltage V V IN DC Input Voltage (1) V I IK DC Input Current -50 ma I OUT DC Output Sink Current 128 ma I CC / I GND DC V CC / GND Current ±100 ma T STG Storage Temperature Range C Note: 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V CC Power Supply Operating V V IN Input Voltage V V OUT Output Voltage V t r, t f Input Rise and Fall Time Switch Control Input (2) 0 5 Switch I/O 0 DC ns/v T A Operating Temperature, Free Air C Note: 2. Unused control inputs must be held HIGH or LOW. They may not float. FST3125 Rev
4 DC Electrical Characteristics Typical values are at V CC = 5.0V and T A = 25 C. Symbol Parameter Conditions V CC (V) T A =-40 to +85 C Min. Typ. Max. V IK Clamp Diode Voltage I IN = -18mA V V IH High-Level Input Voltage 4.0 to V V IL Low-Level Input Voltage 4.0 to V I IN Input Leakage Current 0 V IN ±1.0 µa I OZ Off-state Leakage Current R ON Switch On Resistance (3) I CC ΔI CC Quiescent Supply Current Increase in I CC per Input Units 0 A, B V CC 5.5 ±1.0 µa V IN = 0V, I IN = 64mA V IN = 0V, I IN = 30mA V IN = 2.4V, I IN = 15mA V IN = 2.4V, I IN = 15mA V IN = V CC or GND, I OUT = 0 One Input at 3.4V, Other Inputs at V CC or GND µa ma Note: 3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the A or B pins. Ω AC Electrical Characteristics T A = -40 to +85 C, C L = 50pF, and R U = R D = 500Ω. Symbol Parameter Conditions t PHL, t PLH V CC = V V CC = 4.0V Min. Max. Min. Max. Units Figure Propagation Delay Bus-to-Bus (4) VIN = Open ns Figure 4 Figure 5 t PZH,t PZL Output Enable Time V IN = 7V for t PZL V IN = Open for t PZH ns Figure 4 Figure 5 t PHZ, t PLZ Output Disable Time V IN = 7V for t PLZ V IN = Open for t PHZ ns Figure 4 Figure 5 Note: 4. This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance when driven by an ideal voltage source (zero output impedance). Capacitance T A = +25 C, f = 1MHz. Capacitance is characterized, but not tested. Symbol Parameter Conditions Typ. Units C IN Control Pin Input Capacitance V CC = 5.0V 3 pf C I/O Input/Output Capacitance V CC, /OE = 5.0V 2 pf FST3125 Rev
5 AC Loadings and Waveforms Notes: Input driven by 50Ω source terminated in 50Ω. C L includes load and stray capacitance. Input PRR = 1.0MHz, t w = 500ns. Figure 4. AC Test Circuit Figure 5. AC Waveforms FST3125 Rev
6 Physical Dimensions A B PIN ONE INDICATOR (0.33) M LAND PATTERN RECOMMENDATION C B A 1.75 MAX C SEE DETAIL A C R0.10 R X 45 GAGE PLANE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV (1.04) DETAIL A SCALE: 20:1 SEATING PLANE Figure Lead, Small-Outline Integrated Circuit (SOIC) inch Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FST3125 Rev
7 Physical Dimensions TOP VIEW LAND PATTERN RECOMMENDATION SIDE VIEW END VIEW DETAIL A Figure Lead, Quarter-Size Outline Package (QSOP), MO inch Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FST3125 Rev
8 Physical Dimensions 0.43 TYP TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV R0.09min Figure Lead, Thin Shrink Small Outline Package (TSSOP) MO-153, 4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FST3125 Rev
9 FST3125 Rev
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NC7SZ125 TinyLogic UHS Buffer with 3-STATE Output
NC7SZ125 TinyLogic UHS Buffer with 3-STATE Output Features Space saving SOT23 or SC70 5-lead package Ultra small MicroPak Pb-Free leadless package Ultra High Speed; t PD 2.6ns Typ. into 50pF at 5V V CC
QS54/74FCT373T, 2373T. High-Speed CMOS Bus Interface 8-Bit Latches MDSL QUALITY SEMICONDUCTOR, INC. 1 DECEMBER 28, 1998
Q QUALITY SEMICONDUCTOR, INC. QS54/74FCT373T, 2373T High-Speed CMOS Bus Interface 8-Bit Latches QS54/74FCT373T QS54/74FCT2373T FEATURES/BENEFITS Pin and function compatible to the 74F373 74FCT373 and 74ABT373
74AC244 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs
74AC244 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs General Description The AC/ACT244 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and
74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins Features I CC and I OZ reduced by 50% Common parallel I/O for reduced pin count Additional serial inputs and outputs
PI3C V/3.3V, High Bandwidth, Hot Insertion 10-Bit, 2-Port, Bus Switch
2.5V/3., High Bandwidth, Hot Insertion Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High Bandwidth (>400 MHz) Permits Hot Insertion. Rail-to-Rail, 3. or 2.5V ing 5V I/O
NC7SZ38 TinyLogic UHS 2-Input NAND Gate, Open Drain Output
NC7SZ38 TinyLogic UHS 2-Input NAND Gate, Open Drain Output Features Ultra-High Speed: t PD 2.4ns (Typical) into 50pF at 5V V CC Open Drain Output Stage for OR Tied Applications High Output Sink Drive:
NC7WZ125 TinyLogic UHS Dual Buffer with 3-STATE Outputs
March 2001 Revised January 2005 TinyLogic UHS Dual Buffer with 3-STATE Outputs General Description The is a Dual Non-Inverting Buffer with independent active LOW enables for the 3-STATE outputs. The Ultra
PI5C3253. Dual 4:1 Mux/DeMux Bus Switch
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON ESD Protection up to 2kV HBM Ultra Low Quiescent Power (0.2μA typical) Ideally suited
NC7SV05 TinyLogic ULP-A Inverter (Open-Drain Output)
NC7SV05 TinyLogic ULP-A Inverter (Open-Drain Output) Features 0.9V to 3.6V V CC Supply Operation 3.6V Over-Voltage Tolerant I/Os at VCC from 0.9V to 3.6V Extremely High Speed tpd - 1.0ns: Typical for 2.7V
74LVX08 Low Voltage Quad 2-Input AND Gate
74LVX08 Low Voltage Quad 2-Input AND Gate Features Input Voltage Level Translation from 5 V to 3 V Ideal for Low-power / Low-Noise 3.3 V Applications Guaranteed Simultaneous Switching Noise Level and Dynamic
74LCX541 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs
74LCX541 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs Features 5V tolerant input and outputs 2.3V 3.6V specifications provided 6.5ns t PD max ( = 3.3V), 10µA I CC max Power-down
MM74HC4066 Quad Analog Switch
MM74HC4066 Quad Analog Switch General Description The MM74HC4066 devices are digitally controlled analog switches utilizing advanced silicon-gate CMOS technology. These switches have low ON resistance
NC7WZ16 TinyLogic UHS Dual Buffer
NC7WZ16 TinyLogic UHS Dual Buffer Features Ultra-High Speed: t PD 2.4ns (Typical) into 50pF at 5 CC High Output Drive: ±24mA at 3 CC Broad CC Operating Range: 1.65 to 5.5 Matches Performance of LCX when
INTEGRATED CIRCUITS. CBT3245 Octal bus switch. Product specification Supersedes data of 1998 Dec Jun 19
INTEGRATED CIRCUITS Supersedes data of 1998 Dec 8 2000 Jun 19 FEATURES Standard 245-type pinout 5 Ω switch connection between two ports TTL compatible control input levels Package options include plastic
74F245 Octal Bidirectional Transceiver with 3-STATE Outputs
74F245 Octal Bidirectional Transceiver with 3-STATE Outputs Features Non-inverting buffers Bidirectional data path A outputs sink 24mA B outputs sink 64mA Ordering Information Order Number Package Number
74LVT LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs
74LVT16374 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs General Description The LVT16374 and LVTH16374 contain sixteen non-inverting D-type flip-flops with 3-STATE outputs and is
PI5C3253. Dual 4:1 Mux/DeMux Bus Switch
Features Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra Low Quiescent Power (0.2µA typical) Ideally suited for notebook applications
74LVC16245A/ 74LVCH16245A 16-bit bus transceiver with direction pin; 5V tolerant (3-State)
INTEGRATED CIRCUITS 16-bit bus transceiver with direction pin; 5V tolerant Supersedes data of 1997 Aug 1 IC24 Data Handbook 1997 Sep 25 FEATURES 5 volt tolerant inputs/outputs for interfacing with 5V logic
74AC245 74ACT245 Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
74AC245 74ACT245 Octal Bidirectional Traceiver with 3-STATE Inputs/Outputs General Description The AC/ACT245 contai eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented
74AC573 74ACT573 Octal Latch with 3-STATE Outputs
74AC573 74ACT573 Octal Latch with 3-STATE Outputs General Description The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable (LE) and buffered common Output Enable (OE)
USB1T11A Universal Serial Bus Transceiver
Universal Serial Bus Transceiver General Description The USB1T11A is a one chip generic USB transceiver. It is designed to allow 5.0V or 3.3V programmable and standard logic to interface with the physical
UNISONIC TECHNOLOGIES CO., LTD U74CBTLV3125
UNISONIC TECHNOLOGIES CO., LTD U74CBTLV3125 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH DESCRIPTION The U74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. NC7SZ126 TinyLogic UHS Buffer with 3-STATE Output General Description The
NC7WZ132 TinyLogic UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs
NC7WZ132 TinyLogic UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs Features Space saving US8 surface mount package MicroPak leadless package Ultra High Speed; t PD 3.1ns typ. into 50pF at 5V V CC