IX6R Volt, 6 Ampere High & Low-side Driver for N-Channel MOSFETs and IGBTs

Transcription

1 Features Floating High Side Driver with boot-strap Power supply along with a Low Side Driver. Fully operational to 00V ± 0V/ns dv/dt immunity Gate drive power supply range: - V Undervoltage lockout for both output drivers Separate Logic power supply range:.v to Built using the advantages and compatibility of CMOS and IXYS HDMOS TM processes Latch-Up protected over entire operating range High peak output current: A Low output impedance Low power supply current Immune to negative voltage transients Applications Driving MOSFETs and IGBTs in half-bridge circuits High voltage, high side and low side drivers Motor Controls Switch Mode Power Supplies (SMPS) DC to DC Converters Class D Switching Amplifiers Figure. Circuit Connection IXR 00 Volt, Ampere High & Low-side Driver for N-Channel MOSFETs and IGBTs General Description The IXR Bridge Driver for N-channel MOSFETs and IGBTs with a high side and low side output, whose input signals reference the low side. The High Side driver can control a MOSFET or IGBT connected to a positive bus voltage up to 00V. The logic input stages are compatible with TTL or CMOS, have built-in hysteresis and are fully immune to latch up over the entire operating range. The IXR can withstand dv/dt on the output side up to ± 0V/ns. Ordering Information The IXR is available in the -Pin DIP, the -Pin SOIC, and the heat-sinkable -Pin SOIC Cooltab TM packages. Part Number Package Type IXRP -Pin DIP IXRS -Pin SOIC IXRS -Pin SOIC Warning: The IXR is ESD Sensitive Precaution: when performing the High-Voltage tests, adequate safety precautions should be taken! *Operational voltage rating of 00V determined in a typical half-bridge circuit configuration (refer to Figure and Figure ). Operational voltage in other circuit configurations may vary. Up to 00V IXRS IXRS 00 IXYS CORPORATION All rights reserved DS0G(/0)

2 IXR Figure - IXR Functional Block Diagram VDD VCH VCH Low to High OUT RST IN UVCC Detect Gate Current Output Isolated High Side VDD VCL VCL Low to High Side Delay Equalizer and Shutdown Shutdown Logic UVCC Detect Gate Current Output Ω Pin Description and Configuration SYMBOL FUTION DESCRIPTION VDD Logic Supply Positive power supply for chip CMOS functions Input High side input signal, TTL or CMOS compatible; in phase Input Low side input signal, TTL or CMOS compatible; in phase Enable Chip enable, active low. When driven high, both outputs go low Ground Logic reference ground VCH Supply Voltage High side power supply, referenced to Output High side driver output Return High side voltage return pin VCL Supply Voltage Low side power supply, referenced to Output Low side driver output Ground Low side voltage return pin -PIN DIP -PIN SOIC -PIN SOIC w/cooltab TM N/C VDD VCH IXRP N/C VCL IXRS IXRS Cooltab is a trademark of IXYS Corporation IXYS reserves the right to change limits, test conditions, and dimensions.

3 IXR Absolute Ratings Symbol Definition Min Max Units High side floating supply voltage V V High side floating supply offset Voltage V V High side floating output voltage V V Low side fixed supply voltage -0. V V Low side output voltage V Logic supply voltage V V Logic supply offset voltage V -. V +. V V IN Logic input voltage( & ) V V dv S /dt Allowable offset supply voltage transient 0 V/ns P D Package power dissipation@ T A C. W P D Package power dissipation@ T C C. W R THJA Thermal resistance, junction-to-ambient 0 K/W Recommended Operating Conditions Symbol Definition Min Max Units High side floating supply absolute voltage V + V +0 V V High side floating supply offset voltage V V High side floating output voltage V +0 V Low side fixed supply voltage 0 V V Low side output voltage 0 V CC V Logic supply voltage V + V + V V Logic supply offset voltage V -0. V +0. V V IN Logic input voltage(,, ENbar) V V T A Ambient Temperature -0 o C 00 IXYS CORPORATION All rights reserved

4 Dynamic Electrical Characteristics* = = = +V, C load = nf, and V = V unless otherwise specified. The dynamic electrical characteristics are measured using Figure. IXR Symbol Definition Test Conditions Min Typ Max Units t on Turn-on propagation delay V = 0V 0 0 ns t off Turn-off propagation delay V = 00V ns t enb Device not enable delay 0 ns t r Turn-on rise time ns t f Turn-off fall time ns t dm Delay matching, & turn-on/off 0 ns Static Electrical Characteristics Symbol Definition Test Conditions Min Typ Max Units V INH Logic input voltage,,, = = V. V V INL Logic 0 input voltage,,, = = V 0 V V H / / V H High level output voltage, I O = 0A 0. V -V or -V V L / / V L Low level output voltage, I O = 0A 0. V V or V I HL to bias current. V = = 00V 0 µa I Q Quiescent supply current V IN = 0V or = V ma I Q Quiescent supply current V IN = 0V or = V ma I QDD Quiescent supply current V IN = 0V or = V 0 µa I IN + Logic input bias current V IN = 0 0 µa I IN - Logic 0 input voltage V IN = 0V µa UV + supply undervoltage positive going threshold.... V UV - supply undervoltage negative going threshold... V UV + supply undervoltage positive going threshold... V UV - supply undervoltage negative going threshold... V I GO + or Output high short circuit current; V GO = V, V IN = V, PW<us A I GO - or Output low short circuit current; V GO = 0V, V IN =0V, PW<us - - A * These characteristics are guaranteed by design only. Tested on a sample basis. IXYS reserves the right to change limits, test conditions, and dimensions.

5 IXR / 0% t enb / / % Figure. INPUT/OUPUT Timing Diagram Figure. ENABLE Waveform Definitions / tdon 0% 0% tr tdoff 0% 0% tf 0% 0% Input Signal 0% tdm / % % % tdm Outgoing Signal Figure. Definitions of Switching Time Waveforms Figure. Definitions of Delay Matching Waveforms uf 0. uf VCL=V IXR 0. uf CL CL uf VCH + - V uf (0 to 00V) V++ Buss (V ) 00V 00V 00V ~ ~ 0 Sample Tested for Operation ~ 00kHz 00kHz MHz f PWM Figure. Switching Time Test Circuit Figure. Device operating range: Buss voltage vs. Frequency Tested in typical circuit configuration (refer to Figure & ) 00 IXYS CORPORATION All rights reserved

6 NDYC uf/v IXRS 0/W 0/W IXR V V U Vin L Vout GND V U IXR VDD VCH VCL C + uf C 0.uF C 0.uF GND + C uf L 00uH GND DSEI -A D GND + C 0uF/0V OUTPUT MONITOR HV SCOPE PROBE dvs/dt > 0V/ns BATTERY GND HV 00V PUE B GND U HCPL-J ½ VEE VCC OUT V V K U,, IXDD, C 0.uF C uf Q IXFPN0Q D DSEI-A Measure dv/dt (HV Scope Probe) GND -00V GND Figure. Test circuit for allowable offset supply voltage transient. VIN+ Up to 00V IXCP M0S uf/v MLCC VOUT- VOUT+ GND VOUT- VOUT+ k 0 uf/v MLCC k k k uf/v. N. N IXTHN0P uh 0.uF IXTHN0P 0.uF 0.uF/kV uf/v uf/v MLCC Figure. Test circuit for high frequency, 0kHz, operation.,, = V IXYS reserves the right to change limits, test conditions, and dimensions.

7 NDYC uf/v IXRS IXR VIN+ Up to 00V IXCP M0S uf/v MLCC VOUT- VOUT+ GND VOUT- VOUT+ k 0 uf/v MLCC k k k uf/v.. N N IXTHN0P IXTHN0P 0.uF/kV uf/v uf/v MLCC Figure. Test circuit for low frequency, khz, operation.,, = V 00 IXYS CORPORATION All rights reserved

8 IXR Time - nanoseconds 0 0 Max. t off Typ. t off Max. t on Typ. t on Time - nanoseconds Max. t off Typ. t off Max. t on Typ. t on Temperature - Degrees C Fig. a. Low side turn-on and turn-off delay times vs. temperature Temperature - Degrees C Fig. b. High side turn-on and turn-off times vs. temperature. 0 0 Time - nanonseconds Max. t on Max. t off Typ. t on Time - nanaseconds Max. t off Max. t on Typ. t on Typ. t off 0 Typ. t off VCL Supply Voltage - Volts VCH Supply Voltage - Volts Fig. a. Low side turn-on and turn-off delay times vs.. Fig. b. High side turn-on and turn-off delay times vs.. 00 Time - nanaseconds Max. t off Typ. t off Max. t on Typ. t on Time - nanoseconds Max. t off Typ. t off Max. t on Typ. t on 0 0 VDD Supply Voltage- Volts Fig. a. Low side turn-on and turn-off delay times vs. supply voltage. 0 VDD Supply Voltage - Voltage Fig. b. High side turn-on and turn-off delay times vs.. IXYS reserves the right to change limits, test conditions, and dimensions.

9 IXR 00 0 Enable Delay Time - ns Max. High Side 0 Typ. High Side 0 Max. Low side Typ. Low side Enable Delay Time - ns 00 Max. High Side 0 Typ. High Side 0 Max. Low side Typ. Low side Enable Delay Time - ns Temperature - Degrees C Fig. a. High and Low side ENABLE (Shutdown) times vs. temperature. Max. High Side Typ. High Side Max. Low side Typ. Low side VDD Supply Voltage - Volts Fig. c. High and Low side ENABLE (Shutdown) times vs. supply voltage. Turn-on & Turn-off Rise Time - ns 0 0 VCL/VCH Supply Voltage - Volts Fig.b. High and Low side ENABLE (Shutdown) times vs. supply voltage. Max. turn-on Typ. turn-on Typ. turn-off Max. turn-off Temperature - Degrees C Fig. a. Turn-on and turn-off rise times vs. temperature. Turn-on Rise Time - ns 0 Max. High Side Typ. High Side Max. Low side Typ. Low side Turn-off Fall Time - ns 0 Max. High Side Max. Low side Typ. High Side Typ. Low side 0 0 VCL/VCH Supply Voltage - Volts Fig. b. Turn-on rise times vs. bias supply voltages. 0 0 VCL/VCH Supply Voltage - Volts Fig. c. Turn-off delay times vs. bias supply voltages. 00 IXYS CORPORATION All rights reserved

10 Output Source Current (A) Output Source Current (A) Case Offset Supply Leakage Current - IXR Logic Input Threshold - Volts Max Logic Min Logic 0 & Max Logic V = V CH & Min Logic Logic Supply Voltage - Volts Fig.. Logic input threshold voltage vs bias supply voltage. µa Temperature - Degrees C Fig.. Offset supply leakage current vs. temperature. Logic Input Bias Current - A µ Logic Supply Voltage (V) Fig.. Logic input current vs. bias voltage Temperature - Degrees C Fig. a. Output source current vs. temperature Frequency - khz Fig. 0. IXRS Case temperature rise vs. operating frequency Load: IXTU0N0 V = 00V V = 0V V = 0V V BIAS Supply Voltage (V) Fig. b. Output source current vs supply voltatge IXYS reserves the right to change limits, test conditions, and dimensions.

11 IXR Output Current - Amperes Minimum Output Current - Amperes Minimum Fig. a. Output sink current vs. temperature Bias Voltage - Volts Fig. b. Output sink current vs. bias voltage Undervoltage Lockout (+) - Volts Max Typ Min Undervoltage Lockout (-) - Volts Max Typ Min Fig. a. Undervoltage positive trip vs. temperature. Fig. b. Undervoltage negative trip vs. temperature. Undervoltage Lockout (+) - Volts Max Typ Min Fig. a. Undervoltage positive trip vs. temperature. Undervoltage Lockout (-) - Volts Max Typ Min Fig. b. Undervoltage negative trip vs. temperature. 00 IXYS CORPORATION All rights reserved

12 o o IXR 0 0 VCH Current - µa VCH Current - µa Current - µa C Case Temperature Fig. a. Quiescent current vs. temperature for the high side power supply Fig.. Quiescent current vs. temperature for the low side power supply Load Conditions: A: = 00V B: = 00V C: =00V D: =00V E: = 00V F: = 00V A C E B D F C Case Temperature Voltage - Volts Fig. b. Quiescent current vs. voltage for the high side power supply. A B C D Load Conditions: A: = 00V B: = 00V C: =00V D: =00V E: = 00V F: = 00V E F Frequency - khz Fig. a. Case temperature rise vs. switching frequency for IXRS Frequency - khz Fig. b. Case temperature rise vs. switching frequency for IXRS IXYS reserves the right to change limits, test conditions, and dimensions.

13 IXR A b b c D D E E e ea eb L E H e D B A A B C D E e H h L M N h x %%d N L c M E H D A e h e B D A h x E L c 00 IXYS CORPORATION All rights reserved