Single Serial Input PLL Frequency Synthesizer

Transcription

1 FUJITSU SEMICODUCTO DT SHEET DS E SSP Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz prescaler DESCIPTIO The Fujitsu is serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. 2/ or a /5 can be selected for the prescaler that enables pulse swallow operation. The latest BiCMOS process technology is used, resuitantly a supply current is limited as low as.5 m typ. This operates with a supply voltage of.0 V (typ.) Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. s a result of this, is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile Communications). FETUES High frequency operation: 2.5 GHz max. (@ P = /5) 2.0 GHz max. (@ P = 2/) Low power supply voltage: VCC = 2.7 to. V Very Low power supply current: ICC =.5 m typ. (VCC = V) Power saving function: IPS = 0.1 µ typ. (VCC = V) Pulse swallow function: 2/ or /5 Serial input 1-bit programmable reference divider: = 5 to 1,8 Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter: 0 to Binary 11-bit programmable counter: 5 to 2,07 Wide operating temperature: Ta = 0 to +85 C Plastic 1-pin SSOP package (FPT-1P-M05) and 1-pads BCC package (LCC-1P-M02) PCKGES 1-pin, plastic SSOP 1-pads, plastic BCC (FPT-1P-M05) (LCC-1P-M02)

2 To Top / Lineup / Index PI SSIGMETS SSOP-1 pin OSCI 1 1 φ OSCOUT 2 15 φp VP 1 LD/fout VCC DO 5 Top View 1 12 ZC PS GD 11 LE Xfin 7 10 Data fin 8 9 Clock (FPT-1P-M05) BCC-1 pads OSCI φ OSCOUT φp VP 2 1 LD/fout VCC DO GD 5 Top view ZC PS LE Xfin Data fin Clock (LCC-1P-M02) 2

3 PI DESCIPTIOS SSOP-1 Pin no. BCC-1 Pin name I/O 1 1 OSCI I Descriptions Programmable reference divider input. Oscillator input. Connection for an crystal or a TCXO. TCXO should be connected with a coupling capacitor. 2 1 OSCOUT O Oscillator output. Connection for an external crystal. 2 VP Power supply voltage input for the charge pump. VCC Power supply voltage input. 5 DO O Charge pump output. Phase of the charge pump can be reversed by FC bit. 5 GD Ground. 7 Xfin I 8 7 fin I 9 8 Clock I 10 9 Data I LE I PS I 1 12 ZC I 1 1 LD/fout O 15 1 φp O 1 15 φ O Prescaler complementary input, and should be grounded via a capacitor. Prescaler input. Connection with an external VCO should be done with C coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Control bit = H ; Data is transmitted to the programmable reference counter. Control bit = L ; Data is transmitted to the programmable counter. Load enable signal input (Open is prohibited.) When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. Power saving mode control. This pin must be set at L at Power-O. (Open is prohibited.) PS = H ; ormal mode PS = L ; Power saving mode Forced high-impedance control for the charge pump (with internal pull up resistor.) ZC = H ; ormal DO output. ZC = L ; DO becomes high impedance. Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected by LDS bit in the serial data. LDS = H ; outputs fout (fr/fp monitoring output) LDS = L ; outputs LD ( H at locking, L at unlocking.) Phase comparator output for an external charge pump. ch open drain output. Phase comparator output for an external charge pump. CMOS output.

4 To Top / Lineup / Index BLOCK DIGM OSC I 1 OSCOUT 2 PS 12 LE 11 Data 10 Crystal oscillator circuit Intermittent mode control (power save) 1-bit control latch LE Programmable reference divider Binary 1-bit reference counter 17-bit latch 1-bit latch C T SW -bit latch 19-bit shift register 19-bit shift register fr LDS FC fp fr fp LD LD/fr/fp selector Phase comparator Lock detector Super charger 1 φ 15 φp 1 LD/fout 1 ZC V P Clock 9 5 D O LE 7-bit latch 18-bit latch 11-bit latch SW Programmable divider Xfin 7 fin 8 GD Prescaler 2/, /5 Binary 7-bit swallow counter Binary 11-bit programmable counter fp V CC MD Control circuit ote: SSOP-1 pin

5 BSOLUTE MXIMUM TIGS Parameter Symbol ating Min. Max. Unit emark Power supply voltage VCC V VP VCC +.0 V Input voltage VI 0.5 VCC +0.5 V Output voltage VO 0.5 VCC +0.5 V Output current IO m Except DO output Ido m DO output Storage temperature Tstg C WIG: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ECOMMEDED OPETIG CODITIOS Parameter Symbol Value Min. Typ. Max. Unit Power supply voltage VCC V VP VCC.0 V Input voltage VI GD VCC V Operating temperature Ta C emark WIG: ecommended operating conditions are normal operating ranges for the semiconductor device. ll the device s electrical characteristics are warranted when operated within these ranges. lways use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. o warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. HandIing Precautions This device should be transported and stores in anti-static containers. This is a static-sensitive device; take proper anti-esd precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. lways turn the power supply off before inserting or removing the device from its socket. Protect leads with a conductive sheet when handling or transporting PC boards with devices. 5

6 To Top / Lineup / Index ELECTICL CHCTEISTICS Parameter Symbol Condition *1: Conditions; VCC =.0 V, Ta = +25 C, in locking state. *2: VCC =.0 V, fosc = 12.8 MHz, Ta = +25 C, in power saving mode. *: C coupling with a 1000 pf capacitor connected. *: The symbol (minus) means direction of current flow. *5: Ta = +25 C (VCC = 2.7 to. V, Ta = 0 to +85 C) Value Unit Min. Typ. Max. fin = 2500 MHz, Power supply current* 1 ICC *1.5 m fosc = 12 MHz, P = /5 Power saving current Ips *2 ZC = H or open 10 µ Operating frequency Crystal oscillator operating frequency Input sensitivity Input voltage Input current Output voltage High impedance cutoff current Output current fin * fin P = 2/ P = / MHz fosc min. 500 mvp-p 0 MHz Vfin 50 Ω system (efer to the test circuit.) dbm OSCI * VOSC 0.5 VCC VP-P Data, Clock, LE, PS, ZC Data, Clock, LE, PS ZC OSCI VIH VCC 0.7 VIL VCC 0. IIH * IIL * IIH * IIL * Pull up input IIH IIL * φp VOL Open drain output 0. V φ, LD/fout DO DO VOH VCC = V, IOH = 1 m VCC 0. VOL VCC = V, IOL = 1 m 0. VDOH VCC = V, IOH = 1 m VP 0. VDOL VCC = V, IOL = 1 m 0. IOFF VCC = V, VP = V VOOP = GD to V V µ µ µ.0 n φp IOL Open drain output 1.0 m φ, LD/fout DO IOH * 1.0 IOL 1.0 IDOH *, 5 VCC = V, VP = V, VDOH = 2.0 V, Ta = +25 C IDOL * VCC = V, VP = V VDOL = 1.0 V, Ta = +25 C V V m m

7 FUCTIO DESCIPTIOS 1. Pulse Swallow Function The divide ratio can be calculated using the following equation: fvco = [(M ) + ] fosc ( < ) fvco : Output frequency of external voltage controlled oscillator (VCO) : Preset divide ratio of binary 11-bit programmable counter (5 to 2,07) : Preset divide ratio of binary 7-bit swallow counter (0 127) fosc : Output frequency of the reference frequency oscillator : Preset divide ratio of binary 1-bit programmable reference counter (5 to 1,8) M : Preset divide ratio of modules prescaler (2 or ) 2. Serial Data Input Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high, stored data is latched according to the control bit data as follows: Table.1 Control Bit Control bit (CT) H L Destination of serial data 17 bit latch (for the programmable reference divider) 18 bit latch (for the programmable divider) (1) Shift register configuration Programmable reference counter LSB Data flow MSB C T SW FC LDS CT : Control bit [Table. 1] 1 to 1 : Divide ratio setting bit for the programmable reference counter (5 to 1,8) [Table. 2] SW : Divide ratio setting bit for the prescaler (2/ or /5) [Table. 5] FC : Phase control bit for the phase comparator [Table. 7] LDS : LD/fout signal select bit [Table. ] ote: Start data input with MSB first 7

8 To Top / Lineup / Index Programmable reference counter LSB Data flow MSB C T CT : Control bit [Table. 1] 1 to 11 : Divide ratio setting bits for the programmable counter (5 to 2,07) [Table. ] 1 to 7 : Divide ratio setting bits for the swallow counter (0 to 127) [Table. ] ote: Start data input with MSB first Table.2 Binary 1-bit Programmable eference Counter Data Setting Divide ratio () ote: Divide ratio less than 5 is prohibited. Table. Binary 11-bit Programmable Counter Data Setting Divide ratio () ote: Divide ratio less than 5 is prohibited. 8

9 Table. Binary 7-bit Swallow Counter Data Setting Divide ratio () Table.5 Prescaler Data Setting SW Prescaler divide ratio H 2/ L /5 Table. LD/fout Output Select Data Setting LDS H fout signal L LD signal LD/fout output signal (2) elation between the FC input and phase characteristics The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the phase comparator output (φ, φp) are reversed according to the FC bit. lso, the monitor pin (fout) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φ, and φp is shown below. Table.7 FC Bit Data Setting (LDS = H ) FC = High FC = Low DO φ φp LD/fout DO φ φp LD/fout fr > fp H L L L H Z* fr < fp L H Z* fout = fr H L L fout = fp fr = fp Z* L Z* Z* L Z* * : High impedance 9

10 To Top / Lineup / Index When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics. : When the LPF and VCO characteristics are similar to (1), set FC bit high. : When the VCO characteristics are similar to (2), set FC bit low. VCO output frequency (1) PLL LPF VCO (2) LPF input voltage Table.8 PS Pin Setting Table.9 ZC Pin Setting PS pin H L ZC pin H L Status ormal mode Power saving mode DO output ormal output High impedance 10

11 . Power Saving Mode (Intermittent Mode Control Circuit) Setting a PS pin to Low, the IC enters into power saving mode resultatly current consumption can be limited to 10 µ (max.). Setting PS pin to High, power saving mode is released so that the IC works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from the power saving mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up, thus keeping the loop locked. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 µ (max.). ote: While the power saving mode is executed, ZC pin should be set at H or open. If ZC is set at L during power saving mode, approximately 10 µ current flows. PS pin must be set L at Power-O. The power saving mode can be released (PS : L H) 1µs later after power supply remains stable. During the power saving mode, it is possible to input the serial data. O VCC Clock Data LE PS (1) (2) () (1) PS = L (power saving mode) at Power-O (2) Set serial data after power supply remains stable. () elase power saving mode (PS : L H) after setting serial data. 11

12 To Top / Lineup / Index. Serial Data Input Timing 1st. data 2nd. data Control bit Invalid data Data MSB ~ ~ LSB ~ Clock t7 t1 t2 t t LE ~ t t5 On rising edge of the clock, one bit of the data is transferred into the shift register. Parameter Min. Typ. Max. Unit Parameter Min. Typ. Max. Unit t1 20 ns t5 100 ns t2 20 ns t 20 ns t 0 ns t7 100 ns t 0 ns 12

13 PHSE COMPTO OUTPUT WVEFOM fr fp twu twl LD [ FC = H ] φp φ DO H Z L [ FC = L ] φp φ DO L Z H otes: 1. Phase error detection range: 2π to +2π 2. Pulses on DO output signal during locked state are output to prevent dead zone.. LD output becomes low when phase is twu or more. LD output becomes high when phase error is twl or less and continues to be so for three cycles or more.. twu and twl depend on OSCI input frequency. twu > /fosc (e. g. twu > 12.5 ns, foscin = 12.8 MHz) twl < 8/fosc (e. g. twl < 25.0 ns, foscin = 12.8 MHz) 5. LD becomes high during the power saving mode (PS = L.) 1

14 To Top / Lineup / Index TYPICL CHCTEISTICS 1. fin Input Sensitivity Input sensitivity (V fin) Input frequency vs. Input sensitivity (Prescaler = /5) (dbm) +10 Ta = +25 C ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, SPEC 0 VCC = 2.7 V VCC =.0 V VCC =. V (MHz) Input frequency (fin) Input sensitivity (V fin) (dbm) Input frequency vs. Input sensitivity (Prescaler = 2/),,,,,,,,,,,,,,,,,,,,,,,,,,,,,, SPEC,,,,,,,,,,,,,,, Ta = +25 C 0 VCC = 2.7 V VCC =.0 V VCC =. V (MHz) Input frequency (fin) 1

15 2. OSCI Input Sensitivity (dbm) +10 0,,,,,,,,,,,, SPEC Input frequency vs. Input sensitivity Ta = +25 C Input sensitivity (VOSC) VCC = 2.7 V VCC =.0 V VCC =. V (MHz) Input frequency (fosc) 15

16 To Top / Lineup / Index. DO Output Current (V) IOH vs. VOH Ta = +25 C VCC =.0 V VP =.0 V, 5.0 V.5000 /div VOH IDO 2.500/div (m) IOH (V) IOL vs. VOL Ta = +25 C VCC =.0 V VP =.0 V, 5.0 V.5000 /div VOL IDO 2.500/div (m) IOL 1

17 . fin Input Impedance 1; 2; Ω Ω 1 GHz Ω 10.8 Ω 1.5 GHz ; Ω Ω 2 GHz 2 ;.9 Ω 8.07 Ω 2.5 GHz 1 5. OSCI Input Impedance 1;.5 kω 19.0 kω MHz 2; Ω 5.75 kω 10 MHz ; Ω kω 20 MHz 12 ; 1.8 Ω kω 0 MHz 17

18 To Top / Lineup / Index TEST CICUIT (FO MESUIG IPUT SESITIVITY fin/osci) VCC VP 0.1 µf S G 50 Ω 1000 pf 1000 pf 0.1 µf pf 50 Ω S G Controller (setting divide ratio) VCC Oscilloscope ote: SSOP-1 pin 18

19 PPLICTIO EXMPLE VP LPF VCO Output 10 kω 12 kω Lock detect. 12 kω 10 kω From a controller φ φp LD/fout ZC PS LE Data Clock OSCI OSCOUT VP VCC DO GD Xfin fin C1 X tal C pf 1000 pf 0.1 µf 0.1 µf C1, C2: Depend on the crystal parameters VP: V max. ote: SSOP-1 pin 19

20 To Top / Lineup / Index ODEIG IFOMTIO Part number Package emarks PFV1 PV 1-pin, plastic SSOP (FPT-1P-M05) 1-pads, plastic BCC (LCC-1P-M02) 20

21 PCKGE DIMESIOS 1-pin, plastic SSOP (FPT-1P-M05) * : These dimensions do not include resin protrusion. * 5.00±0.10(.197±.00) (.00) (Mounting height) IDEX *.0±0.10.0± (.21) (.17±.00) (.252±.008) OM 0.5±0.12 (.025±.007) "" Details of "" part 0.10±0.10(.00±.00) (STD OFF).55(.179)EF ±0.20 (.020±.008) C 199 FUJITSU LIMITED F101S-2C- Dimensions in mm (inches) (Continued) 21

22 To Top / Lineup / Index (Continued) 1-pins, plastic BCC (LCC-1P-M02) * : These dimensions do not include resin protrusion. 1.55±0.10 (.179±.00) (.02)MX (Mouting height) 9.0(.1)TYP 0.5(.02)TYP 1 0.0±0.10 (.01±.00).0±0.10 (.19±.009) 5 2.5(.09) TYP "" "B" 1.15(.05)TYP E-MK 1 0.0(.01) 0.085±0.0 (.00±.002) (STD OFF) 0.80(.02) TYP 0.25±0.10 (.01±.00) 1.725(.08) TYP (.002) Details of "" part 0.75±0.10 (.00±.00) Details of "B" part 0.0±0.10 (.02±.00) 0.0±0.10 (.01±.00) 0.0±0.10 (.02±.00) C 199 FUJITSU LIMITED C101S-1C-1 Dimensions in mm (inches) 22

23 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KWSKI PLT, -1-1, Kamikodanaka akahara-ku, Kawasaki-shi Kanagawa , Japan Tel: (0) Fax: (0) orth and South merica FUJITSU MICOELECTOICS, IC. Semiconductor Division 55 orth First Street San Jose, C , U.S.. Tel: (08) Fax: (08) Customer esponse Center Mon. Fri.: 7 am 5 pm (PST) Tel: (800) Fax: (08) Europe FUJITSU MIKOELEKTOIK GmbH m Siebenstein -10 D-0 Dreieich-Buchschlag Germany Tel: (010) 90-0 Fax: (010) sia Pacific FUJITSU MICOELECTOICS SI PTE. LIMITED #05-08, 151 Lorong Chuan ew Tech Park Singapore 5571 Tel: (5) Fax: (5) ll ights eserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. lso, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CUTIO: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. ny semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9710 FUJITSU LIMITED Printed in Japan 2