PLL FrequencySynthesizer MB15F03L

Transcription

1 FUJITSU SEMICODUCTO DT SHEET DS0-0-E SSP Dual Serial Input PLL FrequencySynthesizer MBF0L DESCIPITO The Fujitsu MBF0L is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 800MHz and a 0MHz prescalers. 6/6 or a 8/9 for the 800MHz prescaler, and a 6/7 or a / for 0MHz prescaler can be selected that enables pulse swallow operation. The latest BiCMOS process technology is used, resuitantly a supply current is limited as low as.0m typ. at a supply voltage of.0v. Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. s a result of this, MBF0L is ideally suitable for digital mobile communications, such as PHS(Personal Handy Phone System), PC (Personal Communication etwork) and PCS(Personal Communication Service). FETUES High frequency operation F synthesizer: 800MHz max. / IF synthesizer: 0MHz max. Low power supply voltage: VCC =.7 to.6v Very Low power supply current : ICC =.0 m typ. (Vcc = V) Power saving function : Supply current at power saving mode Typ.0.µ (Vcc=V), Max.0µ (IPS=IPS) Dual modulus prescaler : 800MHz prescaler(6/6,8/9), 0MHz prescaler(6/7,/) Serial input bit programmable reference divider: = to 6,8 Serial input 8bit programmable divider consisting of: - Binary 7bit swallow counter: 0 to 7 - Binary bit programmable counter: to,07 Onchip high performance charge pump circuit and phase comparator, achieving highspeed lockup and low phase noise Onchip phase control for phase comparator Wide operating temperature: Ta = -0 to 8 C PCKGE 6-pin, Plastic SSOP 6-pin, Plastic BCC (FPT-6P-M0) (LCC-6P-M0)

2 MBF0L PI SSIGMET SSOP-6-PI GDF 6 Clock OSCin Data GDIF LE finif VccIF TOP VIEW finf VccF LD/fout 6 XfinF PSIF 7 0 PSF DoIF 8 9 DoF (FPT-6P-M0) BCC-6-PI GDF Clock OSCin 6 Data GDIF LE finif VCCIF TOP VIEW finf VCCF LD/fout 0 XinF PSIF PSF DOIF DOF (LCC-6P-M0)

3 MBF0L PI DESCIPTIO SSOP-6 Pin o. BCC-6 Pin name I/O 6 GDF Ground for FPLL section. Descriptions OSCin I The programmable reference divider input. TCXO should be connected with a C coupling capacitor. GDIF Ground for the IF-PLL section. finif I Prescaler input pin for the IF-PLL. The connection with VCO should be C coupling. VccIF Power supply voltage input pin for the IF-PLL section. 6 LD/fout O 7 6 PSIF I 8 7 DoIF O 9 8 DoF O 0 9 PSF I 0 XfinF I VccF finf I LE I Data I 6 Clock I Lock detect signal output (LD) / phase comparator monitoring output (fout) The output signal is selected by a LDS bit in a serial data. LDS bit = H ; outputs fout signal LDS bit = L ; outputs LD signal Power saving mode control for the IF-PLL section. This pin must be set at L Power-O. (Open is prohibited.) PSIF = H ; ormal mode PSIF = L ; Power saving mode Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Charge pump output for the F-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Power saving mode control for the F-PLL section. This pin must be set at L Power-O. (Open is prohibited.) PSF = H ; ormal mode PSF = L ; Power saving mode Prescaler complimentary input for the F-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the F-PLL section, the shift register and the oscillator input buffer. When power is OFF, latched data of F- PLL is cancelled. Prescaler input pin for the F-PLL. The connection with VCO should be C coupling. Load enable signal input (with the schmitt trigger circuit.) When LE is H, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input (with the schmitt trigger circuit.) data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, F-ref. counter, F-prog. counter) according to the control bit in a serial data. Clock input for the -bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a rising edge of the clock.

4 MBF0L BLOCK DIGM VccIF GDIF 7 PSIF Intermittent mode control (IFPLL) -bit latch 7-bit latch LDS SWIF FCIF Binary 7-bit swallow counter (IFPLL) -bit latch Binary -bit programmable counter(ifpll) fpif Phase comp. (IFPLL) Charge pump (IFPLL) Super charger 8 DoIF finif Prescaler (IFPLL) 6/7,/ -bit latch -bit latch Lock Det. (IFPLL) T T Binary bit programmable ref. frif counter(ifpll) LDI OSCin finf XfinF PSF 0 O Prescaler (FPLL) 6/6, 8/9 Intermittent mode control (FPLL) T T -bit latch LDS SWF FCF -bit latch Binary -bit programmable ref. counter(fpll) -bit latch Binary 7-bit swallow counter (FPLL) 7-bit latch frf Binary -bit programmable counter(fpll) -bit latch fpf LDF Lock Det. (FPLL) Phase comp. (FPLL) D Charge pump (FPLL) Selector LD frif frf fpif fpf Super charger 6 LD/fout 9 DoF LE Schmitt circuit Latch selector Data Clock 6 Schmitt circuit Schmitt circuit C C -bit shift register VCCF GDF ote: SSOP-6 pin

5 MBF0L BSOLUTE MXIMUM TIGS Parameter Symbol ating Unit emark Power supply voltage VCC 0. to +.0 V Input voltage VI 0. to VCC +0. V Output voltage VO 0. to VCC +0. V IO 0 to +0 m Except Do Output current Ido to + m Do output Storage temperature TSTG to + C WIG: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ECOMMEDED OPETIG CODITIOS Parameter Symbol Value Min Typ Max Unit ote Power supply voltage VCC V VCCIF=VCCF Input voltage Vi GD VCC V Operating temperature Ta 0 +8 C WIG: ecommended operating conditions are normal operating ranges for the semiconductor device. ll the device s electrical characteristics are warranted when operated within these ranges. lways yse semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. o warranty is made with repect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. Handling Precautions This device should be transported and stored in anti-static containers. This is a static-sensitive device; take proper anti-esd precautions. Ensure that personnel and equipment are properly grounded. Cover workerbenches with grounded conductive mats. lways turn the power supply off before inserting or removing the device from its socket. Protect leads with a conductive sheet when handling or transporting PC boards with devices.

6 MBF0L ELECTICL CHCTEISTICS Parameter Symbol Condition Power supply current Power saving current Operating frequency Input sensitivity Input voltage Input current Output voltage High impedance cutoff current ICCIF * ICCF * IpsIF IpsF finif =.MHz, fosc = MHz finf = 800MHz, fosc = MHz VccIF current at PSIF = L VccF current at PSIF/F = L (Vcc=.7V to.6v, Ta=-0 C to 8 C) Value Unit Min. Typ. Max * 0 0. * 0 finif * finif IFPLL 0 0 finf * finf FPLL OSCin fosc 0 m µ MHz finif VfinIF IFPLL, 0Ω termination 0 + dbm finf VfinF FPLL, 0Ω termination 0 + dbm OSCin VOSC 0. VCC Vp-p Data, Clock, LE PSIF, PSF Data, Clock, LE, PSIF, PSF OSCin LD/fout DoIF, DoF DoIF, DoF VIH Schmitt trigger input VCCx VIL Schmitt trigger input VCCx0. 0. VIH VCCx0.7 VIL VCCx0. IIH * IIL * IIH IIL * 00 0 VOH IOH=.0m VCC0. VOL IOL=.0m 0. V VDOH IDOH =.0m VCC0. VDOL VCC=.0V, IDOL=.0m 0. V IOFF VCC=.0V, VOFF=GD to VCC.0 n V V µ µ (Continued) 6

7 MBF0L (Continued) Output current Parameter Symbol Condition LD/fout DoIF, DoF *: Conditions ; VccIF = V, Ta = C, in locking state. *: Conditions ; VccF = V, Ta = C, in locking state. *: fosc =.8 MHz, Vcc =.0V, Ta = C *: C coupling with a 000pF capacitor connected. *: The symbol "-"(minus) means direction of current flow. (Vcc=.7V to.6v, Ta=-0 C to 8 C) Value Unit Min. Typ. Max. IOH * Vcc =.0V.0 IOL Vcc =.0V.0 Vcc =.0V, IDOH * VDOH = 6.0V, Ta= C Vcc =.0V, VDOL = IDOL 8.0V, Ta= C m m 7

8 MBF0L FUCTIOL DESCIPTIOS The divide ratio can be calculated using the following equation: fvco = {(P x ) + } x fosc ( < ) fvco: Output frequency of external voltage controlled oscillator (VCO) P: Preset divide ratio of dual modulus prescaler (6 or for IF-PLL, 6 or 8 for F-PLL) : Preset divide ratio of binary -bit programmable counter ( to,07) : Preset divide ratio of binary 7-bit swallow counter (0 7) fosc: eference oscillation frequency : Preset divide ratio of binary -bit programmable reference counter ( to 6,8) Serial Data Input Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/FPLL sections, programmable reference dividers of IF/F PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. Table. Control Bit Control bit C C Destination of serial data L L The programmable reference counter for the IF-PLL. H L The programmable reference counter for the F-PLL. L H The programmable counter and the swallow counter for the IF-PLL H H The programmable counter and the swallow counter for the F-PLL Shift egister Configuration Programmable eference Counter LSB Data Flow MSB C C T T X X X X X C, : Control bit [Table. ] to : Divide ratio setting bits for the programmable reference counter ( to 6,8) [Table. ] T, : Test purpose bit [Table.] X : Dummy bits(set "0" or "") ote: Data input with MSB first. 8

9 MBF0L Programmable Counter LSB Data Flow MSB C C L D S S W F C IF/F IF/F C, : Control bit [Table. ] to : Divide ratio setting bits for the programmable counter ( to,07) [Table. ] to 7 : Divide ratio setting bits for the swallow counter (0 to 7) [Table. ] SWIF/F : Divide ratio setting bit for the prescaler (6/7 or / for the IF-PLL, 6/6 or 8/9 for the F-PLL) [Table. 6] FCIF/F : Phase control bit for the phase detector [Table. 7] LDS : LD/fout signal select bit [Table. 8] ote: Data input with MSB first. Divide ratio () Table. Binary -bit Programmable eference Counter Data Setting ote: Divide ratio less than is prohibited T T LD/fout pin state Table. Test Purpose Bit Setting L L Outputs frif. H L Outputs frf. L H Outputs fpif. H H Outputs fpf. 9

10 MBF0L Divide ratio () ote: Divide ratio less than is prohibited. ote: Divide ratio () range = 0 to 7 Table. Binary -bit Programmable Counter Data Setting Table. Binary 7-bit Swallow Counter Data Setting Divide ratio () Table. 6 Prescaler Data Setting Prescaler divide ratio SW = H SW = L IF-PLL 6/7 / F-PLL 6/6 8/9 Table. 7 Phase Comparator Phase Switching Data Setting FCIF,F = H FCIF,F = L () DoIF,F DoIF,F fr > fp H L fr = fp Z Z fr < fp L H VCO polarity () () VCO Output Frequency ote: Z = Highimpedance Depending upon the VCO and LPF polarity, FC bit should be set. VCO Input Voltage () Table. 8 LD/fout Output Select Data Setting LDS H L LD/fout output signal fout (frif/f, fpif/f) signals LD signal 0

11 MBF0L Serial Data Input Timing st. data nd. data Control bit Invalid data Data MSB LSB Clock t t t t 7 t LE t t 6 On rising edge of the clock, one bit of the data is transferred into the shift register. Parameter Min Typ Max Unit Parameter Min Typ Max Unit t 0 ns t 0 ns t 0 ns t6 00 ns t 0 ns t7 00 ns t 0 ns

12 MBF0L PHSE DETECTO OUTPUT WVEFOM frif/f fpif/f twu twl LD (FC bit = High) DoIF/F Z H L (FC bit = Low) DoIF/F Z LD Output Logic Table IFPLL section FPLL section LD output Locking state / Power saving state Locking state / Power saving state Unlocking state Unlocking state Locking state / Power saving state Unlocking state Locking state / Power saving state Unlocking state H L L L ote: Phase error detection range = π to +π Pulses on DoIF/F signals are output to prevent dead zone. LD output becomes low when phase error is twu or more. LD output becomes high when phase error is twl or less and continues to be so for three cycles or more. twu and twl depend on OSCin input frequency as follows. twu > /fosc: i.e. twu >.ns when foscin =.8 MHz twl < 8/fosc: i.e. twl < 6.0ns when foscin =.8 MHz

13 MBF0L POWE SVIG MODE (ITEMITTET MODE COTOL CICUIT) Setting a PSIF(F) pin to Low, IF-PLL (F-PLL) enters into power saving mode resultant current consumption can be limited to 0µ (typ.). Setting PS pin to High, power saving mode is released so that the device works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up. Thus keeping the loop locked. PS pin must be set L at Power-O. llow µs after frequency stabilization on power-up for exiting the power saving mode (PS: L to H) Serial data can be entered during the power saving mode. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 0µ per one PLL section. t that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high impedance. VCO control voltage is naturally kept at the locking voltage which defined by a LPF s time constant. s a result of this, VCO s frequency is kept at the locking frequency. PSIF PSF IF-PLL counters F-PLL counters OSC input buffer L L OFF OFF OFF H L O OFF O L H OFF O O H H O O O O Vcc Clock Data LE PS () () () () PS = L (power saving mode) at Power-O ()Set serial data after power supply remains stable. ()elease saving mode(ps : L H) after setting serial data.

14 MBF0L TEST CICUIT (PESCLE IPUT/POGMMBLE EFEECE DIVIDE IPUT SESITIVITY TEST) fout Oscilloscope VccIF 0.µF 000pF 0Ω S.G S.G 000pF GD 0Ω MBF0L S.G Ω 000pF VccF Controller (divide ratio setting) 000pF 0.µF ote.:ssop-6 pin.

15 MBF0L TYPICL CHCTEISITICS. fin Input Sensitivity V fin F vs. fin F 0 Ta = + C 0 SPEC Vfin F (dbm) V CC =.7 V V CC =.0 V V CC =.6 V fin F (MHz) Vfin IF (dbm) SPEC V fin IF vs. fin IF fin IF (MHz) Ta = + C V CC =.7 V V CC =.0 V V CC =.6 V. OSCin Input Characteristics V fosc (dbm) SPEC V fosc vs. fosc Ta = + C V CC =.7 V V CC =.0 V V CC =.6 V fosc (MHz)

16 MBF0L. DoF Output Current I DOH vs. V DOH.000 V CC = V Ta = + C H level output voltage V DOH (V) H level output current I DOH (m ) I DOL vs. V DOL V CC = V Ta = + C L level output voltage V DOL (V) L level output current I DOL (m) 6

17 MBF0L. DoIF Output Current I DOH vs. V DOH.000 V CC = V Ta = + C H level output voltage V DOH (V) H level output current I DOH (m).00 I DOL vs. V DOL.000 V CC = V Ta = + C L level output voltagee V DOL (V) L level output current I DOL (m) 7

18 MBF0L. Input Impedance. fin F Input Inpedance characteristic F : : : : Ω.7 Ω 00 MHz 0.7 Ω Ω GHz 0.06 Ω.667 Ω. GHz.6 Ω 9.77 Ω.8 GHz STT MHz fin IF Input Inpedance characteristic STOP MHz : : 78.7 Ω 98.9 Ω 0 MHz 7. Ω 0. Ω 0 MHz IF : 87. Ω 77.9 Ω 00 MHz : 6.6 Ω 88.9 Ω 00 MHz STT MHz STOP MHz 8 (Continued)

19 MBF0L (Continued) OSC I Input Impedance characteristic : 7. kω. kω MHz : Ω 6.8 kω 0 MHz OSCI : : 6.8 Ω.9799 kω 0 MHz 78. Ω.7 kω 0 MHz STT MHz STOP MHz 9

20 MBF0L PPLICTIO EXMPLE Output VCO LPF from controller 000 pf V 0.mF 000 pf Clock Data LE finf VccF XfinF PSF DoF MBF0L GDF OSCI GDIF finif VccIF LD/fout PSIF DoIF 000 pf 000 pf V Lock Det. TCXO 0.µF Output VCO LPF Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation when open-circuited in the input). ote.:ssop-6 pin 0

21 MBF0L ODEIG IFOMTIO Part number Package emarks MBF0L PFV MBF0L PV 6pin, Plastic SSOP (FPT-6P-M0) 6pin, Plastic BCC (LCC-6P-M0)

22 MBF0L PCKGE DIMESIO 6 pins, Plastic SSOP (FPT-6P-M0) * : These dimensions do not include resin protrusion. *.00±0.0(.97±.00) (.00) IDEX *.0± ±0.0.0(.) (.7±.00) (.±.008) OM 0.6±0. (.06±.007) "" Details of "" part 0.0±0.0(.00±.00) (STD OFF).(.79)EF ±0.0 (.00±.008) C 99 FUJITSU LIMITED F60S-C- Dimensions in mm (inches) (Continued)

23 MBF0L (Continued) 6 pins, Plastic BCC (LCC-6P-M0) * : These dimensions do not include resin protrusion..±0.0 (.79±.00) (.0)MX (Mounting height) 9.0(.)TYP 0.6(.06)TYP 0.0±0.0 (.06±.00).0±0.0 (.6±.00).(.8) TYP "" "B".(.06)TYP E-MK 6 0.0(.06) 0.08±0.00 (.00±.00) (STD OFF) 0.80(.0) TYP 6 0.±0.0 (.0±.00).7(.068) TYP Details of "" part 0.7±0.0 (.00±.00) Details of "B" part 0.60±0.0 (.0±.00) 0.0(.00) 0.0±0.0 (.06±.00) 0.60±0.0 (.0±.00) C 996 FUJITSU LIMITED C60S-C- Dimensions in mm (inches)

24 MBF0L FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KWSKI PLT, --, Kamikodanaka akahara-ku, Kawasaki-shi Kanagawa -88, Japan Tel: (0) 7-7 Fax: (0) 7-9 orth and South merica FUJITSU MICOELECTOICS, IC. Semiconductor Division orth First Street San Jose, C 9-80, U.S.. Tel: (08) Fax: (08) -90/90 Europe FUJITSU MIKOELEKTOIK GmbH m Siebenstein Dreieich-Buchschlag Germany Tel: (060) Fax: (060) 690- sia Pacific FUJITSU MICOELECTOICS SI PTE. LIMITED #0-08, Lorong Chuan ew Tech Park Singapore 67 Tel: (6) Fax: (6) 8 00 ll ights eserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. lso, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CUTIO: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. ny semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F970 FUJITSU LIMITED Printed in Japan