Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler

Transcription

1 FUJITSU SEMICODUCTO DT SHEET DS0-1-1E SSP Single Serial Input PLL Frequency Synthesizer On-Chip.5 GHz Prescaler MB15E07 DESCIPTIO The Fujitsu MB15E07 is serial input Phase Locked Loop (PLL) frequency synthesizer with a.5 GHz prescaler. / or a 6/65 can be selected for the prescaler that enables pulse swallow operation. The latest BiCMOS process technology is used, resuitantly a supply current is limited as low as 8 m typ. This operates with a supply voltage of.0 V (typ.) Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. s a result of this, MB15E07 is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile Communications). FETUES High frequency operation:.5 GHz max (@ P= 6/65) 1.8 GHz max (@P = /) Low power supply voltage: VCC =.7 to.6 V Very Low power supply current : ICC = 8.0 m typ. (VCC = V) Power saving function : IPS = 0.1 µ typ. Pulse swallow function: / or 6/65 Serial input 1-bit programmable reference divider: = 5 to 16,8 Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 17 - Binary 11-bit programmable counter: 5 to,07 Wide operating temperature: Ta = 0 to 85 C Plastic 16-pin SSOP package (FPT-16P-M05) PCKGE 16-pin, Plastic SSOP (FPT-16P-M05)

2 PI SSIGMET (Top View) OSCin 1 16 φ OSCout 15 φp Vp 1 LD/fout V CC 1 ZC Do 5 1 PS GD 6 11 LE Xfin 7 10 Data fin 8 9 Clock

3 PI DESCIPTIOS Pin no. Pin name I/O Descriptions 1 OSCI I Programmable reference divider input. Oscillator input. Connection for an crystal or a TCXO. TCXO should be connected with a coupling capacitor. OSCOUT O Oscillator output. Connection for an external crystal. VP Power supply voltage input for the charge pump. VCC Power supply voltage input. 5 DO O Charge pump output. Phase of the charge pump can be reversed by FC bit. 6 GD Ground. 7 Xfin I Prescaler complementary input, and should be grounded via a capacitor. 8 fin I 9 Clock I 10 Data I 11 LE I 1 PS I 1 ZC I 1 LD/fout O Prescaler input. Connection with an external VCO should be done with C coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Control bit = H ;Data is transmitted to the programmable reference counter. Control bit = L ;Data is transmitted to the programmable counter. Load enable signal input (Open is prohibited.) When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. Power saving mode control. This pin must be set at L at Power-O. (Open is prohibited.) PS = H ; ormal mode PS = L ; Power saving mode Forced high-impedance control for the charge pump (with internal pull up resistor.) ZC = H ; ormal Do output. ZC = L ; Do becomes high impedance. Lock detect signal output(ld)/phase comparator monitoring output (fout). The output signal is selected by LDS bit in the serial data. LDS = H ; outputs fout (fr/fp monitoring output) LDS = L ; outputs LD ( H at locking, L at unlocking.) 15 φp O Phase comparator output for an external charge pump. ch open drain output. 16 φ O Phase comparator output for an external charge pump. CMOS output.

4 BLOCK DIGM OSCI 1 OSCOUT PS 1 LE 11 Data 10 Crystal Oscillator circuit Intermittent mode control (power save) 1-bit control latch LE Programmable reference divider Binary 1-bit reference counter 17-bit latch 1-bit latch C T SW -bit latch 19-bit shift register 19-bit shift register fr LDS FC fp fr fp LD Phase comparator Lock detector LD/fr/fp selector Charge pump 16 φ 15 φp 1 LD/fout 1 ZC VP Clock 9 Super charger 5 Do LE 7-bit latch 18-bit latch 11-bit latch SW Programmable divider XfI fi 7 8 GD 6 Prescaler /, 6/65 Binary 7-bit swallow counter Binary 11-bit programmable counter fp V CC MD Control Circuit

5 BSOLUTE MXIMUM TIGS Parameter Symbol ating Unit emark Power supply voltage VCC 0.5 to +.0 V VP VCC to +6.0 V Input voltage VI 0.5 to VCC +0.5 V Output voltage VO 0.5 to VCC +0.5 V Storage temperature Tstg 55 to +15 C ote: Permanent device damage may occur if the above bsolute Maximum atings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ECOMMEDED OPETIG CODITIOS Parameter Symbol Value Min. Typ. Max. Unit Power supply voltage VCC V VP VCC 6.0 V Input voltage VI GD VCC V Operating temperature Ta C emark Handling Precautions This device should be transported and stores in anti-static containers. This is a static-sensitive device; take proper anti-esd precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. lways turn the power supply off before inserting or removing the device from its socket. Protect leads with a conductive sheet when handling or transporting PC boards with devices. 5

6 ELECTICL CHCTEISTICS Parameter Symbol Condition (VCC =.7 to.6 V, Ta = 0 to +85 C) Value Unit Min. Typ. Max. Power supply current* 1 ICC fin = 1800 MHz, fosc = 1 MHz, P = / 8.0 m Power saving current Ips ZC = H or open µ Operating frequency fin P = / MHz P = 6/ MHz Crystal oscillator operating frequency fosc min. 500 mvp-p 0 MHz Input sensitivity fin Vfin 50 Ω system (efer to the test circuit.) 10 + dbm OSCin VOSC 500 VCC mvp-p Input voltage Data, Clock, LE, PS, ZC VIH Vcc 0.7 VIL Vcc 0. V Data, Clock, LE, PS IIH IIL µ Input current ZC IIH IIL Pull up input µ OSCin IIH IIL µ φp VOL Open drain output 0. V Output voltage φ, LD/fout VOH Vcc 0. VOL 0. V Do VDOH Vp 0. VDOL 0. V High impedance cutoff current Do IOFF 1.1 µ φp IOL Open drain output 1.0 m φ, LD/fout IOH 1.0 IOL 1.0 m Output current Do IDOH IDOL VCC =.0 V, Vp = 5 V, VDOH =.0 V, Ta = 5 C VCC =.0 V, Vp = 5 V, VDOL = 1.0 V, Ta = 5 C m *1: Conditions; VCC =.0 V, Ta = 5 C, in locking state. 6

7 FUCTIO DESCIPTIOS Pulse Swallow Function The divide ratio can be calculated using the following equation: fvco = [(P x ) + ] x fosc ( < ) fvco : Output frequency of external voltage controlled oscillator (VCO) : Preset divide ratio of binary 11-bit programmable counter (5 to,07) : Preset divide ratio of binary 7-bit swallow counter (0 17) fosc : Output frequency of the reference frequency oscillator : Preset divide ratio of binary 1-bit programmable reference counter (5 to 16,8) P : Preset divide ratio of modules prescaler ( or 6) Serial Data Input Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high, stored data is latched according to the control bit data as follows: Control bit (CT) H L Table.1 Control Bit Destination of serial data 17 bit latch (for the programmable reference divider) 18 bit latch (for the programmable divider) Shift egister Configuration Programmable eference Counter LSB Data Flow MSB C T SW FC LDS CT : Control bit 1 to 1 : Divide ratio setting bit for the programmable reference counter (5 to 16,8) SW : Divide ratio setting bit for the prescaler (/ or 6/65) FC : Phase control bit for the phase comparator LDS : LD/fout signal select bit ote : Start data input with MSB first [Table. 1] [Table. ] [Table. 5] [Table. 7] [Table. 6] 7

8 Programmable eference Counter LSB Data Flow MSB C T CT : Control bit 1 to 11 : Divide ratio setting bits for the programmable counter (5 to,07) 1 to 7 : Divide ratio setting bits for the swallow counter (0 to 17) ote : Start data input with MSB first [Table. 1] [Table. ] [Table. ] Divide ratio () Table. Binary 1-bit Programmable eference Counter Data Setting ote: Divide ratio less than 5 is prohibited. ote: Divide ratio less than 5 is prohibited. Divide ratio () range = 5 to, Divide ratio () Table. Binary 11-bit Programmable Counter Data Setting

9 Table. Binary 7-bit Swallow Counter Data Setting Divide ratio () ote: Divide ratio () range = 0 to 17 Table. 5 Prescaler Data Setting SW Prescaler Divide ratio H / L 6/65 Table. 6 LD/fout Output Select Data Setting LDS H L fout signal LD signal LD/fout output signal elation between the FC input and phase characteristics The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the phase comparator output (φ, φp) are reversed according to the FC bit. lso, the monitor pin (fout) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φ, and φp is shown below. Table. 7 FC Bit Data Setting (LDS = H ) FC = High FC = Low Do φ φp LD/fout Do φ φp LD/fout fr > fp H L L (fr) L H Z* (fp) fr < fp L H Z* (fr) H L L (fp) fr = fp Z* L Z* (fr) Z* L Z* (fp) * : High impedance 9

10 When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics. : When the LPF and VCO characteristics are similar to ➀, set FC bit high. : When the VCO characteristics are similar to ➁, set FC bit low. ➀ VCO Output Frequency PLL LPF VCO ➁ LPF Input Voltage Power Saving Mode (Intermittent Mode Control Circuit) Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to 10µ (max.). Setting PS pin to High, power saving mode is released so that the IC works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from the power saving mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up, thus keeping the loop locked. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 µ (max.). t that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high impedance. VCO control voltage is naturally kept at the locking voltage which defined by a LPF s time constant. s a result of this, VCO s frequency is kept at the locking frequency. ote: While the power saving mode is executed, ZC pin should be set at H or open. If ZC is set at L during power saving mode, approximately 10 µ current flows. PS pin must be set L at Power-O. The power saving mode can be released (PS : L H) 1µs later after power supply remains stable. During the power saving mode, it is possible to input the serial data. PS pin H L ZC pin H L Table.8 PS Pin Setting Status ormal mode Power saving mode Table.9 ZC Pin Setting Do output ormal output High impedance 10

11 SEIL DT IPUT TIMIG Data MSB LSB Clock LE t7 t1 t t t t5 t6 On rising edge of the clock, one bit of the data is transferred into the shift register. Parameter Min. Typ. Max. Unit Parameter Min. Typ. Max. Unit t1 0 ns t5 100 ns t 0 ns t6 0 ns t 0 ns t7 100 ns t 0 ns 11

12 PHSE COMPTO OUTPUT WVEFOM fr fp twu twl LD [ FC = H ] φp φ Do H Z L [ FC = L ] φp φ Do L Z H otes: 1. Phase error detection range:πto +π. Pulses on Do output signal during locked state are output to prevent dead zone.. LD output becomes low when phase is twu or more. LD. output becomes high when phase error is twl or less and continues to be so for three cysles or more.. twu and twl depend on OSCin input frequency. twu 8/fosc (e g.twu 65ns, foscin = 1.8 MHz) twl 16/fosc (e g.twl 150ns, foscin = 1.8 MHz) 5. LD becomes high during the power saving mode (PS = L.) 1

13 TEST CICUIT (for Measuring Input Sensitivity fin/oscin) V CC V P 0.1µF P.G 50Ω 1000pF 1000pF 0.1µF 1000pF 50Ω P.G Controller (setting devide ratio) V CC Oscilloscope 1

14 PPLICTIO EXMPLE LPF VCO Output 10kΩ 1kΩ To a lock detect. 1kΩ 10kΩ From φ φp LD/F OUT ZC PS LE Data Clock MB15E OSC I OSC OUT V P V CC D O GD Xf I f I C 1 X tal C 0.1 µ F 0.1 µ F 1000pF 1000pF C 1, C : Depend on the crystal parameters (Continued) 1

15 TYPICL CHCTEISTICS Do Output Current [Ta = + 5 C] [V CC = V, Vp = V, 5 V] [Ta = + 5 C] [V CC = V, Vp = V, 5 V] 5.0 Vp = V Vp = 5 V 5.0 Vp = V Vp = 5 V.0.0 V OH (V).0 V OL (V) I OH (m) I OL (m) fin Input Sensitivity Vfin vs. fin [Ta = +5 C] +10 Prescalar = 6/65 Main. counter div. ratio = 10 Swallow = O V CC = Vp Vfin (dbm) SPEC V CC =.7 V V CC =.0 V V CC =.6 V fin (MHz) (Continued) 15

16 (Continued) fin Input Snsitivity +10 [Ta = 5 C] Prescaler = / Main, counter div. ratio = 1860 Swallow = O 0 SPEC Vfin (dbm) : VDD =.7 V : VDD =.0 V : VDD =.6 V fin (MHz) OSCin Input Characteristics Vf OSC vs. f OSC [Ta = +5 C] +10 SPEC 0 ef. counter div. ratio = 767 fin, Xfin : OPE Vf OSC (dbm) V CC =.7 V V CC =.0 V V CC =.6 V f OSC (MHz) (Continued) 16

17 (Continued) fin Input Impedance fin : 9.1Ω kω.159 pf MHz 1 : Ω 6.666Ω 1 GHz : 10.71Ω 1.8Ω 1.5 GHz : 16.7Ω 1.5Ω GHz 1 OSCin Input Impedance : 00.1Ω -.89 kω.1 pf MHz OSCin 1 1 :.516Ω.99 kω 1 MHz : 150.5Ω.888 kω 10 MHz : 1.8Ω 98.7Ω 50 MHz 17

18 EFEECE IFOMTIO Test Circuit Diagram (PC pplication).65 V.65 V φ φ P LD fout ZC PS LE Data Clock Data interface board & PC Comparison freq ; 00 khz - div ratio ; 65 -Prescaler Div ; 6/65 -fol = 160 MHz -fom = 16 MHz -foh = 1679 MHz 1 MB15E k 7 k 7 k f OSC = 1 MHz Signal Generator HP86B Vsupply =.65 V OSCin OSCout Vp V CC D O 100 pf 51 cox µ + 10 µ 0.1 µ 0.1 µ 8 GD xfin fin 1 nf pf 7 k 1 n 1 k n (film cap) 10 p 18 C GD P Kv = MHz/V (MQE5-1619) C GD B -Spectrum nalyzer -Time Interval nalyzer µ cox. Output V VCO =.65 V + cox. 10 µ (Continued) 18

19 (Continued) PLL Lock Up toem = 0 µs (160 MHz 1679 MHz, within = 1kHz) PLL Phase loop band = 77.5 dbc/hz Mkr x : µs y : MHz EF 7.7 dbm 10 db/ TT 00 db MK 1.0 khz 5.7 db MHz.00 khz/div BW 00 khz VBW 00 khz KHz 5.17 µs µs SP 60.0 MHz CETE GHz PLL Lock Up toem = 00 µs (1679 MHz 160 MHz, within ±1 khz) PLL eference Leakage 00 MHz offset = 70.0 dbc Mkr x : µs y : MHz EF 7. dbm 10 db/ TT 00 db MK 00 khz 70 db MHz.00 khz/div BW 10 khz VBW 10 khz KHz µs µs SP 1.00 MHz CETE GHz 19

20 ODEIG IFOMTIO Part number Package emarks MB15E07PFV1 16-pin Plastic SSOP (FPT-16P-M05) 0

21 PCKGE DIMESIO 16 pins, Plastic SSOP (FPT-16P-M05) * : These dimensions do not include resin protrusion. * 5.00±0.10(.197±.00) (.00) IDEX *.0± ± (.1) (.17±.00) (.5±.008) OM 0.65±0.1 (.056±.007) "" Details of "" part 0.10±0.10(.00±.00) (STD OFF).55(.179)EF ±0.0 (.00±.008) C 199 FUJITSU LIMITED F1601S-C- Dimensions in mm (inches) 1

22 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KWSKI PLT, -1-1, Kamikodanaka akahara-ku, Kawasaki-shi Kanagawa 11-88, Japan Tel: (0) Fax: (0) 75-9 orth and South merica FUJITSU MICOELECTOICS, IC. Semiconductor Division 55 orth First Street San Jose, C , U.S.. Tel: (08) Fax: (08) -90/905 Europe FUJITSU MIKOELEKTOIK GmbH m Siebenstein Dreieich-Buchschlag Germany Tel: (0610) Fax: (0610) sia Pacific FUJITSU MICOELECTOICS SI PTE. LIMITED #05-08, 151 Lorong Chuan ew Tech Park Singapore Tel: (65) Fax: (65) ll ights eserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. lso, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CUTIO: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. ny semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F970 FUJITSU LIMITED Printed in Japan