2.6GHz Bidirectional I 2 C BUS Controlled Synthesiser

Transcription

1 SP555.6GHz Bidirectional I C BUS Controlled Synthesiser The SP555 is a single chip frequency synthesiser designed for T tuning systems. Control data is entered in the standard I C BUS format. The device contains 4 addressable current limited outputs and 4 addressable Bi-Directional open collector ports one of which is a 3 bit DC. The information on these ports can be read via the I C BUS. The device has one fixed I C BUS address and 3 programmable addresses, programmed by applying a specific input voltage to one of the current limited outputs. This enables or more synthesisers to be used in a system. DS36 ISSUE 4.5 November Ordering Information SP555GS/KG/MPS (Tubes) SP555GS/KG/MPD (Tape & Reel) 6lead minature plastic package FETURES Complete.6GHz Single Chip System Programmable via I C BUS Low power consumption (5 65m) Low Radiation Phase Lock Detector aractor Drive mp Disable 6 Controllable Outputs, 4 Bi-Directional 5 Level DC ariable I C BUS ddress For Multi Tuner pplications Full ESD Protection* CHRGE PUMP CRYSTL Q CRYSTL Q SD SCL I/O PORT P * I/O PORT P6 I/O PORT P5 * Normal ESD handling procedures should be observed. PPLICTIONS Satellite T High IF Cable Tuning Systems 8 SP 555S 6 9 = Logic level I/O * = 3-bit DC input DRIE OUTPUT EE RF INPUT RF INPUT CC P OUTPUT PORT PORT P3/DD SELECT I/O PORT P4 Fig. Pin connections top view MP6

2 SP555 ELECTRICL CHRCTERISTICS T amb = - C to +8 C, CC = +4. to 5.3. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Reference frequency = 4MHz unless otherwise stated. Characteristic Pin Min. alue Typ. Max. Units Conditions Supply current Prescaler input voltage Prescaler input voltage 3, 4 3, m m RMS m RMS CC = 5 5MHz to.6ghz Sinewave MHz, see Fig. 5 Prescaler input impedance Prescaler input capacitance 3, 4 5 Ω pf SD, SCL Input high voltage Input low voltage Input high current Input low current Leakage current Input voltage = CC Input voltage = When CC = SD Output voltage 4.4 I sink = 3m Charge pump current low Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance ±5 ± 64 8 ±5 n Ω mp-p Ω Byte 4, bit =, pin = Byte 4, bit =, pin = Byte 4, bit 4 =, pin = pin 6 = Output Ports P, P3 sink current P, P3 leakage current P4-P sink current P4-P leakage current,, m m OUT = OUT = 3 OUT =. OUT = 3 Input Ports P3 input current high P3 input current low P4,P5,P input voltage low P4,P5,P input voltage high P6 input current high P6 input current low 9,8,6 9,8, pin = 3. pin = See Table 3 for DC Levels

3 SP555 RF IN RF IN SCL SD PRE MP DDRESS SELECT POWER ON DETECTOR I C BUS TRNSCEIER 3 BIT DC PRESCLER 46 3 TTL LEEL COMP 5 BIT PROGRMMBLE DIIDER 5 BIT LTCH DIIDER RTIO 6 BIT LTCH PORT INFORMTION F div PHSE F comp COMP DIIDER F 45 LOCK DET GTE CHRGE PUMP CONTROL DT LTCH T CP LOGIC OS OSC 4MHz 3 6 Q CRYSTL Q CHRGE PUMP DRIE/ RICP OUT CC P P3 P4 P5 P6 P Fig. Block diagram 5 EE FUNCTIONL DESCRIPTION The SP555 is programmed from an I C BUS. Data and Clock are fed in on the SD and SCL lines respectively as defined by the I C BUS format. The synthesiser can either accept new data (write mode) or send data (read mode). The Tables in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I C Bus system. Table 4 shows how the address is selected by applying a voltage to P3. The last bit of the address byte (R/W) sets the device into read mode if it is high and write mode if it is low. When the SP555 receives a correct address byte it pulls the SD line low during the acknowledge period and during following acknowledge periods after further data bytes are programmed. When the SP555 is programmed into the read mode the controlling device accepting the data must pull down the SD line during the following acknowledge period to read another status byte. WRITE MODE (FREQUENCY SYNTHESIS) When the device is in the write mode Bytes + 3 select the synthesised frequency while bytes select the output port states and charge pump information. Once the correct address is received and acknowledged, the first Bit of the next Byte determines whether that byte is interpreted as byte or 4, a logic for frequency information and a logic for charge pump and output port information. dditional data bytes can be entered without the need to re-address the device until an I C stop condition is recognised. This allows a smooth frequency sweep for fine tuning or FC purposes. If the transmission of data is stopped mid-byte (i.e., by another device on the bus) then the previously programmed byte is maintained. Frequency data from bytes and 3 is stored in a 5-bit shift register and is used to control the division ratio of the 5- bit programmable divider which is preceded by a divide-by- 6 prescaler and amplifier to give excellent sensitivity at the local oscillator input; see Fig 5. The input impedance is shown in Fig. The programmed frequency can be calculated by multiplying the programmed division ratio by 6 times the comparison frequency F comp. When frequency data is entered, the phase comparator, via the charge pump and varactor drive amplifier, adjusts the local oscillator control voltage until the output of the programmable divider is frequency and phase locked to the comparison frequency. The reference frequency may be generated by an external source capacitively coupled into pin or provided by an onboard 4MHz crystal controlled oscillator. Note that the comparison frequency is 85kHz when a 4MHz reference is used. Bit of byte 4 of the programming data (CP) controls the current in the charge pump circuit, a logic for ± and a logic for ±5, allowing compensation for the variable tuning slope of the tuner and also to enable fast channel changes over the full band. Bit 4 of byte 4 (T) disables the charge pump if set to a logic. Bit 8 of byte 4 (OS) switches the charge pump drive amplifier s output off when it is set to a logic. Bit 3 of Byte 4 (T) selects a test mode where the phase comparator inputs are available on P6 and P, a logic connects F comp to P6 and F div to P. Byte 5 programs the output ports P to P; on a logic for a high impedance output, logic for low impedance (on). RED MODE When the device is in the read mode the status data read from the device on the SD line takes the form shown in Table. Bit (POR) is the power-on reset indicator and is set to a logic if the power supply to the device has dropped below 3 and the programmed information lost (e.g., when the device is initially turned on). The POR is set to when the read sequence is terminated by a stop command. The outputs are all set to high impedance when the device is initially powered up. Bit (FL) indicates whether the device is phase locked, a logic is present if the device is locked and a logic if the device is unlocked. 3

4 SP555 Bits 3, 4 and 5 (I,I,I) show the status of the I/O Ports P, P5 and P4 respectively. logic indicates a low level and a logic a high level. If the ports are to be used as inputs they should be programmed to a high impedance state (logic ). These inputs will then respond to data complying with TTL type voltage levels. Bits 6, and 8 (,,) combine to give the output of the 5 level DC. The 5 level DC can be used to feed FC information to the microprocessor from the IF section of the receiver, as illustrated in the typical application circuit. PPLICTION typical pplication is shown in Fig. 4. ll input/output interface circuits are shown in Fig. 6. MSB LSB ddress M M Byte Programmable divider Byte Programmable divider Byte 3 Charge pump and test bits CP T T OS Byte 4 I/O port control bits P P6 P5 P4 P3 X X P Byte 5 Table Write data format (MSB transmitted first) ddress M M Byte Status byte POR FL I I I Byte Table Read data format (MSB is transmitted first) : cknowledge bit M, M : ariable address bits (see Table 4) CP : Charge Pump current select T : Test mode selection T : Charge pump disable OS : aractor drive Output disable Switch P, P6, P5, P4, : Control output states P3, P POR : Power On Reset indicator FL : Phase lock detect flag I, I, I : Digital information from Ports P, P5 and P4, respectively,, : 5 Level DC data from P6 (see Table 3) X : Don't care oltage input to P6.6 CC to CC to 6 CC 3 CC to 45 CC 5 CC to 3 CC to.5 CC Table 3 DC levels M M oltage input to P3 to CC lways valid 3 CC to CC 8 CC -3. Table 4 ddress selection Fig. 3 Data formats 4

5 SP555 PPLICTION typical application is shown in Fig. 4. ll input/output interface circuits are shown in Fig IF SIGNL IF SECTION FC OUTPUT P4 +3 STELLITE TUNER OSCILLTOR OUTPUT RICP INPUT k T P3 P.µ n n SP 555S n k 8n P5 P6 P 8p I C BUS 4MHz CRYSTL SCL SD CONTROL MICRO N394 Fig. 4 Typical application 3 IN (m RMS INTO 5 Ω) 5 OPERTING WINDOW FREQUENCY (MHz) Fig. 5 Typical input sensitivity 5

6 SP555 REF CC 5 5 CHRGE PUMP RF INPUTS DRIE OUTPUT RF input Loop amplifier CC CC PORT SCL/SD * CK 3k * ON SD ONLY Ports P-P4 SCL and SD inputs CC CC PORT P3 ONLY PORT CRYSTL Q K CRYSTL Q Reference oscillator Ports P and P3 Fig. 6 SP555 Input/output interface circuits 6

7 SP555 Fig. Typical input impedance BSOLUTE MXIMUM RTINGS ll voltages are referred to EE and pin 3 at Parameter Pin Min. alue Max. Units Conditions Supply voltage -.3 RF input voltage 3, 4.5 p-p Port voltage 6-6-9, Port in off state Port in on state Port in on state Total port output current 6-5 m RF input DC offset 3, CC +.3 Charge pump DC offset -.3 CC +.3 Drive DC offset CC +.3 Crystal oscillator DC offset -.3 CC +.3 SD, SCL input voltage Storage temperature CC C With CC applied CC not applied Junction temperature +5 C MP 6 Thermal resistance, chip-to-ambient MP 6 Thermal resistance, chip-to-case 4 C/W C/W Power consumption at mw ll ports off

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