ZL Features. Description

Transcription

1 Features February 27 Zarlink ST-BUS compatible 8-line x 32-channel inputs 8-line x 32-channel outputs 256 ports non-blocking switch Single power supply (+5 V) Low power consumption: 3 mw Typ. Microprocessor-control interface Three-state serial outputs Ordering Information ZL5DE 4 Pin Plastic DIP ZL5DP 44 Pin PLCC ZL5DE 4 Pin Plastic DIP ZL5DP 44 Pin PLCC Pb Free Matte Tin -4 C +85 C Description This VLSI ISO-CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up kbit/s channels. Each of the eight serial inputs and outputs consist of kbit/s channels multiplexed form a 248 kbit/s ST-BUS stream. In addition, the ZL5 provides microprocessor read and write access individual ST-BUS channels. C4i Fi V DD V SS ODE STi STi STi2 STi3 STi4 STi5 STi6 STi7 Serial Parallel Converter Data Memory Frame Counter Control Register Control Interface Output MUX Connection Memory Parallel Serial Converter STo STo STo2 STo3 STo4 STo5 STo6 STo7 DS CS R/W A5/ A DTA D7/ D CSTo Figure - Functional Block Diagram Zarlink Semiconducr Inc. Zarlink, ZL and the Zarlink Semiconducr logo are trademarks of Zarlink Semiconducr Inc. Copyright 2-27, Zarlink Semiconducr Inc. All Rights Reserved.

2 STi3 STi4 STi5 STi6 STi7 VDD Fi C4i A A A2 NC STi2 STi STi DTA CSTo ODE STo STo STo2 NC NC A3 A4 A5 DS R/W CS D7 D6 D5 NC STo3 STo4 STo5 STo6 STo7 VSS D D D2 D3 D4 DTA STi STi STi2 STi3 STi4 STi5 STi6 STi7 VDD Fi C4i A A A2 A3 A4 A5 DS R/W CSTo ODE STo STo STo2 STo3 STo4 STo5 STo6 STo7 VSS D D D2 D3 D4 D5 D6 D7 CS 44 PIN PLCC 4 PIN PLASTIC DIP Figure 2 - Pin Connections 4 DIP Pin # 44 PLCC Name Description 2 DTA Data Acknowledgement (Open Drain Output). This is the data acknowledgement on the microprocessor interface. This pin is pulled low signal that the chip has processed the data. A 99 Ω, /4W, resisr is recommended be used as a pullup STi- STi STi3- STi7 ST-BUS Input 2 (Inputs). These are the inputs for the 248 kbit/s ST-BUS input streams. ST-BUS Input 3 7 (Inputs). These are the inputs for the 248 kbit/s ST-BUS input streams. 2 V DD Power Input. Positive Supply. 3 Fi Framing -Type (Input). This is the input for the frame synchronization pulse for the 248 kbit/s ST-BUS streams. A low on this input causes the internal counter reset on the next negative transition of C4i. 2 4 C4i 4.96 MHz Clock (Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this clock A-A2 Address 2 (Inputs). These are the inputs for the address lines on the microprocessor interface. A3-A5 Address 3 5 (Inputs). These are the inputs for the address lines on the microprocessor interface DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface R/W Read or Write (Input). This is the input for the read/write signal on the microprocessor interface - high for read, low for write CS Chip Select (Input). This is the input for the active low chip select on the microprocessor interface D7-D5 Data 7 5 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor interface. 2

3 4 DIP Pin # 44 PLCC Name Description D4-D Data 4 (Three-state I/O Pins). These are the bidirectional data pins on the microprocessor interface V SS Power Input. Negative Supply (Ground) STo7- STo3 STo2- STo ST-BUS Output 7 3 (Three-state Outputs). These are the pins for the eight 248 kbit/s ST-BUS output streams. ST-BUS Output 2 (Three-state Outputs). These are the pins for the eight 248 kbit/s ST-BUS output streams ODE Output Drive Enable (Input). If this input is held high, the STo-STo7 output drivers function normally. If this input is low, the STo-STo7 output drivers go in their high impedance state. NB: Even when ODE is high, channels on the STo-STo7 outputs can go high impedance under software control. 4 CSTo Control ST-BUS Output (Complementary Output). Each frame of 256 bits on this ST-BUS output contains the values of bit in the 256 locations of the Connection Memory High. 6, 8, 28, 4 NC No Connection. 3

4 Functional Description In recent years, there has been a trend in telephony wards digital switching, particularly in association with software control. Simultaneously, there has been a trend in system architectures wards distributed processing or multi-processor systems. In accordance with these trends, ZARLINK has devised the ST-BUS (Serial Telecom Bus). This bus architecture can be used both in software-controlled digital voice and data switching, and for interprocessor communications. The uses in switching and in interprocessor communications are completely integrated allow for a simple general purpose architecture appropriate for the systems of the future. The serial streams of the ST-BUS operate continuously at 248 kbit/s and are arranged in 25 µs wide frames which contain 32 8-bit channels. ZARLINK manufactures a number of devices which interface the ST-BUS; a key device being the ZL5 chip. The ZL5 can switch data from channels on ST- BUS inputs channels on ST-BUS outputs, and simultaneously allows its controlling microprocessor read channels on ST-BUS inputs or write channels on ST-BUS outputs (Message Mode). To the microprocessor, the ZL5 looks like a memory peripheral. The microprocessor can write the ZL5 establish switched connections between input ST-BUS channels and output ST-BUS channels, or transmit messages on output ST- BUS channels. By reading from the ZL5, the microprocessor can receive messages from ST-BUS input channels or check which switched connections have already been established. By integrating both switching and interprocessor communications, the ZL5 allows systems use distributed processing and switch voice or data in an ST-BUS architecture. Hardware Description Serial data at 248 kbit/s is received at the eight ST- BUS inputs (STi STi7), and serial data is transmitted at the eight ST-BUS outputs (STo STo7). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g., ZARLINK s MT8964). This serial input word is converted in parallel data and sred in the 256 X 8 Data Memory. Locations in the Data Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read by the microprocessor which controls the chip. Locations in the Connection Memory, which is split in high and low parts, are associated with particular ST-BUS output streams. When a channel is due be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input, then the contents of the Connection Memory Low location associated with the output channel is used address the Data Memory. This Data Memory address corresponds the channel on the input ST-BUS stream on which the data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the contents of the Connection Memory Low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes. The Connection Memory data is received, via the Control Interface, at D7 D. The Control Interface also receives address information at A5 A and handles the microprocessor control signals CS, DTA, R/W and DS. There are two parts any address in the Data Memory or Connection Memory. A5 A4 A3 A2 A A HEX ADDRESS LOCATION X X X X X - F 2 2 3F Control Register Channel Channel Channel 3 Writing the Control Register is the only fast transaction. Memory and stream are specified by the contents of the Control Register. Figure 3 - Address Memory Map 4

5 The higher order bits come from the Control Register, which may be written or read from via the Control Interface. The lower order bits come from the address lines directly. The Control Register also allows the chip broadcast messages on all ST-BUS outputs (i.e., put every channel in Message Mode), or split the memory so that reads are from the Data Memory and writes are the Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels go in a high-impedance state, which enables arrays of ZL5s be constructed. It also controls the CSTo pin. All ST-BUS timing is derived from the two signals C4i and Fi. Software Control The address lines on the Control Interface give access the Control Register directly or, depending on the contents of the Control Register, the High or Low sections of the Connection Memory or the Data Memory. If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If A5 is high, then the address lines A4-A select the memory location corresponding channel -3 for the memory and stream selected in the Control Register. The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory be chosen, and the stream address bits define one of the ST-BUS input or output streams. Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are the Connection Memory Low. The other mode control bit, bit 6, puts every output channel on every output stream in active Message Mode; i.e., the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the ODE pin is low. In this mode the chip behaves as if bits 2 and of every Connection Memory High location were, regardless of the actual values. Mode Control Bits (unused) Memory Select Bits Stream Address Bits BIT NAME DESCRIPTION 7 6 Split Memory Message Mode 5 (unused) Memory Select Bits Stream Address Bits When, all subsequent reads are from the Data Memory and writes are the Connection Memory Low, except when the Control Register is accessed again. When, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. When, the contents of the Connection Memory Low are output on the Serial Output streams except when the ODE pin is low. When, the Connection Memory bits for each channel determine what is output. - - Not be used - - Data Memory (read only from the microprocessor port) - - Connection Memory Low - - Connection Memory High The number expressed in binary notation on these bits refers the input or output ST-BUS stream which corresponds the subsection of memory made accessible for subsequent operations. Figure 4 - Control Register Bits 5

6 No Corresponding Memory - These bits give s if read. Per Channel Control Bits BIT NAME DESCRIPTION 2 Message Channel When, the contents of the corresponding location in Connection Memory Low are output on the location s channel and stream. When, the contents of the corresponding location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection the location s channel and stream. CSTo Bit This bit is output on the CSTo pin one channel early. The CSTo bit for stream is output first. Output Enable If the ODE pin is high and bit 6 of the Control Register is, then this bit enables the output driver for the location s channel and stream. This allows individual channels on individual streams be made high-impedance, allowing switching matrices be constructed. A enables the driver and a disables it. Figure 5 - Connection Memory High Bits Stream Address Bits Channel Address Bits BIT NAME DESCRIPTION 7-5 Stream Address Bits 4- Channel Address Bits The number expressed in binary notation on these 3 bits is the number of the ST-BUS stream for the source of the connection. Bit 7 is the most significant bit. e.g., if bit 7 is, bit 6 is and bit 5 is, then the source of the connection is a channel on STi4. The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (The ST-BUS stream where the channel lies is defined by bits 7, 6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is, bit 3 is, bit 2 is, bit is and bit is, then the source of the connection is channel 9. If bit 2 of the corresponding Connection High location is or if bit 6 of the Control Register is, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated define the source of the connection which is output on the channel and stream associated with this location. Figure 6 - Connection Memory Low Bits 6

7 If bit 6 of the Control Register is, then bits 2 and of each Connection Memory High location function normally (see Fig. 5). If bit 2 is, the associated ST- BUS output channel is in Message Mode; i.e., the byte in the corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the ST-BUS input stream and channel where the byte is be found (see Fig. 6). Bit of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS streams, and the bit for stream is output first in the channel; e.g., bit s for channel 9 of streams -7 are output synchronously with ST-BUS channel 8 bits 7-. If the ODE pin is low, then all serial outputs are highimpedance. If it is high and bit 6 in the Control Register is, then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is, then the bit in the Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output stream and channel. Bit = enables the driver and bit = disables it (see Fig. 5). 7

8 Absolute Maximum Ratings Parameter Symbol Min Max Units V DD - V SS V 2 Voltage on Digital Inputs V I V SS -.3 V DD +.3 V 3 Voltage on Digital Outputs V O V SS -.3 V DD +.3 V 4 Current at Digital Outputs I O 4 ma 5 Srage Temperature T S C 6 Package Power Dissipation P D 2 W Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect ground (V SS ) unless otherwise stated.. Characteristics Sym Min Typ Max Units Test Conditions Operating Temperature T OP C 2 Positive Supply V DD V 3 Input Voltage V I V DD V Typical figures are at 25 C and are for design aid only: not guaranteed and not subject production testing. DC Electrical Characteristics - Voltages are with respect ground (V SS ) unless otherwise stated. Characteristics Sym Min Typ I Supply Current I DD 6 ma Outputs unloaded 2 N Input High Voltage V IH 2. V 3 P U Input Low Voltage V IL.8 V 4 T Input Leakage I IL 5 µa V I between V SS and V DD 5 S Input Pin Capacitance C I 8 pf 6 Output High Voltage V OH 2.4 V I OH = ma O 7 U Output High Current I OH 5 ma Sourcing. V OH =2.4V 8 T Output Low Voltage V OL.4 V I OL = 5 ma P 9 U Output Low Current I OL ma Sinking. V OL =.4V T High Impedance Leakage I OZ 5 µa V O between V SS and V DD S Output Pin Capacitance C O 8 pf Typical figures are at 25 C and are for design aid only: not guaranteed and not subject production testing. Test Point V DD S is open circuit except when testing output levels or high impedance states. Output Pin S R L S2 S2 is switched V DD or V SS when testing output levels or high impedance states. C L V SS V SS Figure 7 - Output Test Load 8

9 AC Electrical Characteristics - Clock Timing (Figures 8 and 9) Characteristics Sym Min Typ Max Units Test Conditions Clock Period t CLK ns 2 I Clock Width High t CH ns 3 N Clock Width Low t CL 22 5 ns 4 P U Clock Transition Time t CTT 2 ns 5 T Frame Pulse Setup Time t FPS 2 ns 6 S Frame Pulse Hold Time t FPH 2 ns 7 Frame Pulse Width t FPW 244 ns Timing is over recommended temperature & power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject production testing. Contents of Connection Memory are not lost if the clock sps, however, ST-BUS outputs go in the high impedance state. NB: Frame Pulse is repeated every 52 cycles of C4i. C4i Fi BIT CELLS Channel 3 Bit o Channel Bit 7 Figure 8 - Frame Alignment t CLK t CL t CTT t CH C4i.8V t CHL t CTT t FPH t FPS t FPH t FPS Fi.8V t FPW Figure 9 - Clock Timing 9

10 AC Electrical Characteristics - Serial Streams (Figures 7,, and 2) Characteristics Sym Min Typ Max Units Test Conditions STo/7 Delay - Active High Z t SAZ 5 ns R L = KΩ, C L =5 pf 2 O STo/7 Delay - High Z Active t SZA 6 ns C L =5 pf 3 U T STo/7 Delay - Active Active t SAA 65 ns C L =5 pf 4 P STo/7 Hold Time t SOH 45 ns C L =5 pf 5 U T Output Driver Enable Delay t OED 45 ns R L = KΩ, C L =5 pf 6 S External Control Hold Time t XCH 5 ns C L =5 pf 7 External Control Delay t XCD 75 ns C L =5 pf 8 I Serial Input Setup Time t SIS -4 ns 9 N Serial Input Hold Time t SIH 4 ns Timing is over recommended temperature & power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject production testing. High Impedance is measured by pulling the appropriate rail with R L, with timing corrected cancel time taken discharge C L. C4i.8V Bit Cell Boundary ODE.8V STo STo7 2.4V.4V t SOH STo STo7 2.4V.4V t OED t OED t SAZ Figure - Output Driver Enable STo 2.4V STo7.4V Bit Cell Boundaries t SZA C4i.8V STo STo7 2.4V.4V t SOH STi STi7.8V t SIH t SAA t SIS CSTo 2.4V.4V t XCH Figure 2 - Serial Inputs t XCD Figure - Serial Outputs and External Control

11 AC Electrical Characteristics - Processor Bus (Figures 7 and 3) Characteristics Sym Min Typ Max Units Test Conditions Chip Select Setup Time t CSS 2 ns 2 Read/Write Setup Time t RWS 25 5 ns 3 Address Setup Time t ADS 25 5 ns 4 Acknowledgement Delay Fast t AKD 4 ns C L =5 pf Slow t AKD cycles C4i cycles 5 Fast Write Data Setup Time t FWS 2 ns 6 Slow Write Data Delay t SWD 2..7 cycles C4i cycles 7 Read Data Setup Time t RDS.5 cycles C4i cycles, C L = 5 pf 8 Data Hold Time Read t DHT 2 ns R L = KΩ, C L =5 pf Write t DHT 2 ns 9 Read Data To High Impedance t RDZ 5 9 ns R L = KΩ, C L =5 pf Chip Select Hold Time t CSH ns Read/Write Hold Time t RWH ns 2 Address Hold Time t ADH ns 3 Acknowledgement Hold Time t AKH 6 8 ns R L = KΩ, C L =5 pf Timing is over recommended temperature & power supply voltages. Typical figures are at 25 C and are for design aid only: not guaranteed and not subject production testing. High Impedance is measured by pulling the appropriate rail with R L, with timing corrected cancel time taken discharge C L. Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period. DS CS.8V t CSS t CSH R/W.8V t RWS t RWH A5 A.8V t ADS t AKD t ADH DTA 2.4V.4V t AKH t RDS t DHT D7 D 2.4V (Read) (Write).8V (Read.8V (Write) t SWD t FWS t RDZ Figure 3 - Processor Bus

12 Package Outlines F A G D D D 2 E H E e: (lead coplanarity) I E 2 A Notes: ) Not scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) For D & E add for allowable Mold Protrusion." Dim 2-Pin 28-Pin 44-Pin 68-Pin 84-Pin Min Max Min Max Min Max Min Max Min Max A.65 (4.2).8 (4.57).65 (4.2).8 (4.57).65 (4.2).8 (4.57).65 (4.2).2 (5.8).65 (4.2).2 (5.8) A.9 (2.29).2 (3.4).9 (2.29).2 (3.4).9 (2.29).2 (3.4).9 (2.29).3 (3.3).9 (2.29).3 (3.3) D/E.385 (9.78) D /E.35 (8.89) D 2 /E 2.29 (7.37).395 (.3).356 (9.42).33 (8.38).485 (2.32).45 (.43).39 (9.9).495 (2.57).456 (.582).43 (.92).685 (7.4).65 (6.5).59 (4.99).695 (7.65).656 (6.662).63 (6.).985 (25.2).95 (24.3).89 (22.6).995 (25.27).958 (24.333).93 (23.62).85 (3.).5 (29.2).9 (27.69).95 (3.35).58 (29.43).3 (28.7) e F.26 (.66).32 (.82).26 (.66).32 (.82).26 (.66).32 (.82).26 (.66).32 (.82).26 (.66).32 (.82) G.3 (.33).2 (.533).3 (.33).2 (.533).3 (.33).2 (.533).3 (.33).2 (.533).3 (.33).2 (.533) H.5 BSC (.27 BSC).5 BSC (.27 BSC).5 BSC (.27 BSC).5 BSC (.27 BSC).5 BSC (.27 BSC) I.2 (.5).2 (.5).2 (.5).2 (.5).2 (.5) Plastic J-Lead Chip Carrier - P-Suffix 2

13 3 2 E E n-2 n- n D A 2 A L C b 2 e e A e B e C Notes: D ) Not scale 2) Dimensions in inches 3) (Dimensions in millimeters) b Plastic Dual-In-Line Packages (PDIP) - E Suffix 8-Pin 6-Pin 8-Pin 2-Pin DIM Plastic Plastic Plastic Plastic Min Max Min Max Min Max Min Max A.2 (5.33).2 (5.33).2 (5.33).2 (5.33) A 2.5 (2.92).95 (4.95).5 (2.92).95 (4.95).5 (2.92).95 (4.95).5 (2.92).95 (4.95) b.4 (.356).22 (.558).4 (.356).22 (.558).4 (.356).22 (.558).4 (.356).22 (.558) b 2.45 (.4).7 (.77).45 (.4).7 (.77).45 (.4).7 (.77).45 (.4).7 (.77) C.8 (.23).4 (.356).8 (.23).4(.356).8 (.23).4 (.356).8 (.23).4 (.356) D.355 (9.2).4 (.6).78 (9.8).8 (2.32).88 (22.35).92 (23.37).98 (24.89).6 (26.9) D.5 (.3).5 (.3).5 (.3).5 (.3) E.3 (7.62).325 (8.26).3 (7.62).325 (8.26).3 (7.62).325 (8.26).3 (7.62).325 (8.26) E.24 (6.).28 (7.).24 (6.).28 (7.).24 (6.).28 (7.).24 (6.).28 (7.) e. BSC (2.54). BSC (2.54). BSC (2.54). BSC (2.54) e A.3 BSC (7.62).3 BSC (7.62).3 BSC (7.62).3 BSC (7.62) L.5 (2.92).5 (3.8).5 (2.92).5 (3.8).5 (2.92).5 (3.8).5 (2.92).5 (3.8) e B.43 (.92).43 (.92).43 (.92).43 (.92) e C.6 (.52).6 (.52).6 (.52).6 (.52) NOTE: Controlling dimensions in parenthesis ( ) are in millimeters. 3

14 3 2 E E n-2 n- n D A 2 A α L C b 2 e e A e B Notes: D ) Not scale 2) Dimensions in inches 3) (Dimensions in millimeters) b Plastic Dual-In-Line Packages (PDIP) - E Suffix 22-Pin 24-Pin 28-Pin 4-Pin DIM Plastic Plastic Plastic Plastic Min Max Min Max Min Max Min Max A.2 (5.33).25 (6.35).25 (6.35).25 (6.35) A 2.25 (3.8).95 (4.95).25 (3.8).95 (4.95).25 (3.8).95 (4.95).25 (3.8).95 (4.95) b.4 (.356).22 (.558).4 (.356).22 (.558).4 (.356).22 (.558).4 (.356).22 (.558) b 2.45 (.5).7 (.77).3 (.77).7 (.77).3 (.77).7 (.77).3 (.77).7 (.77) C.8 (.24).5 (.38).8 (.24).5 (.38).8 (.24).5 (.38).8 (.24).5 (.38) D.5 (26.67).2 (28.44).5 (29.3).29 (32.7).38 (35.).565 (39.7).98 (5.3) 2.95 (53.2) D.5 (.3).5 (.3).5 (.3).5 (.3) E.39 (9.9).43 (.92).6 (5.24).67 (7.2).6 (5.24).67 (7.2).6 (5.24).67 (7.2) E.29 (7.37).33 (8.38) E.33 (8.39).38 (9.65).485 (2.32).58 (4.73).485 (2.32).58 (4.73).485 (2.32).58 (4.73) E.246 (6.25).254 (6.45) e. BSC (2.54). BSC (2.54). BSC (2.54). BSC (2.54) e A.4 BSC (.6).6 BSC (5.24).6 BSC (5.24).6 BSC (5.24) e A.3 BSC (7.62) e B.43 (.92) L.5 (2.93).6 (4.6).5 (2.93).2 (5.8).5 (2.93).2 (5.8).5 (2.93).2 (5.8) α Shaded areas for 3 Mil Body Width 24 PDIP only 4

15 For more information about all Zarlink products visit our Web Site at Information relating products and services furnished herein by Zarlink Semiconducr Inc. or its subsidiaries (collectively Zarlink ) is believed be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor be regarded as a representation relating the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfacry in a specific piece of equipment. It is the user s responsibility fully determine the performance and suitability of any equipment using such information and ensure that any publication or data used is up date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure perform may result in significant injury or death the user. All products and materials are sold and services provided subject Zarlink s conditions of sale which are available on request. Purchase of Zarlink s I 2 C components conveys a licence under the Philips I 2 C Patent rights use these components in and I 2 C System, provided that the system conforms the I 2 C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconducr logo are trademarks of Zarlink Semiconducr Inc. Copyright Zarlink Semiconducr Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE