2.9 GHz PLL for SAT TV Tuner with UNi-Bus. 14 bit Shift Reg. 15 bit Latch LOCK. SET 15/14 bit counter. Phase detector

Transcription

1 PLL for SAT TV Tuner with UNi-Bus Description The U6239B is a single-chip frequency synthesizer with bidirectional I 2 C bus control and unidirectional 3-wire bus control, developed for SAT TV-tuner and cable tuner applications. Features divide-by-6 prescaler integrated UNi-BUS: I 2 C bus and 3-wire bus I 2 C bus software compatible to U6223B 3-wire bus software compatible to LC725 (Sanyo) I 2 C bus mode: 4 bidirectional ports (open collector) 2 unidirectional ports (open collector) 5 level ADC or unidirectional port (open collector) Address mode select function (AMS, Pin 3): 3 or 4 addresses selectable via Pin This IC contains an integrated preamplifier, a high frequency prescaler, a reference divider with multiple programmable divider ratios, a crystal oscillator, a phase/ frequency detector together with a charge pump, a tuning amplifier and an analog-to-digital converter. 3-wire bus mode: 4 unidirectional ports (open collector) Lock output (open collector) Programmable reference divider Low power consumption (typ. 5 V / 23 ma) Electrostatic protection according to MIL-STD 883 Block Diagram AS / ENABLE / P3 5 bit Latch UNI BUS SCL 5 Control SDA 4 Vs 2 GND 5 Power on reset POR 7 bit Latch 4 bit Shift Reg. 8 bit Latch 7 bit Latch T ADC I/O Ports P/Lock 9 P4 8 P5 7 P6 / ADC 6 P7 Sync 5 bit Latch T 5I RD,2,3 OS LOCK RFi 4 3 RDS / AMS 3 XTAL 2 Oscillator div. by 6 Prescaler AMS RDS SET 5/4 bit counter divide by 256/52/off/24 divide by 25/5/4/25 divide by 5//28/5 Phase detector Charge pump FP FR 6VD PD Figure. Block diagram Rev. A5, 2-Nov- (5)

2 Ordering Information Extended Type Number Package Remarks U6239B-MFPG3 SO6, plastic package Taped and reeled Pin Configuration PD Q RDS/AMS SDA SCL P7 P6/ ADC P Figure 2. Pinning Circuit Description VD GND RFi RFi V S P/ Lock AS/ENABLE/ P3 The U6239B is a single-chip PLL designed for SAT TV tuner and cable tuner. It consists of a divide-by-6 prescaler with an integrated preamplifier, a 5-bit programmable divider, a crystal oscillator, and a reference divider with selectable divider ratios, a phase/ frequency detector together with a charge pump which drives the tuning amplifier. Only one external transistor is required for varactor line driving. The device can be controlled via I 2 C bus format or via 3-wire bus format. It detects automatically which bus format has been received. Therefore, there is no need for a bus selection pin. In I 2 C bus mode, the device has four programmable or one fixed and three programmable I 2 C bus addresses, depending on the voltage level at Pin 3. They are P4 SSO6 package on request Pin Symbol Function ÁÁÁÁ PD Charge pump output 2 Q Crystal input 3 RDS/ AMS Reference divider select input (3-wire bus mode) Address mode select input (I 2 C bus mode) 4ÁÁÁÁÁ SDA ÁÁÁÁ Data input/ output ÁÁ 5ÁÁÁÁÁ SCL ÁÁÁÁ Clock input ÁÁ 6 ÁÁÁÁÁ P7 ÁÁÁÁ Port 7 input/ output ÁÁ ÁÁ 7 ÁÁÁÁÁ P6/ ÁÁÁÁ Port 6 output ÁÁÁÁÁ ADC ÁÁÁÁ Analog-Digital-Converter input ÁÁ 8ÁÁÁÁÁ P5 ÁÁÁÁ Port 5 input/ output 9ÁÁÁÁÁ P4 ÁÁÁÁ Port 4 input/ output ÁÁ ÁÁÁÁÁ AS/ ÁÁÁÁ Address select input ÁÁÁÁÁ ENABLE/ ÁÁÁÁ Enable input P3 Port 3 output ÁÁÁÁ P/Lock Port output/lock output 2 V S Supply voltage 3 RFi RF input 4 RFi RF input ÁÁ 5 ÁÁÁÁÁ GND ÁÁÁÁ Ground ÁÁ 6 ÁÁÁÁÁ VD ÁÁÁÁ Active filter output programmed by applying a specific input voltage to the address select input Pin, enabling the use of up to four synthesizers in a system. If the fixed address is used, this pin can be used as a normal output port. The same pin serves as the enable signal input in 3-wire bus mode. Depending whether the fixed address is used or not there are five or six open collector outputs for switching functions available. In 3-wire bus mode there are four open collector outputs and one lock signal output. All open collector outputs are capable of sinking at least ma. In I 2 C bus mode an analog-to-digital converter (ADC) is available for digital AFC (automatic frequency control) applications and the ports P4, P5 and P7 can also be used as input ports. 2 (5) Rev. A5, 2-Nov-

3 Functional Description The U6239B is programmed via a 2-wire I 2 C bus or 3-wire bus depending on the received data format. In I 2 C bus mode the three bus input pins 4, 5, are used as SDA, SCL and address select inputs or in 3-wire bus mode as date, clock and enable inputs, respectively. The data include the scaling factor SF and port output information. In I 2 C bus mode there are some additional functions available (ADC, bidirectional ports, etc.) Oscillator frequency calculation : f VCO = 6 SPF f refosc /SRF f vco : Locked frequency of voltage controlled oscillator SPF : Scaling factor of programmable divider (5 bit in I 2 C bus mode, 4 bit in 3-wire bus mode) SRF : Scaling factor of reference divider (256 52/24 in I 2 C bus mode, 25/5//4/2528/5 in 3-wire bus mode) f refosc : Reference oscillator frequency: 3.2/ 4 MHz crystal or external reference frequency (max. 8 MHz) The input amplifier together with a divide-by-6 prescaler provides excellent sensitivity (see Typical prescaler input sensitivity ). The input impedance is shown in the diagram Typical input impedance. When a new divider ratio is entered according to the requested f VCO, the phase detector and charge pump adjusts the control voltage of the VCO together with the tuning amplifier until the output signals of the programmable divider and the reference divider are in frequency locked and phase locked. The reference frequency may be provided by an external source, capacitively coupled into Pin 2, or by using an on-board crystal with an 8 pf capacitor in series. The crystal operates in the series resonance mode. The reference divider division ratio is selectable to 256/ 52/ 24 in the I 2 C bus mode and 25/ 5/ / 4/ 25/ 28/ 5 in the 3-wire bus mode. In I 2 C bus mode, the division ratio may be set via three bits, in 3-wire bus mode via two bits and a voltage at the reference divider select input Pin 3. In addition, there are port outputs available for band switching and other purposes. Application A typical application is shown on page 4. All input/ output interface circuits are shown on the pages 2 and 3. Some special features which are related to test- and alignment procedures for tuner production are explained together with the bus mode descriptions. Absolute Maximum Ratings All voltages are referred to GND (Pin 5) Parameters Symbol ÁÁÁÁÁ ConditionsÁÁÁÁÁ Min. ÁÁÁÁ Max. ÁÁÁÁ Unit Supply voltage Pin 2 Vs ÁÁÁÁÁ ÁÁÁÁÁ.3 ÁÁÁÁ 6 ÁÁÁÁ V RF input voltage Pins 3, 4 RFi ÁÁÁ.3 ÁÁÁÁ Vs +.3ÁÁÁÁ V Port output current Pins 6- P, P3-7 ÁÁÁÁÁ Open collectorááááá ÁÁÁÁ 5 ÁÁÁÁ ma Total port output current Pins 6- P, P3-7 ÁÁÁÁÁ Open collectorááááá ÁÁÁÁ 5 ÁÁÁÁ ma Port input/ output voltage Pins 6- P3-7 ÁÁÁÁÁ In off state ÁÁÁÁÁ.3 ÁÁÁÁ 4 ÁÁÁÁ V Port output voltage Pins 6- P, P3-7 ÁÁÁÁÁ In on state ÁÁÁÁÁ.3 ÁÁÁÁ 6 ÁÁÁÁ V Bus input/ output voltage Pins 4 and 5 VSDA, VSCL ÁÁÁ.3 ÁÁÁÁ 6 ÁÁÁÁ V SDA output current Pin 4 ISDA ÁÁÁÁÁ Open collectorááááá ÁÁÁÁ 5 ÁÁÁÁ ma Address select/ Enable input Pin AS/ ÁÁÁÁÁ Port in off ÁÁÁÁÁ.3 ÁÁÁÁ 4 ÁÁÁÁ V Port output voltage ENABLE/ P3 state ÁÁÁÁ Charge pump output voltage Pin PD.3 Vs +.3 V ÁÁÁÁ Active filter output voltage Pin 6 VD.3 Vs +.3 V Á ÁÁÁÁ Crystal oscillator voltage Pin 2 Q.3 Vs +.3 V Reference divider select input/ Pin 3 RDS/.3 V S +.3 V Address mode select input AMS Junction temperature T j 4 25 C Storage temperature T stg 4 25 C Rev. A5, 2-Nov- 3 (5)

4 Operating Range All voltages are referred to GND (Pin 5) Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit ÁÁÁ Supply voltage Pin 2 V S ÁÁÁÁ 4.5 ÁÁÁÁ 5 ÁÁÁÁ ÁÁÁÁ 5.5 V Á ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ Ambient temperature T amb 2 85 C ÁÁÁ ÁÁÁ ÁÁÁÁ Á Input frequency Pins 3 and 4 RFi MHz ÁÁÁ Á Programmable divider I 2 C bus mode SF ÁÁÁ Á Programmable divider 3-wire bus mode SF Thermal Resistance Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Junction ambient Package SO6 soldered to PCB R thja K/W Electrical Characteristics Test conditions (unless otherwise specified): V S = 5 V, T amb = 25 C Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Á Supply current (prescaler on) Ports off Pin 2 ICC 23 ma ÁÁ ÁÁ Input sensitivity ÁÁÁÁ f RFi = 25 MHz ÁÁÁ Pin 3 ÁÁÁÁÁ Vi ) ÁÁÁ 3 ÁÁÁ mv rms ÁÁÁÁ f RFi = MHz ÁÁÁ Pin 3 ÁÁÁÁÁ Vi ) ÁÁÁ 2 3 ÁÁÁ mv rms ÁÁ Crystal oscillator ÁÁÁÁ Recommended crystal series ÁÁ Á 2 ÁÁÁ ÁÁÁÁ resistance Á ÁÁÁÁ Crystal oscillator drive level ÁÁÁ Pin 2 ÁÁÁÁÁ 5 mv rms ÁÁÁÁ Crystal oscillator source ÁÁÁ Nominal spread 5% ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ 65 ÁÁÁÁ ÁÁÁ ÁÁÁ impedance Pin 2 ÁÁÁ External reference input AC coupled sinewave ÁÁÁÁ frequency ÁÁÁ Pin 2 Á ÁÁÁ 2 ÁÁÁ ÁÁÁÁ ÁÁÁ 8 MHz ÁÁÁÁ External reference input ÁÁÁ AC coupled sinewave Á ÁÁÁÁ amplitude ÁÁÁ Pin2 Á 7 2 ÁÁÁ mv rms ÁÁ Port outputs (current limited, output function only in I 2 C bus mode) Port P at Pin. Port P3 at Pin, is only usable with AMS = L (= 3 address mode). P, P3 Sink current VH = 2 V, Pins and ISL.7.5 ma Leakage current VH = 3.2 V IL A Port outputs, Lock output (open collector, locked = L. Ports P4 P7 at Pins 6 9) Lock output at Pin, only in 3-wire bus mode. Saturation voltage IL = ma VSL 2 ).5 V Leakage current VH = 3.2 V IL A 4 (5) Rev. A5, 2-Nov-

5 Electrical Characteristics (continued) Parameters Test Conditions / Pins Symbol Min. Typ. Max. Unit Port inputs (Ports 4, 5 and 7 at Pins 6, 8 and 9) Input voltage high Vi H 2.7 V Input voltage low Vi L.8 V Input current high Vi H = 3.2 V Ii H A Input current low Vi L = V Ii L A ADC input (ADC, Pin 7, see page 8 for ADC-levels) Input current high Vi H = 3.2 V Ii H A Input current low Vi L = V Ii L A Charge pump output (PD) Charge pump current H 5I =, VPD =.7 V, Pin IPDH 8 A Charge pump current L 5I =, VPD =.7 V, Pin IPDL 5 A Charge pump leakage current T =, VPD =.7 V, Pin IPDTRI 5 na Charge pump amplifier gain Pins and 6 64 Bus inputs Data and Clock (SDA, SCL) I 2 C bus mode and 3-wire bus mode Input voltage high Pins 4 and 5 Vi H V Input voltage low Pins 4 and 5 Vi L.5 V Input current high Vi H = V S, Pins 4 and 5 Ii H A V + Input current low Vi L = V, Pins 4 and 5 Ii L 2 A Output voltage SDA (open collector) ISDA L = 3 ma, Pin 4 VSDA L.4 V Bus input Enable, 3-wire bus mode (ENABLE, Pin ) Input voltage high Pin Vi H 75% V V S S.3 V Input voltage low Pin Vi L. V Input current high Vi H = V S, Pin Ii H A Input current low (RDS = L ) Vi L = V, Pin Ii L A Input current low (RDS = H ) Vi L = V, Pin Ii L A Address selection / port output (AS/P3, Pin ) Input current low (AMS = L) Vi L = V (3 address) Ii L A Input current high (AMS = L) Vi H = 3.2 V (3 address) Ii H A Input current low (AMS = H) Vi L = V (4 address) Ii L A Input current high (AMS = H) Vi H = V S (4 address) Ii H A Reference divider select/address mode select (RDS, AMS) Input voltage high Pins 4 and 5 Vi H V Input voltage low Pins 4 and 5 Vi L.5 V Input current high Vi H = V S, Pins 4 and 5 Ii H A Input current low Vi L = V, Pins 4 and 5 Ii L 2 A Notes: ) RMS - voltage calculated from the measured available power on 5. 2 ) Tested with one port active. The collector voltage of an active port must not exceed 6 V. Rev. A5, 2-Nov- 5 (5)

6 I 2 C Bus Description Functional Description When the U6239B is controlled via a 2-wire I 2 C bus format, then data and clock signals are fed into the SDA and SCL lines respectively. Depending on the LSB of the address byte, the device can either accept new data (write mode: LSB = ) or send data (read mode: LSB = ). Depending on the voltage at the address mode select input, the device has one fixed and three programmable or four programmable I 2 C bus addresses. The tables I 2 C bus write data format and I 2 C bus read data format describe the format of the data and show how to select the device addresses by applying the appropriate voltages at address select Pin and the address mode select Pin 3. Write Mode (Address byte LSB = ) When write mode is activated and the correct address byte is received, the SDA line is pulled low by the device during the acknowledge period. The SDA line is also pulled low during the acknowledge periods, when additional data bytes are programmed. After the address transmission (first byte), data bytes can be sent to the device. There are four data bytes requested to fully program the device. Once the correct address is received and acknowledged, the first bit of the following byte determines whether that byte is interpreted as byte 2 or 4; a logic for divider information and a logic for control and port output information. If byte 2 has been received, the device always expects byte 3 next. Likewise if byte 4 has been received, byte 5 is expected. Additional data bytes can be entered without the need to re-address the device until an I 2 C bus stop condition is recognized. This allows a smooth frequency sweep for fine tuning AFC purposes. The table I 2 C bus pulse diagram provides some possible data transfer examples. In addition, the stop condition is not a must, the device may be programmed by using the start condition only. The programmable divider bytes PDB and PDB2 are stored in a 5-bit latch and control the division ratio of the 5-bit programmable divider. The control byte CB enables the controlling of the following special functions: 5I bit switches between low and high charge pump current T bit enables divider test mode when it is set to logic T bit enables the charge pump to be disabled when it is set to logic RD3, 2 and - bits enable selection of the reference divider ratio OS-bit disables the charge pump drive amplifier output when it is set to logic. The charge pump current can only be controlled in I 2 C bus mode. In 3-wire bus mode, the high charge pump current is always active. The OS-bit function disables the complete PLL function. This enables the tuner alignment by supplying the tuning voltage directly through the 3 V supply voltage of the tuner. The control byte CB2 programs the port outputs P and P3-7. Description MSB I 2 C Bus Data Format ÁÁÁÁÁ Address byte ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ AS ÁÁÁÁ AS2 ÁÁÁ ÁÁÁ A ÁÁÁÁÁ Programmable divider, byte ÁÁÁ ÁÁÁÁ n4 ÁÁÁ n3 ÁÁÁ n2 ÁÁÁ n ÁÁÁ n ÁÁÁÁ n9 ÁÁÁ n8 ÁÁÁ A ÁÁÁÁÁ Programmable divider, byte 2 ÁÁÁ n7 ÁÁÁÁ n6 ÁÁÁ n5 ÁÁÁ n4 ÁÁÁ n3 ÁÁÁ n2 ÁÁÁÁ n ÁÁÁ n ÁÁÁ A ÁÁÁÁÁ Control byte ÁÁÁ ÁÁÁÁ 5I ÁÁÁ T ÁÁÁ T ÁÁÁ X ÁÁÁ RD2 ÁÁÁÁ RD ÁÁÁ OS ÁÁÁ A ÁÁÁÁÁ Control byte 2 ÁÁÁ P7 ÁÁÁÁ P6 ÁÁÁ P5 ÁÁÁ P4 ÁÁÁ P3 ÁÁÁ X ÁÁÁÁ X ÁÁÁ P ÁÁÁ A A = Acknowledge; X = not used n to n4 : Scaling factor (SF) SF = 6384n n n + n SF - range: 256 to T, T : Test mode selection T = : divider test mode on, T = : divider test mode off FP at Pin 6, FR at Pin 7 T = : charge pump disable T = : charge pump enable P, 3 to 7: Port outputs P, 3, 4, 5, 6, 7 = : port active 5I : Charge pump current switch 5I = : high current 5I = : low current OS : Output switch OS = : varicap drive disable OS = : varicap drive enable LSB 6 (5) Rev. A5, 2-Nov-

7 I 2 C Bus Description (continued) Reference divider selection RD, RD2: RD2 RD Reference Divider Ratio * when a 4MHz crystal is used Address selection AS, AS2, AMS: 24 off Frequency Step Size* 62.5 khz 25 khz 25 khz Max. Operating Frequency* 2.47 GHz AMS Voltage at Pin 3 <.8 V or open <.8 V or open <.8 V or open <.8 V or open > 2.4 > 2.4 > 2.4 > 2.4 AS AS2 Address Dec. Value Voltage at Pin C C2 C4 C6 C C2 C4 C to % V S always valid 4 to 6% V S 9% V S to 3.2 V to % V S open 4 to 6% V S 9% V S to V S Read Mode (Address byte LSB = ) After the address transmission (first byte), the status byte can be read from the device on the SDA line (MSB first). Data is valid on the SDA line during logic high of the SCL signal. The controller accepting the data has to pull the SDA line to low-level during all status-byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line to low-level during this period, the device will then release the SDA line to allow the controller to generate a STOP condition. The POR bit (power-on-reset) is set to a logic when the supply voltage V S of the device has dropped below 3 V (at 25 C) and also when the device is initially turned on. The POR bit is reset to a logic when the read sequence is terminated by a STOP condition. When the POR bit is set high (at low V S ), this indicates that all the programmed information is lost and the port outputs are all set to high impedance state. The FL bit indicates whether the loop is in phase lock condition (logic ) or not (logic ). If the ADC or the ports are to be used as inputs, the corresponding outputs must be programmed to a high impedance state (logic ). The bits I2, I and I show the status of the I/O ports P7, P5 and P4 respectively. A logic indicates a LOW level and a logic a HIGH level (TTL levels). The bits A2, A and A represent the digital information of the 5-level ADC. This converter can be used to feed AFC information to the controller from the IF section of the receiver, as shown in the typical application circuit on page 4. Rev. A5, 2-Nov- 7 (5)

8 I 2 C Bus Description (continued) Description MSB I 2 C Bus Read Data Format Address byte ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Status byte ÁÁÁÁ POR ÁÁÁ FL ÁÁÁ I2 ÁÁÁ I ÁÁÁ LSB AS ÁÁÁ AS2 ÁÁÁ ÁÁÁÁ ÁÁÁ A IÁÁÁÁ A2 ÁÁÁ A ÁÁÁ A ÁÁÁ POR : Power-on reset flag: POR = on power on FL : In-lock flag: FL =, when loop is phase locked I2, I, I : Digital information of I/O-ports P7, P5 and P4 respectively A2, A, A : Digital data of the 5-level ADC. see next table A/D Converter Levels: A2 A A Input voltage to ADC Pin 9 ÁÁÁ ÁÁÁÁ ÁÁÁ 6% Vs to 3.2 V ÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ 45% to 6% Vs ÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ 3% to 45% Vs ÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ 5% to 3% Vs ÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ V to 5% Vs I 2 C Bus Pulse Diagram Address byte / A /.Byte / A / 2.Byte / A / 3.Byte / A / 4.Byte / A / SDA SCL START STOP Data transfer examples START ADR PDB PDB2 CB CB2 STOP START ADR CB CB2 PDB PDB2 STOP START ADR PDB PDB2 CB STOP START ADR PDB PDB2 STOP START ADR CB CB2 STOP START ADR CB STOP Description START = Start condition ADR = Address byte PDB = Programmable divider byte PDB2 = Programmable divider byte 2 CB = Control byte CB2 = Control byte 2 STOP = Stop condition 8 (5) Rev. A5, 2-Nov-

9 I 2 C-Bus Description (continued) I 2 C-Bus Timing t W STT SDA t S STT t t t t t LOW HIGH R F S STP SCL t H STT t S DAT t H DAT START CLOCK DATACHANGE STOP Figure 3. I 2 C-bus timing Parameters Symbol Min. Max. Unit Rise time SDA, SCL t R ÁÁÁÁÁ ÁÁÁÁÁ 5 ÁÁÁÁÁ s Fall time SDA, SCL t F ÁÁÁÁÁ ÁÁÁÁÁ 5 ÁÁÁÁÁ s Clock frequency SCL f SCL ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ khz Clock H pulse t HIGH ÁÁÁÁÁ ÁÁÁ s Clock L pulse t LOW ÁÁÁÁÁ ÁÁÁ s Hold time start t H ÁÁÁÁÁ STT ÁÁÁ s Waiting time start t W ÁÁÁÁÁ STT ÁÁÁ s Setup time start t S ÁÁÁÁÁ STT ÁÁÁ s Setup time stop t S ÁÁÁÁÁ STP ÁÁÁ s Setup time data t S DAT ÁÁÁÁÁ.25 ÁÁÁ s Hold time data ÁÁÁÁ ÁÁÁ s t H DAT 3-Wire Bus Description When the U6239B is controlled via a 3-wire bus format, then data, clock and enable signals are fed into the SDA, SCL and AS/ENABLE/P3 lines respectively. The diagram 3-wire bus pulse diagram shows the data format. The data consist of a single word which contains the programmable divider (4 bit) and port information. Bit No. 5 of the programmable divider is always zero, when the 3-wire bus mode is active. The data is only clocked into the internal data shift register on the negative clock transition during the enable high period. During enable low periods the clock input is disabled. New data words are only accepted by the internal data latches from the shift register on a negative transition of the enable signal if exactly eigtheen clock pulses were sent during the high period of the enable. The data sequence and the timing is described in the following diagrams. In 3-wire bus mode Pin 9 automatically becomes the lock-signal output. An improved lock detect circuit generates a flag when the loop has attained lock. In lock is indicated by a low impedance state (on) of the open collector output. In 3-wire bus mode the high charge pump current is always active. The charge pump current can only be controlled in I 2 C bus mode. The complete PLL function can be disabled by programming a normally not used division ratio of zero. This allows the tuner alignment by supplying the tuning voltage directly through the 33 V supply voltage of the tuner. In 3-wire bus mode the division ratio of the reference divider is controlled via information RD, RD2 and the reference divider select input Pin 3. Rev. A5, 2-Nov- 9 (5)

10 3-Wire Bus Description (continued) Reference divider selection RD, RD2, RDS: RDS Voltage at Pin 3 RD2 RD Reference Divider Ratio Frequency Step Size* Maximum Operating Frequency* to % V S or open to % V S or open to % V S or open to % V S or open khz 28 khz 28 khz 64 khz 2.97 GHz 9 to % V S 9 to % V S 9 to % V S 9 to % V S khz 256kHz 256 khz 28 khz * when a 4-MHz crystal is used 3-Wire Bus Pulse Diagram SDA 4 Port bits/ 2 Ref.Div. bits P4 P5 RD RD2 P6 P7 MSB n3 4-bit scaling factor SF LSB n SCL ENABLE Figure 4. 3-wire bus pulse diagram n to n3 Scaling factor (SF) SF = 892n n n + n SF - Range: P4 to P7 Port outputs P4 - P7 = : port active RD, RD2 Reference divider selection see table above 3-Wire Bus Timing Data LSB Clock Enable TL TS TC TH TSL TT Figure 5. 3-Wire bus timing Parameters Symbol Min. Max. Unit ÁÁ Setup time ÁÁÁÁ TS ÁÁÁÁÁ 2 ÁÁÁÁÁ ÁÁÁÁÁ s ÁÁ Enable hold time ÁÁÁÁ TSL ÁÁÁÁÁ 2 ÁÁÁÁÁ ÁÁÁÁÁ s ÁÁ Clock width ÁÁÁÁ TC ÁÁÁÁÁ 2 ÁÁÁÁÁ ÁÁÁÁÁ s ÁÁ Enable setup time ÁÁÁÁ TL ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ s ÁÁ Enable between two transmissions ÁÁÁÁ TT ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ s ÁÁ Data hold time ÁÁÁÁ TH ÁÁÁÁÁ 2 ÁÁÁÁÁ ÁÁÁÁÁ s (5) Rev. A5, 2-Nov-

11 Typical Prescaler Input Sensitivity Vi (mv rms on 5 ) Operating window Frequency (MHz) Figure 6. Typical Prescaler Input Sensitivity Typical Input Impedence j.5j 2j.2j 4. GHz 5j 3.5 GHz GHz MHz.2j 2.5 GHz 5 MHz 5j.5j 2. GHz.5 GHz j GHz 2j Z = 5 Ω Figure 7. Typical input impedance Rev. A5, 2-Nov- (5)

12 Input/ Output Interface Circuits Vref Vs.5k.5k RF Port RF2 Vref Figure 8. RF input Figure. Ports P4, P5, P6, P7 6 2k PD P3 Vs AMS 25k 2k AS / P3 ENABLE 375k Vref OS (O/P Disable) 45k VD AMS Figure. Address select/ Enable input/ Port output P3 Figure 9. Loop amplifier 2 (5) Rev. A5, 2-Nov-

13 V S Vs P Lock 2k Port P/Lock SDA/SCL/RDS/AMS 3 k 4 k 2 ACK RDS/AMS only SDA only Figure 4. Port P/ Lock output Figure 2. SCL/SDA and RDS/AMS input Vs XTAL Q Figure 3. Reference oscillator Rev. A5, 2-Nov- 3 (5)

14 Application Circuit f SAT SAT Tuner f f IF VCO AFC 22k 33V 22n RDS/AMS 4 MHz 8 p ADC n RFi n 39k n U6239B Vs GND SDA from/to C SCL AS / ENABLE / P3 P7 P5 P4 P / Lock p Figure 5. Application circuit Package Information Package SO6 Dimensions in mm technical drawings according to DIN specifications (5) Rev. A5, 2-Nov-

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