DATA SHEET. SDN8080G 80-outputs common/segment driver. data sheet (v6) 2005 Sep 29

Transcription

1 DATA HEET DN8080G 80-outputs common/segment driver To improve design and/or performance, Avant Electronics may make changes to its products. Please contact Avant Electronics for the latest versions of its products data sheet (v6) 2005 ep 29

2 DN8080G 1 GENERAL 1.1 Description The DN8080G is a OMMON/EGMEMT driver for large-panel dot-matrix TN LD module. It can be used either as a OMMON driver or as a EGMENT driver, by connecting its input to or V. When its input is connected to, the DN8080G is an 80-OMMON driver. When its input is connected to V, the DN8080G is an 80-EGMENT driver. 1.2 Features Operating voltage range (-V, control logic): 2. ~ 5.5 volts. LD bias voltage range (-VEE): 6 ~ 28 volts. 80-EGMENT driver or 80-OMMON driver, via -pin selection. When used as a EGMENT driver, -bit parallel or 1-bit serial interface with a controller. When used as a OMMON driver, two modes of operation are available: ingle mode or Dual mode. Display duty cycle: 1/6 ~ 1/256. LD on/off control, when used as EGMENT driver. External -level LD bias voltage. Operating frequency range: 8 MHz, when = 5 volts. Operating temperature range: -30 to +85. torage temperature range: -55 to ep 29 2 of 0 data sheet (v6)

3 DN8080G 2 ORDERING INFORMATION Table 1 Ordering information TYPE NUMBER DN8080G-LQFPG DN8080G-QFPG DN8080G-LQFP DN8080G-QFP DN8080G-D DERIPTION LQFP100 Pb-free package. QFP100 Pb-free package. LQFP100 general package. QFP100 general package. Tested die ep 29 3 of 0 data sheet (v6)

4 DN8080G 3 FUNTIONAL BLOK DIAGRAM AND DERIPTION 3.1 Functional block diagram V0 V12 V3 V5 VEE 80-bit -level driver bit level shifter High-voltage area M DIPOFFB Output voltage level LK bit data latch / bi-directional shift register for OMMON data D1_ID D2_DL D3_DM K 20 x -bit (or 80 x 1-bit) bi-directional shift register for EGMENT data L1 L2 lock ontrol Data Latch ontrol AM Power down function ERB V ELB Fig.1 Functional diagram 2005 ep 29 of 0 data sheet (v6)

5 DN8080G 3.2 Block description Table 2 Block description lock control NAME OM/EG DERIPTION Data latch control Power down function OM/EG EG EG Inputs to this block are external signals L1, L2,, and AM. It generates latch clock (LK) and shift clock (K). K is used to shift display data into the 20 x -bit bi-directional shift register for EGMENT data. This block controls shift direction of the 20 x -bit shift register and selects its input data pins. In OMMON driver application, this block is disabled. This block enables or disables lock ontrol block according to ERB/ELB input. Output level selector OM/EG ontrols the output voltage level according to input signals M and DIPOFFB. This is the bi-directional 20 x -bit (80-bits) shift register for EGMEMT data. 20 x -bit In 1-bit serial interface mode of EGMEN driver application, 80 K clocks are bi-directional shift EG needed to shift in 80-bit data. In -bit parallel interface mode, only 20 K register for clocks are needed to shift in 80-bit data. EGMENT data In OMMON driver application, this block is disabled. In EGMENT driver application, this block is used as an 80-bit data latch and the 80-bit data of the EGMENT driver are latched into this latch for output. 80-bit data latch, or bi-directional shift register for OMMON data 80-bit level shifter OM/EG EG In single type OMMON driver application, this block is used as an 80-bit shift register. Depending on the value of HL, 1-bit serial data is shifted into D2_DL or. In dual type OMMON driver application, depending on the value of HL, the 80-bits shift register is divided into two sections with each section having 0-bits. Data are then shifted into the shift register via D2_DL and D3_DM, or D3_DM and. Please refer to Table 6 and Table. This block translates signals from logical voltage to high voltage for driving the TN LD panel. 80-bit -level driver EG elects output voltage levels according to M and the latched data value ep 29 5 of 0 data sheet (v6)

6 DN8080G PINNING DIAGRAM.1 Pinning diagram of LQFP100 package DN8080G-LQFP ELB L1 AM L2 D1_ID D2_DL D3_DM V HL DIPOFFB M V0 V12 V3 V5 VEE ERB Fig.2 Pin assignment of the LQFP100 package ep 29 6 of 0 data sheet (v6)

7 DN8080G.2 Pinning diagram of QFP100 package DN8080G-QFP ELB L1 AM L2 D1_ID D2_DL D3_DM V HL DIPOFFB M V0 V12 V3 V5 VEE ERB Fig.3 Pin assignment of the QFP100 package 2005 ep 29 of 0 data sheet (v6)

8 DN8080G.3 Pad diagram pad # Y (0,0) X hip ID ERB VEE V5 V3 V12 V0 M DIPOFFB HL V D3_DM D2_DL D1_ID L2 AM L1 ELB 50 Note: 1. For chip_on_board (OB) bonding, chip carrier should be connected to or left open. hip carrier is the metal pad to which die is attached. 2. The chip size is : 25 µm x 3169 µm. 3. The hip ID is: Fig. Pad locations ep 29 8 of 0 data sheet (v6)

9 DN8080G. Pad description Table 3 Pad signal names and coordinates The unit for coordinates is µm. PAD NO. PAD NAME OORDINATE PAD PAD OORDINATE PAD PAD OORDINATE NO. NAME NO. NAME X Y X Y X Y V V M DIPOFFB HL V D3_DM D2_DL D1_ID L AM L ELB ERB VEE V V ep 29 9 of 0 data sheet (v6)

10 DN8080G.5 ignal description Table Pad signal description. To avoid a latch-up effect at power-on: V 0.5 V < voltage at any pin at any time < V DD V. YMBOL I/O Interface to/from DERIPTION V0, V12, V3, External bias voltage for LD driver. input power V5 1~80 output LD EGMENT or OMMON driver outputs. In EGMENT driver application mode, L2 is the shifting clock of the 20 x -bit bi-directional shift register. L2 input controller In OMMON driver application mode, this clock is not used. The display data is shifted to the 80-bit OMMON data bi-directional shift register by L1. This input has an internal pull-high PMO. When the device is used as OMMON driver, the PMO is turned on to internally pull this input to HIGH and this pin should therefore be left open or connected to. Please refer to ection 13. M input controller Alternating signal for generating alternating LD-bias voltage. In EGMENT driver application mode, the 80-bits display data is latched into the shift register at the falling edge of this clock. L1 input controller DIPOFFB input controller input /V In OMMON driver application mode, L1 is used as shifting clock of OMMON output data. During the LOW period of this signal, V0 is selected as 0~80 s outputs and the display is therefore turned off. If is connected to V, the DN8080G is used as an 80-output EGMENT driver. If is connected to, the DN8080G is used as an 80-output OMMON driver. Application Mode election. Together with input, this input is used to configure DN8080G into different application modes, as shown in the following table. AM input /V AM application mode OM/EG 0 0 -bit parallel data interface with a controller bit serial data interface with a controller. EG 1 0 ingle-type application mode 1 1 Dual-type application mode OM 2005 ep of 0 data sheet (v6)

11 DN8080G YMBOL D1_ID, D2_DL, D3_DM, I/O I/O, D2, D. Input, D1, D3 Interface to/from controller HL input /V DERIPTION In EGMENT Driver mode and when -bit parallel data interface mode is selected, these inputs are used as -bit parallel data input from a controller. In EGMENT driver mode and when 1-bit serial interface mode is selected, D1_ID is used as serial data input from a controller. In this application, all other 3 inputs must be connected to. In OMMON driver mode and when single-type application mode is selected, OMMON scan pulse is shifted from D2_DL to or from to D2_DL, depending on the logic state of HL. In OMMON driver mode and when dual-type application mode is selected, OMMON scan pulse is shifted from D2_DL and D3_DM to, or from and D3_DM to D2_DL, depending on the logic state of HL. hift direction control. When this input is connected to V, data shift direction is from left to right. When this input is connected to, data shift direction is from right to left. Please refer to Table 6 and Table. In order to reduce power consumption, in EGMENTdriver application mode, the internal operation of the DN8080G is enabled only when its enable input (ELB or ERB) is at LOW. When several DN8080G are connected in cascade, their enable inputs(elb or ERB) are serially enabled. The enabling sequence is decided by HL, as listed below. ELB, ERB input/ output cascade HL egment Driver ELB ERB L Output Input H Input Output In OMMON driver application, these two pins are not used and should be left open ep of 0 data sheet (v6)

12 DN8080G 5 OUTPUT VOLTAGE LEVEL Table 5 Output voltage level M LATHED DATA DIPOFFB OUTPUT LEVEL(1-80) EGMENT MODE L L H V12(V2) V12(V1) L H H V0 V5 H L H V3(V3) V3(V) H H H V5 V0 x(don t care) x(don t care) L V0 V0 OUTPUT LEVEL(1-80) OMMON MODE 2005 ep of 0 data sheet (v6)

13 DN8080G 6 LD BIA VOLTAGE 6.1 EGMENT driver application (=LOW) R R (n-) R R R VEE V0 V1 V2 V3 V V5 to OM driver to OM driver V0 V12 V3 V5 Note: (1) The recommended value for R is in the range from 1K to 10K ohm. (2) The recommended value for is 0.1 µf. DN8080G V EG1~EG80 To LD Panel V0, V5 election level V2, V3 Non-selection level. n= 9 (when 1/6 duty) to 1 (when 1/256 duty) Fig.5 EGMENT driver application. 6.2 OMMON driver application (=HIGH) V0 V0 (n-) R R R V1 V2 V3 to EG driver V12 DN8080G OM1~OM80 To LD Panel R V R V5 VEE V3 V5 V V0, V5 election level V1, V Non-selection level. n= 9 (when 1/6 duty) to 1 when ( 1/256 duty ) Note: (1) The recommended value for R is in the range from 1K to 10K ohm. (2) The recommended value for is 0.1 µf. Fig.6 OMMON driver application ep of 0 data sheet (v6)

14 DN8080G DATA HIFT DIRETION AND DATA PIN I/O ELETION Table 6 Data shift direction in EGMENT driver application (=LOW). AM HL Application mode DATA HIFT DIRETION INPUT PIN(PAD) L D1 D2 D3 D D1 D2 D3 D D1 D2 D3 D L -bit parallel data interface mode D1 D2 hift direction D3 last data D first data { D1_ID, D2_DL, D3_DM, H D D3 D2 D1 D D3 D2 D1 D D3 D2 D1 { first data hift direction D1 D2 D3 D last data L H H 1-bit serial data interface mode Last data (D1_ID) hift direction first data D1_ID first data hift direction last data (D1_ID) 2005 ep 29 1 of 0 data sheet (v6)

15 DN8080G Table Data shift direction in OMMON driver application (=HIGH) AM HL Application mode DATA HIFT DIRETION Input pin(pad) hift direction L D2_DL L ingle-type application mode Input data (D2_DL) hift direction Output data () H Output data (D2_DL) Input data () hift direction L D2_DL, D3_DM H dual-type application mode Input data1 (D2_DL) Input data2 (D3_DM) hift direction Output data () H , D3_DM Output data (D2_DL) Input data2 (D3_DM) Input data1 () 2005 ep of 0 data sheet (v6)

16 DN8080G Table 8 OM/EG ( pin) EG (=LOW) OM (=HIGH) Application of I/O data pins D1_ID, D2_DL, D3_DM, and. Application mode (AM pin) -bit parallel interface mode (AM=LOW) 1-bit serial interface mode (AM=HIGH) single-type application mode (AM=LOW) dual-type application mode (AM=HIGH) HL X X Data interface pins D1_ID D2_DL D3_DM D1 (input) D2 (input) D3 (input) D (input) D1_ID connected to. L D2_DL (input) (output) Open open H D2_DL (output) (input) L D2_DL (input1) D3_DM (input2) D2_DR (output2) Open H D2_DL (output2) D3_DM (input2) (input1) 2005 ep of 0 data sheet (v6)

17 DN8080G 8 ELETRIAL HARATERITI 8.1 Absolute maximum rating Table 9 Absolute maximum rating YMBOL PARAMETER MIN. MAX. UNIT V DD voltage on the input V V LD voltage difference between and VEE V V I (note 1) input voltage on any pin with respect to V 0.3 V DD V I I, I O input/output current on any I/O pin ±15 ma P tot total power dissipation (note 2) 1.5 W T stg storage temperature range T amb operating ambient temperature range Notes 1. The following applies to the Absolute Maximum Ratings: a) tresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge. However, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise noted. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package, not on device power consumption ep 29 1 of 0 data sheet (v6)

18 DN8080G 8.2 D characteristics for EGMENT driver application Table 10 D haracteristics for EGMENT driver application V DD = 5 V ±10%; V = 0 V; all voltages with respect to V unless otherwise specified; T amb = 30 to +85. YMBOL PARAMETER ONDITION MIN. MAX. UNIT V DD supply voltage ontrol logic circuit V V LD supply voltage for LD V LD = - VEE 6 28 V V IL LOW level input voltage note V DD V V IH HIGH level input voltage note 1 0.8V DD V DD V V OL LOW level output voltage I OL = 0. ma; note 2 0. V V OH HIGH level output voltage I OH = -0. ma; note 2 V DD 0. V I LI1 input leakage current of input pins note µa I LI2 input leakage current of V0~V5 note µa I TBY tandby current at =5 volts note 100 µa I TBY tandby current at =3 volts note µa I DD(=5V) Operating current at =5 volts note 6 5 ma I DD(=3V) Operating current at =3 volts note 2 ma I EE High-voltage operating current. note µa R ON ON resistance I ON = 100µA, note 9 2K (typ.), K (max.) Ω Notes to the D characteristics: 1. Measured for the following pins: L1, L2, ELB, ERB, D1_ID, D2_DL, D3_DM,, HL, DIPOFFB, M,, and AM. 2. Measured for the ERB pin and the ELB pin. 3. Measured for V0, V12, V3, and V5.. onditions for the measurement: =5V, V0=, V12=1.1 V, V3= V, V5=VEE= -23 V, F L1 =32 KHz, F L2 =5.12 MHz, HL=V, DIPLAYOFFB=, M=V, AM=0, no-load condition (1/256 duty, 1/1 bias), display data pattern= onditions for the measurement: =3V, V0=, V12=-0.06 V, V3= V, V5=VEE= -23 V, F L1 =32 KHz, F L2 =5.12 MHz, HL=V, DIPLAYOFFB=, M=V, AM=0, no-load condition (1/256 duty, 1/1 bias), display data pattern= onditions for the measurement: =5V, V0=, V12=1.1 V, V3= V, V5=VEE= -23 V, F L1 =32 KHz, F L2 =5.12 MHz, HL=V, DIPLAYOFFB=, F M =80 Hz, AM=0, no-load condition (1/256 duty, 1/1 bias), display data pattern= onditions for the measurement: =3V, V0=, V12=-0.06 V, V3= V, V5=VEE= -23 V, F L1 =32 KHz, F L2 = MHz, HL=V, DIPLAYOFFB=, F M =80 Hz, AM=0, no-load condition (1/256 duty, 1/1 bias), display data pattern= onditions for the measurement: =5V, V0=, V12=1.1 V, V3= V, V5=VEE= -23 V, F L1 =32 KHz, F L2 =5.12 MHz, HL=V, DIPLAYOFFB=, F M =80 Hz, AM=0, no-load condition (1/256 duty, 1/1 bias), display data pattern= Measured at VEE pin. 9. onditions for the measurement: VLD=-VEE, V0==5V, V5=VEE=-23V, V12= - (2/N) x VLD, V3=VEE + (2/N) x VLD, N=1 (1/256 duty, 1/1 bias) ep of 0 data sheet (v6)

19 DN8080G 8.3 D characteristics for OMMON driver application Table 11 D haracteristics for OMMON driver application V DD = 5 V ±10%; V = 0 V; all voltages with respect to V unless otherwise specified; T amb = 30 to +85. YMBOL PARAMETER ONDITION MIN. MAX. UNIT V DD supply voltage ontrol logic part V V LD supply voltage for LD V LD = - VEE 6 28 V V IL LOW level input voltage note V DD V V IH HIGH level input voltage note 1 0.8V DD V DD V V OL LOW level output voltage I OL = 0. ma; note 2 0. V V OH HIGH level output voltage I OH = -0. ma; note 2 V DD 0. V I LI1 input leakage current of input pins note µa I LI2 input leakage current of V0~V5 pins note µa I LI3 input leakage current of input pins note µa with internal pull-up MO. I TBY tandby current at =5 volts note µa I TBY tandby current at =3 volts note µa I DD(=5V) Operating current at =5 volts note 200 µa I DD(=3V) Operating current at =3 volts note µa I EE High-voltage operating current. note µa R ON ON resistance I ON = 100µA, note 10 2K (typ.), K (max.) Ω Notes to the D characteristics 1. Measured for the following input pins: L1, D2_DL(when HL=LOW), (when HL=HIGH), HL, DIPOFFB, M,, and AM. 2. Measured for the following output pins: D2_DL(when HL=HIGH) and (when HL=LOW). 3. Measured for V0, V12, V3, and V5.. Measured for the following input pins with internal pull-up: L2, D1_ID, D3_DM(AM=HIGH), ELB(HL=LOW), ERB(HL=HIGH). 5. onditions for the measurement: =5V, V0=, V12=3.35 V, V3= V, V5=VEE= -23 V, F L1 =32 KHz, F L2 =disabled, HL=V, DIPLAYOFFB=, D2_DL=M=V, AM=0, no-load condition (1/256 duty, 1/1 bias), D1_ID=D3_DM=, =ELB=ERB=OPEN. 6. onditions for the measurement: =5V, V0=, V12=1. V, V3= -21. V, V5=VEE= -23 V, F L1 =32 KHz, F L2 =disabled, HL=V, DIPLAYOFFB=, D2_DL=M=V, AM=0, no-load condition (1/256 duty, 1/1 bias), D1_ID=D3_DM=, =ELB=ERB=OPEN.. onditions for the measurement: =5V, V0=, V12=3.35 V, V3= V, V5=VEE= -23 V, F L1 =32 KHz, F L2 =disabled, HL=V, DIPLAYOFFB=, D2_DL=, f M =80Hz, AM=0, no-load condition (1/256 duty, 1/1 bias), D1_ID=D3_DM=, =ELB=ERB=OPEN. Display data pattern= , , , onditions for the measurement: =3V, V0=, V12=1. V, V3= -21. V, V5=VEE= -23 V, F L1 =32 KHz, F L2 =disabled, HL=V, DIPLAYOFFB=, D2_DL=, f M =80Hz, AM=0, no-load condition (1/256 duty, 1/1 bias), D1_ID=D3_DM=, =ELB=ERB=OPEN. Display data pattern= , , , onditions for the measurement: =5V, V0=, V12=3.35 V, V3= V, V5=VEE= -23 V, F L1 =32 KHz, F L2 =disabled, HL=V, DIPLAYOFFB=, D2_DL=, f M =80Hz, AM=0, no-load condition (1/256 duty, 1/1 bias), D1_ID=D3_DM=, =ELB=ERB=OPEN ep of 0 data sheet (v6)

20 DN8080G Display data pattern= , , , Measured at the VEE pin (that is, current flowing through the VEE pad). 10. VLD= -VEE, V0==5 volts, V5=VEE=-23 volts. V12= - (1/N) x VLD, V3= VEE+ (1/N) x VLD, N=1(1/256 duty, 1/1 bias). 8. A characteristics for EGMENT driver application Table 12 A characteristics for EGMENT driver application V DD = 5 V ±10%; V = 0 V; T amb = -30 to +85. =5V±10% =3V±10% Test YMBOL PARAMETER MIN. TYP MAX. MIN. MAX. condition UNIT t Y lock cycle time Duty=50% ns t WK lock pulse width 5 95 ns t R, t F lock rise/fall time ns t D Data set-up time ns t DH Data hold time ns t lock set-up time ns t H lock hold time ns t PHL Propagation delay time (ELB ns output) t PHL Propagation delay time (ERB ns output) t PU ELB set-up time ELB input ns t PU ERB set-up time ERB input ns t WDL DIPOFFB low pulse width ns t D DIPOFFB clear time ns t PD1 M - OUT propagation delay time L = 15 pf ns t PD2 L1 - OUT propagation delay L = 15 pf ns time t PD3 DIPOFFB - OUT propagation delay time L = 15 pf ns 8.5 A characteristics for OMMON driver application Table 13 A characteristics for OMMON driver application V DD = 5 V ±10%; V = 0 V; T amb = -30 to +85. =5V±10% =3V±10% Test YMBOL PARAMETER MIN. TYP MAX. MIN. MAX. condition UNIT t Y lock cycle time Duty=50% ns t WK lock pulse width 5 95 ns t R, t F lock rise/fall time ns t D Data set-up time ns t DH Data hold time ns t WDL DIPOFFB low pulse width ns t D DIPOFFB clear time ns t DL Output delay time L = 15 pf ns 2005 ep of 0 data sheet (v6)

21 DN8080G YMBOL PARAMETER =5V±10% =3V±10% Test condition MIN. TYP MAX. MIN. MAX. t PD1 M - OUT propagation delay time L = 15 pf ns t PD2 L1 - OUT propagation delay L = 15 pf ns time t PD3 DIPOFFB - OUT propagation delay time L = 15 pf ns UNIT 2005 ep of 0 data sheet (v6)

22 DN8080G 9 TIMING DIAGRAM 9.1 Timing diagram for EGMENT driver application L twck t t H L2 t WK t 0.2 WK 0.2 t t D t F R ty t DH D1_ID ~ DIPOFFB t WDL t D L1 L t PHL 0.8 ELB,ERB (Output1) 0.2 t PU ELB,ERB (Input 2) 0.2 M t PD1 L1 0.2 t PD2 DIPOFFB t PD (Latched data) Fig.18 Timing diagram for EGMENT driver application ep of 0 data sheet (v6)

23 DN8080G 9.2 Timing diagram for OMMON driver application t Y L t R t WK t F t F t D t DH DI ee note below t DL DO ee note below DIPOFFB t WDL t D Note: When in single-type interface mode: (1) DI=> D2_DL (HL=L), (HL=H). (2) DO=> (HL=L), D2_DL (HL=H). When in dual-type interface mode: (3) DI=>D2_DL and D3_DM (HL=L), and D3_DM (HL=H) () DO=> (HL=L), D2_DL (HL=H). M t PD1 L1 0.2 t PD2 DIPOFFB t PD (Latched data) Fig.19 Timing diagram for OMMON driver application ep of 0 data sheet (v6)

24 DN8080G 10 POWER DOWN FUNTION To reduce power consumption, the DN8080G is sequentially enabled via POWER DOWN mode, when used in cascade in EGMENT driver application. Table 1 Power Down function. HL Enable input Enable output current driver status ( the driver being enabled) status of other drivers L ERB ELB H ELB ERB While ERB=LOW, current driver is enabled. While ELB=LOW, current driver is enabled. Disabled. Disabled. Note 1. Power Down function is not available when the DN8080G is used as a OMMON driver. L1 1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1 L2 ELB1(Input1) ERB1/ELB2 (Output1/Input2) ERB2/ELB3 (Output2/Input3) ERB3/ELB (Output3/Input) ERB(Output) Notes: (1) HL=HIGH (ELB=input, ERB=output). urrent DN8080G s ERB output must be connected to the next DN8080G s ELB input. (2) When in -bit parallel interface mode: n=20. (3) When in 1-bit serial interface mode: n=80. Fig.20 Timing diagram for Power Down function ep 29 2 of 0 data sheet (v6)

25 DN8080G 11 OPERATION TIMING DIAGRAM bit parallel mode interface (EGMENT driver) WHEN HL=LOW L2 D1_ID D2_DL D3_DM ERB (Input) ELB (Output) L Fig.21 When HL=LOW WHEN HL=HIGH L2 D1_ID D2_DL D3_DM ELB (Input) ERB (Output) L Fig.22 When HL=HIGH 2005 ep of 0 data sheet (v6)

26 DN8080G bit serial mode interface (EGMENT driver) WHEN HL=LOW L D1_ID ERB (Input) ELB (Output) L Fig.23 HL=LOW, 1-bit serial mode interface WHEN HL=HIGH L2 D1_ID ELB (Input) ERB (Output) L Fig.2 HL=HIGH, 1-bit serial mode interface ep of 0 data sheet (v6)

27 DN8080G 11.3 ingle type interface mode (OMMON driver) WHEN HL=LOW L1 D2_DL OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA9 OM_DATA80 OMMON area of current driver Fig.25 HL=LOW, single-type interface mode WHEN HL=HIGH L1 D2_DL OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA9 OM_DATA80 OMMON area of current driver Fig.26 HL=HIGH, single-type interface mode ep 29 2 of 0 data sheet (v6)

28 DN8080G 11. Dual type interface mode (OMMON driver) WHEN HL=LOW L1 D2_DL D3_DM OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA39 OM_DATA0 OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA9 OM_DATA Fig.2 HL=LOW, dual-type interface mode WHEN HL=HIGH L1 D2_DL D3_DM OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA39 OM_DATA0 OM_DATA1 OM_DATA2 OM_DATA3 OM_DATA9 OM_DATA80 Fig.28 HL=HIGH, dual-type interface mode ep of 0 data sheet (v6)

29 DN8080G 11.5 OMMON/EGMENT driver timing (1/200 duty) L1 LATHED DATA(EG) M OM_DATA1 OM_DATA199 OM_DATA200 OM1 OM199 V0 V1 V V5 V0 V1 V V5 V0 V1 OM200 V V5 EG_DATA1 V0 V1 V2 EG1 V3 V V5 L L1 D1~D Lathced data M Enable Out Fig.29 OMMON/EGMENT driver timing( 1/200 duty) ep of 0 data sheet (v6)

30 DN8080G 12 APPLIATION DIAGRAM bit parallel interface mode (80-outputs EGMENT driver) LOWER VIEW (HL=LOW, AM=LOW) LD PANEL n n ERB AM HL ELB D1_ID ~ ERB AM HL ELB D1_ID ~ ERB AM HL ELB D1_ID ~ -bit parallel data input Fig.30 Lower view (HL=LOW, AM=LOW) UPPER VIEW (HL=HIGH, AM=LOW) -bit parallel data input D1_ID ~ ELB 1 HL AM ERB 80 D1_ID ~ HL AM ELB ERB 1 80 ELB 1 D1_ID ~ HL AM ERB n n+9 LD PANEL Fig.31 Upper view (HL=HIGH, AM=LOW) ep of 0 data sheet (v6)

31 DN8080G bit serial interface mode (80-outputs EGMENT driver) LOWER VIEW (HL=LOW, AM=HIGH) LD PANEL n n ERB AM HL ELB D2_DL~ D1_ID ERB AM HL D1_ID ELB D2_DL~ ERB AM HL ELB D2_DL~ D1_ID 1-bit serial data input Fig.32 Lower view (HL=L, AM=H) UPPER VIEW (HL=HIGH, AM=HIGH) 1-bit serial data input D2_DL~ ELB 1 D1_ID HL AM ERB 80 D2_DL~ ELB 1 D1_ID HL AM ERB 80 D2_DL~ ELB 1 D1_ID HL AM ERB n n+9 LD PANEL Fig.33 Upper view (HL=HIGH, AM=HIGH) ep of 0 data sheet (v6)

32 DN8080G 12.3 ingle type interface mode (80-outputs OMMON driver) input data (OMMON scan pulse) 80 1 AM HL D2_DL 1 80 LD PANEL AM HL D2_DL AM HL D2_DL 1 20 Fig.3 ingle-type interface mode (80-outputs OMMON driver) ep of 0 data sheet (v6)

33 DN8080G 12. Dual type interface mode (0-outputs + 0-outputs OMMON driver) input data 1 (OMMON scan pulse) 80 1 AM HL D2_DL 1 80 AM HL D2_DL LD PANEL (1/2) input data 2 (OMMON scan pulse) Note: in this mode (dual-type OMMON mode), duty ratio can be reduced to half. In this example, 1/200 duty can be used to drive 00 OMMON LD panel. D3_DM AM HL D2_DL AM HL D2_DL LD PANEL (2/2) AM HL D2_DL 1 00 Fig.35 Dual-type interface mode (0-outputs + 0-outputs OMMON driver) ep of 0 data sheet (v6)

34 DN8080G 12.5 Typical application circuit V0 R V1 R (n-)r R R V2 V3 V V5 V0-V5 D1_ID_ DIPOFFB L1 M L2 ELB ERB AM DN8080G HL V0-V5 D1_ID_ DIPOFFB L1 M L2 ELB ERB AM DN8080G HL 1 80 V0-V5 D1_ID_ DIPOFFB L1 M L2 ELB ERB AM DN8080G HL 1 80 EG1 - EG80 EG1 - EG80 EG1 - EG80 V VEE M DIPOFFB 80 DN8080G OM1 ~ OM80 AM 1 HL VO~V5 L1 D2_DL M DIPOFFB 80 OM1 AM DN8080G ~ OM80 HL 1 VO~V5 L1 D2_DL X 20 LD MODULE ontroller DIPOFFB FRAME(M) OM_DATA D1~~D L1 L2 M DIPOFFB 80 AM DN8080G HL 1 V0~V5 L1 D2_DL OM1 ~ OM Fig.36 Typical application circuit 2005 ep 29 3 of 0 data sheet (v6)

35 DN8080G 13 PIN IRUIT Table 15 MO-level schematics of all input, output, and I/O pins. YMBOL Input/ output IRUIT NOTE I/O V0 EN1 n V0, V12, V3, V5, 1~80 V12 V3 VEE VEE EN2 EN3 n= 1 ~ 80 V5 VEE EN VEE, M, DIPOFFB, HL, AM, L1 Input V V L2, D1_ID, D3_DM Input EN V V 2005 ep of 0 data sheet (v6)

36 DN8080G YMBOL Input/ output IRUIT NOTE ELB, ERB I/O EN V Data V Enable V D2_DL, I/O V Data V Enable V 2005 ep of 0 data sheet (v6)

37 DN8080G 1 APPLIATION NOTE Application information is provided in another document. Please contact Avant Electronics for application information ep 29 3 of 0 data sheet (v6)

38 TN LD Driver data sheet (v6) DN8080G DN8080G LQFP100 Package Outline Drawing 15 PAKAGE INFORMATION 2005 ep 29 38

39 TN LD Driver data sheet (v6) DN8080G 16 OLDERING 16.1 Introduction There is no soldering method that is ideal for all I packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted Is, or for printed-circuits with high components densities. In these situations reflow soldering is often recommended. This text gives a very brief description to a complex technology. A more in-depth description of soldering Is can be provided to our customers upon request Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages ( leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, please contact Avant for drypack information. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. everal techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds, depending on heating method. Typical reflow temperatures range from 215 to 250. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 5 minutes at Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The footprint must be at an angle of 5 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer, or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 within 6 seconds. Typical dwelling time is seconds at 250. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16. Repairing soldered joints Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 2 V) applied to the flat part of the lead. ontact time must be limited to 10 seconds at up to 300. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 20 and ep 29 39

40 TN LD Driver data sheet (v6) DN8080G 1 LIFE UPPORT APPLIATION These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Avant customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Avant for any damages resulting from such improper use or sale. With collaboration of ep 29 0