UTC UNISONIC TECHNOLOGIES CO., LTD. 1 PROGRAMMABLE TIMER DESCRIPTION FEATURES PIN CONFIGURATION VDD B A N.C.

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1 PROGRAMMABLE TIMER DESCRIPTION The UTC CD4541 programmable timer comprise a 1-stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, output control logic, and a special power-on reset circuit. The counter divides the oscillator frequency by any of 4 digitally controlled division ratios. SOP-14 FEATURES *Operates at 2 n frequency divider or as single traition timer *Increments on positive edge clock traitio *Wide supply voltage range: 3.0 ~ 15 *Built-in low power RC oscillator *Oscillator frequency range ~ DC to 100 khz *External clock applied to Pin 3 can be used itead of oscillator *Available division ratios 2 8, 2 10, 2 13, or 2 1 *High noise immunity: 0.45 DD (typ.) *Master reset totally independent of automatic reset operation *Automatic reset initializes all counters when power tur on */ select provides output logic level flexibility *High output drive min. one TTL load *Maximum input leakage 1A at 15 over full temperature range DIP-14 *Pb-free plating product number: CD4541L PIN CONFIGURATION Rtc Ctc N.C. AR MR ss DD B A N.C. / SELECT UTC UNISONIC TECHNOLOGIES CO., LTD. 1

2 TRUTH TABLE PIN STATE Auto Reset Operating Auto Reset Disabled Timer Operational Master Reset On 9 Output Initially Low after Reset Output Initially High after Reset 10 Single Cycle Mode Recycle Mode DIISION RATIO TABLE Number of Counter Stages Count A B n 2 n BLOCK DIAGRAM A 12 B 13 Rtc 1 Ctc 2 3 OSC C 8-STAGE COUNTER C B-STAGE COUNTER 1 OF 3 MUX 8 AUTO 5 DD=Pin 14 ss=pin 7 POWER-ON MASTER 10 9 / SELECT UTC UNISONIC TECHNOLOGIES CO., LTD. 2

3 ABSOLUTE MAXIMUM RATINGS (Note 1, 2) PARAMETER SYMBOL RATINGS UNIT Supply oltage DD -0.5 ~ +18 Input oltage IN -0.5 ~ DD +0.5 Power Dissipation DIP P D SOP mw Lead Temperature (soldering, 10 seconds) T L 20 Storage Temperature Range T stg -5 ~ +150 RECOMMENDED OPERATING CONDITIONS (Note 2) PARAMETER SYMBOL RATINGS UNIT Supply oltage DD 3 ~ 15 Input oltage IN 0 ~ DD Operating Temperature Range T opr -40 ~ +85 Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditio for actual device operation. Note 2: SS =0 unless otherwise specified. DC ELECTRICAL CHARACTERISTICS (Note 2, Ta=25, unless otherwise noted.) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT uiescent Device Current LOW Level Output oltage HIGH Level Output oltage LOW Level Input oltage HIGH Level Input oltage LOW Level Output Current (Note 3) HIGH Level Output Current (Note 3) Input Current I DD OL OH IL IH I OL IOH Note 3: IOH and IOL are tested one output at a time. IIN, IN = DD or ss DD =10, IN = DD or ss, IN = DD or ss DD =10, I I O I<1A DD =10, I I O I<1A, o=0.5 or 4.5 DD =10, o=1.0 or 9.0, o=1.5 or 13.5, o=0.5 or 4.5 DD=10, o=1.0 or 9.0, o=1.5 or 13.5, o=0.4 DD =10, o=0.5, o=1.5, o=2.5 DD =10, o=9.5, o=13.5, IN =0, IN = A ma ma A UTC UNISONIC TECHNOLOGIES CO., LTD. 3

4 AC ELECTRICAL CHARACTERISTICS (Note 4, Ta=25, CL=50pF (refer to test circuits)) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Output Rise Time Output Fall Time Turn-Off, Turn-On Propagation Delay, Clock to (2 8 Output) Turn-On, Turn-Off Propagation Delay, Clock to (2 1 Output) Clock Pulse Width Clock Pulse Frequency MR Pulse Width t TLH DD =10 t THL DD =10 t PLH, t PHL DD =10 t PHL, t PLH DD =10 t WH(CL) DD =10 f CL DD =10 t WH(R) DD = Average Input Capacitance C I Any Input pf Power Dissipation Capacitance (Note 5) C PD 100 pf Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power coumption of any CMOS device s s MHz UTC UNISONIC TECHNOLOGIES CO., LTD. 4

5 OPERATING CHARACTERISTICS With Auto Reset pin set to a 0 the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a 1. Both types of reset will result in synchronously resetting all counter stages independent of counter state. The RC oscillator frequency is determined by the external RC network, i.e.: 1 f= if (1 khzf 100kHz) 2.3 RtcCtc and RS ~ 2 Rtc where RS10 k The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (2 8, 2 10, 2 13, and 2 1 ). The 2 n counts as shown in the Division Ratio Table represent the output of the Nth stage of the counter. When A is 1, 2 1 is selected for both states of B. However, when B is 0, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 2 8 ). The / select output control pin provides for a choice of output level. When the counter is in a reset condition and / select pin is set to a 0 the output is a 0. Correspondingly, when / select pin is set to a 1 the output is a 1. When the mode control pin is set to a 1, the selected count is continually tramitted to the output. But, with mode pin 0 and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after 2 n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2 n-1 counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. RC Oscillator Frequency as a Function of R TC and C RC Oscillator Frequency as a Function of R TC and C 1.0M 70 DD =10 DD =10 DSCILLATORFREUENCY,f (khz) 100k 10k DSCILLATORFREUENCY,f (khz) k k 10k 100k 1.0M RESISTANCE, RTC ( K ) f as a function of C and (R TC =5K, =120k ) CAPACITANCE,C (µf) f as a function of R TC and (C=100pF, =2 R TC ) UTC UNISONIC TECHNOLOGIES CO., LTD. 5

6 Oscillator Circuit Using RC Configuration 3 TO CLOCK CIRCUIT INTERNAL RS CTC 2 1 RTC TEST CIRCUIT AND WAEFORMS Power Dissipation Test Circuit and Waveforms DD PULSE GENERATOR AR / SELECT A B MR C L SS (R tc and Ctc outputs are left open ) t WH (CL) % 10% DUTY CYCLE UTC UNISONIC TECHNOLOGIES CO., LTD.

7 Switching Tim e Test Circuit and W aveform s DD PULSE GENERATOR AR / SELECT A B MR C L SS tw H (CL) % 10% tplh tphl 90% 10% ttlh tthl UTC assumes no respoibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specificatio of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written coent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UTC UNISONIC TECHNOLOGIES CO., LTD. 7