MAR. 15, 2004 Version 1.8

Transcription

1 SPLC5C 32 x 65 Dot Matrix LCD Driver MAR. 5, 24 Version.8 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specificatio before placing your order. No respoibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.

2 SPLC5C Table of Contents PAGE. GENERAL DESCRIPTION FEATURES BLOCK DIAGRAM SIGNAL DESCRIPTIONS POWER SUPPLY PINS LCD POWER SUPPLY CIRCUIT TERMINALS SYSTEM BUS CONNECTION TERMINALS LIQUID CRYSTAL DRIVE TERMINALS TEST TERMINALS FUNCTIONAL DESCRIPTIONS THE MPU INTERFACE THE CHIP SELECT ACCESSING THE DISPLAY DATA RAM AND THE INTERNAL REGISTERS THE BUSY FLAG DISPLAY DATA RAM THE DISPLAY DATA LATCH CIRCUIT THE OSCILLATOR CIRCUIT THE COMMON OUTPUT STATUS SELECT DISPLAY TIMING GENERATOR CIRCUIT THE LIQUID CRYSTAL DRIVER CIRCUITS THE POWER SUPPLY CIRCUITS HIGH POWER MODE THE INTERNAL POWER SUPPLY SHUTDOWN COMMAND SEQUENCE REFERENCE CIRCUIT EXAMPLES THE RESET CIRCUIT COMMANDS DISPLAY ON/OFF DISPLAY START LINE SET PAGE ADDRESS SET COLUMN ADDRESS SET STATUS READ DISPLAY DATA WRITE DISPLAY DATA READ For NEWHAVENGARY Use Only 6.8. ADC SELECT (SEGMENT DRIVER DIRECTION SELECT) DISPLAY NORMAL/REVERSE DISPLAY ALL POINTS ON/OFF LCD BIAS SET READ/MODIFY/WRITE END RESET COMMON OUTPUT MODE SELECT POWER CONTROLLER SET MAR. 5, 24

3 SPLC5C 6.7. V 5 VOLTAGE REGULATOR INTERNAL RESISTOR RATIO SET THE ELECTRONIC VOLUME (DOUBLE BYTE COMMAND) STATIC INDICATOR (DOUBLE BYTE COMMAND) PAGE BLINKING (DOUBLE BYTE COMMAND) SET DRIVING MODE (DOUBLE BYTE COMMAND) POWER SAVE (COMPOUND COMMAND) NOP TEST TABLE 3 TABLE OF SPLC5C COMMANDS COMMAND DESCRIPTION INSTRUCTION SETUP: REFERENCE (REFERENCE) PRECAUTIONS ON TURNING OFF THE POWER ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS DC CHARACTERISTICS DISPLAY PATTERN OFF DISPLAY PATTERN CHECKER DISPLAY PATTERN CHECKER TIMING CHARACTERISTICS THE MPU INTERFACE (REFERENCE EXAMPLES) CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE) CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) VLCD VOLTAGE (VOLTAGE BETWEEN TO V 5 ) RELATIONSHIP OF V 5 VOLTAGE REGULATOR INTERNAL RESISTOR RATIO REGISTER AND ELECTRONIC VOLUME CONTROL REGISTER PACKAGE/PAD LOCATIONS PAD ASSIGNMENT AND LOCATIONS ORDERING INFORMATION DISCLAIMER REVISION HISTORY For NEWHAVENGARY Use Only 3 MAR. 5, 24

4 SPLC5C 32 x 65 DOT MATRIX LCD DRIVER. GENERAL DESCRIPTION The SPLC5C, a singlechip dot matrix liquid crystal display drivers, is specially designed to connect directly with a microprocessor bus. The 8bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM. It generates a liquid crystal drive signal independent of the microprocessor. Since the SPLC5C contai a 65 X 32 bits of display data RAM, a to correspondence between the liquid crystal panel pixels and the internal RAM bits, it is able to enable displays with a high degree of flexibility. The SPLC5C contai 65 common output circuits, 32 segment output circuits and therefore, a single chip can drive a 65 X 32 dot display (capable of displaying 8 colum X 4 rows of a 6 X 6 dot kanji font). In addition, the capacity of the display can also be extended through the use of master/slave structures between chips. The chips can save a great amount of power because no external operating clock is required for the display data RAM to read and write These chips not designed for resistance to light or Resistance to radiation. Highspeed 8bit MPU interface (capability to be connected directly to the both the 8 X 86 series MPUs and the 68 series MPUs)/Serial interface are supported. Wide range of operating temperatures. CMOS process CR oscillator circuit equipped internally (External clock can also be input). Abundant command functio Display data Read/Write, display ON/OFF, Normal/Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V 5 voltage regulation internal resistor ratio set. operatio. Since each chip is equipped internally with a Lowpower liquid crystal display power supply circuit equipped lowpower liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock CR oscillator circuit, the SPLC5C can be used for creating the lowest power display system with the fewest components for high performance portable devices. internally. Booster circuit (with Boost ratios of Double/Triple/Quad, where the stepup voltage reference power supply can be input externally). Highaccuracy voltage adjustment circuit (Thermal gradient.5%/ or external input). V 5 voltage regulator resistors equipped internally, 2. FEATURES Direct display of RAM data through the display data RAM. : Nonilluminated. : Illuminated. RAM capacity. 65 X 32 = 858 bits. Display driver circuits. SPLC5C: 65 common outputs and 32 segment outputs. Static drive circuit equipped internally for indicators. ( system, with variable flashing speed.) For NEWHAVENGARY Use Only V 4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. Driving Mode register provided for different size panel loading. Extremely low power coumption. Low operating power when the builtin power supply is used Power supply Operable on the low 2.4 voltage Logic power supply VSS = 2.4V to 5.5V Boost reference voltage: VSS2 = 2.4V to 6.V Liquid crystal drive power supply: V 5 = 4.5V to 2V Product Name Duty Bias SEG Dr COM Dr VREG Temperature Gradient Shipping Forms SPLC5C /65 /9, / %/ Bare Chip with Gold Bump 4 MAR. 5, 24

5 SPLC5C 3. BLOCK DIAGRAM VSS V V 2 V 3 V 4 V 5 CAPP CAPN CAP2P CAP2N CAP3N V OUT VSS2 V R V RS IRS HPM REF I/O buffer SEG SEG3 COM COM63 COMS SEG Drivers COM Drivers COMS COM output status select circuit Power supply circuit Page address circuit Display data latch circuit Display data RAM 32 X 65 Column address circuit Line address circuit Display timing generation circuit Oscillator circuit FRS FR CL DOF MS CLS Bus holder For NEWHAVENGARY Use Only CS CS2 AP (EP) RD (RWP) WR Command decoder PS MPU interface RESET D7(SI) D6(SCL) Status D5 D4 D3 D2 D D 5 MAR. 5, 24

6 SPLC5C 4. SIGNAL DESCRIPTIONS 4.. Power Supply PINs Mnemonic PIN No. Type Description 2 P Shared with MPU power supply terminal VCC VSS P V terminal connected to the system GND. VSS2 4 P A reference power supply for the stepup voltage circuit for the liquid crystal drive V RS P The externalinput V REG power supply for the LCD power supply voltage regulator. These can only be enabled for the models with the V REG external input option. V, V 2, V 3, V 4, P A multilevel power supply for the liquid crystal drive. The voltage applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through V 5 changing the impedance using an op. amp. Voltage levels are determined based on, and must maintain the relative magnitudes shown below. (= V ) V V 2 V 3 V 4 V 5 Master operation: When the power supply tur ON, the internal power supply circuits generate the V to V 4 voltages shown below. The voltage settings are selected by the LCD bias command. SPLC5C V /9.V5 /7.V5 V2 2/9.V5 2/7.V5 V3 7/9.V5 5/7.V5 V4 8/9.V5 6/7.V5 P: Power Supply 4.2. LCD Power Supply Circuit Terminals Mnemonic PIN No. Type Description CAPP 2 O DC/DC voltage converter. A capacitor is connected between this terminal and the CAPN terminal. CAPN 2 O DC/DC voltage converter. A capacitor is connected between this terminal and the CAPP terminal. CAP2P 2 O DC/DC voltage converter. A capacitor is connected between this terminal and the CAP2N terminal. CAP2N 2 O DC/DC voltage converter. A capacitor is connected between this terminal and the CAP2P terminal. CAP3N 2 O DC/DC voltage converter. A capacitor is connected between this terminal and the CAPP terminal. V OUT 3 O DC/DC voltage converter. A capacitor is connected between this terminal and VSS. For NEWHAVENGARY Use Only V R 2 I Output voltage regulator terminal. Provides the voltage between and V 5 through a resistive voltage divider. These are only enabled when the V 5 voltage regulator internal resistors are not used (IRS = L ). These cannot be used when the V 5 voltage regulator internal resistors are used (IRS = H ). 6 MAR. 5, 24

7 SPLC5C 4.3. System Bus Connection Terminals Mnemonic PIN No. Type Description DB7 (SI) (SCL) 8 I/O This is an 8bit bidirectional data bus that connects to an 8bit or 6bit standard MPU data bus. When the serial interface is selected (PS = L ), DB7 serves as the serial data input terminal (SI) and DB6 serves as the serial clock input terminal (SCL). At the same time, DB5 are set to high impedance. When the chip select is inactive, DB to DB7 are set to high impedance. AP I This is connected to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. AP = H : Indicates DB7 is display data. AP = L : Indicates DB7 is control data. RESET I When RESET is set to L, the settings are initialized. The RESET signal level performs the reset operation. CS 2 I This is the chip select signal. When CS = L and CS2 = H, the chip select becomes active, CS2 and data/command I/O is enabled. RD (EP) I When connected to an 88 MPU, this is LOW active. This pin is connected to the RD signal of the 88 MPU, and the SPLC5C data bus is in an output status when this signal is L. When connected to a 68 Series MPU, this is HIGH active. This is the 68 Series MPU enable clock input terminal. WR (RWP) I When connected to an 88 MPU, this is LOW active. This terminal connects to the 88 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. When connected to a 68 Series MPU: This is the read/write control signal input terminal. When RWP = H : Read. When RWP = L : Write. C86 I This is the MPU interface switch terminal. C86 = H : 68 Series MPU interface. C86 = L : 88 MPU interface. PS I This is the parallel data input/serial data input switch terminal. PS = H : Parallel data input. PS = L : Serial data input. The following applies depending on the PS status: PS Data/Command Data Read/Write Serial Clock 'H' AP DB to DB7 RD, WR Write only SCL (DB6) 'L' AP SI(DB7) When PS = L, DB to DB5 are high impedance. DB to DB5 may be H, L or Open. RD (EP) and WR (RWP) are fixed to either H or L. With serial data input, RAM display data reading is not supported. CLS I Terminal to select whether to enable or disable the display clock internal oscillator circuit. CLS = H : Internal oscillator circuit is enabled. CLS = L : Internal oscillator circuit is disabled (requires external input). When CLS = L, input the display clock through the CL terminal. FR I/O This is the liquid crystal alternating current signal I/O terminal. MS = H : Output MS = L : Input When the SPLC5C chip is used in master/slave mode, the various FR terminals must be connected. For NEWHAVENGARY Use Only 7 MAR. 5, 24

8 SPLC5C Mnemonic PIN No. Type Description MS I This terminal selects the master/slave operation for the SPLC5C chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. MS = H : Master operation MS = L : Slave operation The following is true depending on the MS and CLS status: MS CLS Oscillator Circuit Power Supply Circuit CL FR FRS DOF 'H' 'H' Enabled Enabled Output Output Output Output 'L' Disabled Enabled Input Output Output Output 'L' 'H' Disabled Disabled Input Input Output Input 'L' Disabled Disabled Input Input Output Input CL I/O This is the display clock input terminal The following is true depending on the MS and CLS status. MS CLS CL 'H' 'L' 'H' 'L' 'H' 'L' Output Input Input Input When the SPLC5C chips are used in master/slave mode, the various CL terminals must be connected. DOF I/O This is the liquid crystal display blanking control terminal. MS = H : Output MS = L : Input When the SPLC5C chip is used in master/slave mode, the various DOF terminals must be connected. FRS O This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON when in master operation mode, and is used in conjunction with the FR terminal. IRS O This terminal selects the resistors for the V5 voltage level adjustment. IRS = H : Use the internal resistors. IRS = L : Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal. This pin is enabled only when the master operation mode is selected. It is fixed to either H or L when the slave operation mode is selected. HPM I This is the power control terminal for the power supply circuit for liquid crystal drive. HPM = H : Normal mode. HPM = L : High power mode. This pin is enabled only when the master operation mode is selected. It is fixed to either H or L when the slave operation mode is selected. REF I This is the reference source select terminal for the power supply circuit for liquid crystal drive. REF = H ; external reference source from VRS terminal. REF = L ; internal reference source from SPLC5C terminal. This pin is enable only when the master operation mode is selected. It is fixed to either H or L when the slave operation mode is selected. For NEWHAVENGARY Use Only 8 MAR. 5, 24

9 SPLC5C 4.4. Liquid Crystal Drive terminals Mnemonic PIN No. Type Description SEG3 32 O These are the liquid crystal segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from, V2, V3, and V5. RAM DATA FR Normal Display Output Voltage Reverse Display H H V2 H L V5 V3 L H V2 L L V3 V5 Power save COM63 64 O These are the liquid crystal common drive outputs. Part No. COM SPLC5C COM63 Through a combination of the contents of the scan data and with the FR signal, a single level is selected from, V, V 4, and V 5. Scan Data FR Output Voltage H H V 5 H L L H V L L Power Save COMS 2 O These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these pi open if they are not used. When in master/slave mode, the same signal is output by both master and slave Test Terminals Mnemonic PIN No. Type Description TEST I This is terminal for IC chip testing only. TEST3, TEST4 2 I These are terminals for IC chip testing only. TEST5, TEST6 2 O These are terminals for IC chip testing only. For NEWHAVENGARY Use Only V 4 9 MAR. 5, 24

10 SPLC5C 5. FUNCTIONAL DESCRIPTIONS 5.. The MPU Interface 5... Selecting the interface type For SPLC5C, data trafers are accomplished through an 8bit bidirectional data bus (DB7 ) or through a serial data input (SI). By selecting the PS terminal polarity to the H or L, it is possible to select either parallel data input or serial data input as shown in Table. Table PS CS CS2 AP RD WR C86 DB7 DB6 DB5 H: Parallel Input CS L: Serial Input CS CS2 AP RD WR C86 DB7 DB6 DB5 CS2 AP SI SCL (HiZ) indicates fixed to either H or to L The parallel interface When the parallel interface is selected (PS = H ), it is possible to connect directly to either an 88system MPU or a 68 Series MPU (as shown in Table 2) by selecting the C86 terminal to either H or L. Table 2 C86 CS CS2 AP RD WR DB7 H: 68 Series MPU Bus CS CS2 AP EP RWP DB7 L: 88 MPU Bus CS CS2 AP RD WR DB7 Data bus signals are recognized by a combination of AP, RD (EP), WR (RWP) signals, shown in Table 3. Table 3 Shared 68 Series 88 Series AP WRP RD WR Function Read the display data Write the display data Read Status Write control data (command) The serial interface When the serial interface is selected (PS = L ) and when the chip is in active state ( CS= L and CS2 = H ), the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin at the rising edge of the serial clocks DB7, DB6 through DB in order. The data is converted to The AP input determines whether the serial data input is display data or command data; when AP = H, the data is display data, and when AP = L, the data is command data. The AP input is read and used for detecting every 8th rising edge of the serial clock after the chip is active. 8bit parallel data at the rising edge of the eighth serial clock. For NEWHAVENGARY Use Only MAR. 5, 24

11 SPLC5C CS CS2 SI DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB7 DB6 DB5 DB4 DB3 DB2 SCL AP Figure : serial interface signal chart. Note: When the chip is not active, the shift registers and counter are reset to their initial states. Note2: Reading is not acceptable in serial interface mode. Note3: Caution is required on the SCL signal when it comes to lineend reflectio and external noise. SUNPLUS recommends that operation should be rechecked on the actual equipment The Chip Select The SPLC5C have two chipselectterminals: CS and CS2. The MPU interface or the serial interface is enabled only when MPU WR DATA Writing N N+ N+2 N+3 CS = L and CS2 = H. Internal Timing BUS Holder Write Signal Latch N N+ N+2 N+3 When the chip select is inactive, DB7 enter into a high impedance state, and the AP, RD, and WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset Accessing the Display Data RAM and the Internal Registers Data traferring at a high speed is eured since the MPU is required to satisfy the cycle time (tcyc) requirement alone in accessing the SPLC5C. Wait time may not be coidered. Also, in SPLC5C chips, each time data is sent from MPU. A type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Note that data of the specified address is not generated by the read itruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy read is required whenever the addresses setup or write cycle operation is conducted. This relatiohip is shown in Figure 2. For NEWHAVENGARY Use Only INternal Timing MPU Reading WR RD DATA N N n n+ Address Preset Read Signal Column Address Preset N Increment N+ N+2 Bus Holder N n n+ n+2 Address Set Dummy Data Read Data Read #n Read #n #n+ Figure The Busy Flag When the busy flag is, it indicates that the SPLC5C is running internal processes. At this moment, no command aside from a status read will be received. The busy flag is outputted to DB7 pin with the read itruction. If the cycle time (tcyc) is remained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. MAR. 5, 24

12 SPLC5C 5.5. Display Data RAM Display data RAM The display data RAM is a RAM that stores the dot data for the display. It has a 65 (8 page x 8 bit +) x 32bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the DB7 display data from the MPU corresponds to the liquid crystal display common direction, there are few cotraints at the time of display data trafer when multiple SPLC5C chips are used. Therefore, display structures can be created easily and with a high degree of freedom. D D D2 D3 D4 Display data RAM Figure 3 Moreover, reading from and writing to the display RAM in the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Coequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering) The page address circuit As shown in Figure 4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (DB3, DB2, DB, DB =,,, ) is the page for the RAM region used only by the indicators, and only display data DB is used The column addresses COM COM COM2 COM3 COM4 Liquid crystal display As is shown in Figure 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the increment of column addresses stops with 83H. Because the column address depends on the page address, it is necessary to respecify both the page address and the column address when moving, for example, from page column 83H to page column H. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the For NEWHAVENGARY Use Only relatiohip between the display data RAM column address and the segment output. Because of this, the cotraints on the IC layout when the LCD module is assembled can be minimized. Table 4 SEG Output SEG SEG3 ADC (DB) (H) Column Address 83(H) 83(H) Column Address (H) The line address circuit The line address circuit, as shown in Figure 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, which is normally the top line of the display can be specified. This is the COM output when the common output mode is normal and the COM63 output for SPLC5C when the common output mode is reversed. The display area is a 65line area for the SPLC5C from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed. Page Address D3 D2 D D Data D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D D D2 D3 D4 D5 D6 D7 D SEG 83 SEG 82 SEG2 8 2 SEG3 8 3 SEG4 7F 4 SEG5 7E 5 SEG6 7D 6 SEG7 7C 7 Page Page Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 Figure 4 2 MAR. 5, 24 7C 7 7D 6 7E 5 7F SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 Line Address H H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH H H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 2H 2H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 3H 3H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH D D ADC LCD Out When the common output mode is normal Column Address COM Output COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM2 COM2 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM3 COM3 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM4 COM4 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM5 COM5 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM6 COM6 COM62 COM63 CMOS Regardless of the display start line address, the SPLC5A access 65th line

13 SPLC5C 5.6. The Display Data Latch Circuit The display data latch circuit temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. Table 5 Status Normal Reverse COM Scan Direction SPLC5C COM COM63 COM63 COM 5.7. The Oscillator Circuit This is a CRtype oscillator that produces the display clock. The oscillator circuit is only enabled when MS = H and CLS = H. When CLS = L, the oscillation stops, and the display clock is input through the CL terminal The Common Output Status Select In the SPLC5C chips, the COM output scan direction can be selected by the common output status select command (See Table 5.). Coequently, the cotraints in IC layout at the time of LCD module assembly can be minimized Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Coequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drivewave form using a 2frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. Twoframe alternating current drivewave form (SPLC5C) CL FR COM COM RAM DATA For NEWHAVENGARY Use Only V V 4 V 5 V V 4 V 5 V 2 SEGn V 3 V 5 Figure 5 3 MAR. 5, 24

14 SPLC5C When multiple SPLC5C chips are used, the slave chips must be supplied the display timing signals (FR, CL, DOF ) from the master chip(s). Table 6 shows the status of the FR, CL, and DOF signals. Table 6 Operating Mode FR CL DOF Master (MS = H ): The internal oscillator circuit is enabled (CLS = H ) The internal oscillator circuit is disabled (CLS = L ) Output Output Output Input Output Output Operating Mode FR CL DOF Slave (MS = L ): The internal oscillator circuit is enabled (CLS = H ) The internal oscillator circuit is disabled (CLS = L ) Input Input Input Input Input Input 5.. The Liquid Crystal Driver Circuits These are a 97channel (SPLC5C) that generates four voltage levels for driving the liquid crystal. The combination of the display data, the COM scan signals, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows examples of the SEG and COM output waveform. COM COM COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM COM COM2 COM3 COM4 COM5 For NEWHAVENGARY Use Only FR COM COM COM2 SEG SEG SEG2 COMSEG COMSEG VSS V V2 V3 V4 V5 V V2 V3 V4 V5 V V2 V3 V4 V5 V V2 V3 V4 V5 V V2 V3 V4 V5 V V2 V3 V4 V5 V5 V4 V3 V2 V V V V2 V3 V4 V5 V5 V4 V3 V2 V V V V2 V3 V4 V5 Figure 6 4 MAR. 5, 24

15 SPLC5C 5.. The Power Supply Circuits The power supply circuits are lowpower coumption power supply circuits that generate the voltage levels for the liquid crystal drivers. They comprise Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Coequently, it is possible to make an external power supply and the internal power supply function in parallel. Table 7 shows the Power Control Set Command 3bit data control functio, and Table 8 shows reference combinatio. Table 7 The Control Details of Each Bit of the Power Control Set Command Item Status '' '' DB2 Booster circuit control bit ON OFF DB Voltage regulator circuit (V regulator circuit) control bit ON OFF DB Voltage follower circuit (V/F circuit) control bit ON OFF Table 8 Reference Combinatio Use Settings DB DB DB Stepup V regulator V/F External Stepup Voltage circuit circuit circuit voltage input SystemTerminal Only the internal power supply is used O O O VSS2 Used Only the V regulator circuit and the V/F circuit are used X O O V OUT, VSS2 Open Only the V/F circuit is used X X O V 5, VSS2 Open Only the external power supply is used X X X V to V 5 Open Note: The stepup system terminals refer CAPP, CAPN, CAP2P, CAP2N, and CAP3N. Note2: While other combinatio, not shown above, are also possible, these combinatio are not recommended because they have no practical use The stepup voltage circuits Using the stepup voltage circuits equipped within the SPLC5C chips, it is possible to product a Quad stepup, a Triple stepup, and a Double stepup of the VSS2 voltage levels. Quad stepup: Connect capacitor C between CAPP and CAPN, between CAP2P and CAP2N, between CAPP and CAP3N, and between VSS2 and VOUT, to produce a voltage level in the negative direction at the VOUT terminal that is 4 times the voltage level between and VSS2. For NEWHAVENGARY Use Only Triple stepup: Connect capacitor C between CAPP and CAPN, between CAP2P and CAP2N and between VSS2 and VOUT, and short between CAP3N and VOUT to produce a voltage level in the negative direction at the VOUT terminal that is 3 times the voltage difference between and VSS2. Double stepup: Connect capacitor C between CAPP and CAPN, and between VSS2 and VOUT, leave CAP2P open, and short between CAP2N, CAP3N and VOUT to produce a voltage in the negative direction at the VOUT terminal that is twice the voltage between and VSS2. 5 MAR. 5, 24

16 SPLC5C The stepup voltage relatiohips are shown in Figure 7. + C VSS2 VOUT VSS2 + + C C VOUT VSS2 VOUT C + C CAP3N CAPP CAPN SPLC5C + C CAP3N CAPP CAPN SPLC5C + C CAP3N CAPP CAPN SPLC5C CAP2N C C + CAP2P + CAP2N CAP2P OPEN CAP2N CAP2P 4 x stepup voltage circuit 3 x stepup voltage circuit 2 x stepup voltage circuit = V VSS2 = 3V VOUT = 4 x VSS2 = 2V = V VSS2 = 3V VOUT = 3 x VSS2 = 9V = V VSS2 = 5V VOUT=2 x VSS2 = V 4 x stepup voltage relatiohips 3 x stepup voltage relatiohips 2 x stepup voltage relatiohips Figure 7 Note: The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rate The voltage regulator circuit The stepup voltage generated at VOUT outputs the liquid crystal driver voltage V5 through the voltage regulator circuit. Because the SPLC5C chips have an internal highaccuracy fixed voltage power supply with a 64level electronic volume function and internal resistors for the V 5 voltage regulator, systems can be cotructed without having to include highaccuracy voltage regulator circuit components. Moreover, in the SPLC5C, two types of thermal gradients have been prepared as V REG optio: () approximately.5%/ and (2) external input (supplied to the VRS terminal) When the V 5 voltage regulator internal resistors are used For NEWHAVENGARY Use Only Through the use of the V 5 voltage regulator internal resistors and the electronic volume function, the liquid crystal power supply voltage, V 5, can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V 5 voltage can be calculated using equation A over the range where V 5 < V OUT. Rb V 5 = + VEN Ra Internal Ra Internal Rb Rb α = + Ra 62 VREG [ Q V EN = ( α 62) ] Equation A VREG Figure 8 VEN (cotant voltage supply + electronic volume) V REG is the ICinternal fixed voltage supply, and its voltage at T A = 25 is as shown in Table 9. V5 6 MAR. 5, 24

17 SPLC5C Table 9 Equipment Type Thermal Gradient Units VREG Units () Internal Power Supply.5 [%/ ] [V] (2) External Input VRS [V] α is set to level of 64 possible levels by the electronic volume function depending on the data set in the 6bit electronic volume register. Table shows the value for depending on the electronic volume register settings. Table DB5 DB4 DB3 DB2 DB DB α : : : : : : : When an external resistance is used (i.e., The V 5 Voltage Regulator Internal Resistors are not used) () The liquid crystal power supply voltage V 5 can also be set without using the V 5 voltage regulator internal resistors (IRS terminal = L ) by adding resistors Ra and Rb between and VR, and between VR and V 5, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V5 through commands. In the range where V 5 < V OUT, the V 5 voltage can be calculated using equation B based on the external resistance, Ra and Rb. Rb' V 5 = + VEN Ra' External resistor Ra' Rb' α = + Ra' 62 VREG [ Q V EN = ( α 62) ] Equation B VREG VEN (fixed voltage power supply + electronic volume) V5 Rb/Ra is the V 5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V 5 voltage regulator internal resistor ratio set command. The ( + Rb/Ra) ratio assumes the values shown in Table depending on the 3bit data settings in the V 5 voltage regulator internal resistor ratio register. V 5 voltage regulator internal resistance ratio register value and ( + Rb/Ra) ratio (Reference value) Table Register SPLC5C Equipment Type by Thermal Gradient [Units: %/ ] DB2 DB DB ().5 (2) VREG External Input For NEWHAVENGARY Use Only External resistor Rb' Figure 9 Setup example: When selecting T A = 25 and V5 = 7.V for an SPLC5C model where the temperature gradient =.5%/. When the central value of the electron volume register is (DB5, DB4, DB3, DB2, DB, DB) = (,,,,, ), then α = 3 and V REG = 2.V. According to equation B: Rb' V 5 = + VEN Ra' Rb' α 7.V = + ( 2.) Ra' 62 Equation B2 Moreover, when the value of the current running through Ra and Rb is set to 5µA, Ra' + Rb' =.4MΩ Equation B3 7 MAR. 5, 24

18 SPLC5C Coequently, by equatio B2 and B3, Rb' = 3.2 Ra' Ra' = 34kΩ Rb' = 6kΩ At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 2. Table 2 V 5 Min. Typ. Max. Units Variable [V] Range (63 levels) (central value) ( level) Notch width 52 [mv] When external resistors are used (i.e. The V5 Voltage Regulator Internal Resistors Are Not Used). (2) When the external resistor described above are used, adding a variable resistor makes it possible to perform fine adjustments on Ra and Rb, to set the liquid crystal drive voltage V 5. In this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage V 5 by commands to adjust the liquid crystal display brightness. In the range where V 5 < V OUT the V 5 voltage can be calculated by equation C below based on the R and R2 (variable resistor) and R3 settings, where R2 can be subjected to fine adjustments ( R2). V Ra' R + R R R + R = + VEN 2 R3 + R2 + R2 α = + (VREG) R R [ V = ( α 62) ] EN VREG Q Equation C External resistor R V EN (fixed voltage power supply + electronic volume) V 5 Rb' External resistor R 2 External resistor R 3 For NEWHAVENGARY Use Only R2 V R Figure 8 MAR. 5, 24

19 SPLC5C Setup example: When selecting T A = 25 and V 5 = 5.V to 9.V (using R2) for an SPLC5C model where the temperature gradient =.5%/. When the central value for the electronic volume register is set at (DB5, DB4, DB3, DB2, DB, DB) = (,,,,, ), α = 3 VREG = 2.V so, according to equation C, when R2 = Ω, in order to make V 5 = 9.V, R3 + R2 3 9.V = + (2.) R 62 Equation C2 When R2 = R2, in order to make V = 5.V, R3 3 5.V = + (2.) R R2 62 Equation C3 + Moreover, when the current flowing and V5 is set to 5µA, R + R2 + R3 =.4MΩ Equation C4 With this, according to equation C2, C3 and C4, R = 264kΩ R2 = 2kΩ R3 = 925kΩ At this time, the V5 voltage variable range and notch width based on the electron volume function is as shown in Table 3. Table 3 V 5 Min. Typ. Max. Units Variable Range (63 levels) (central value) ( level) [V] Notch width 53 [mv] Note: When the V 5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF. Note2: The VR terminal is enabled only when the V 5 voltage regulator internal resistors are not used (i.e. the IRS terminal = L ). When the V 5 voltage regulator internal resistors are used (i.e. when the IRS terminal = H ), the VR terminal is left open. For NEWHAVENGARY Use Only Note3: Because the input impedance of the VR terminal is high, it is necessary to take into coideration short leads, shield cables, etc. to handle noise The liquid crystal voltage generator circuit The V 5 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V, V 2, V 3, and V 4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V, V 2, V 3 and V 4 to the liquid crystal drive circuit. /9 bias or /7 bias for SPLC5C can be selected High Power Mode The power supply circuit equipped in the SPLC5C chips has very low power coumption (normal mode: HPM = H ). However, for LCDs or panels with large loads, this lowpower power supply may cause display quality to degrade. When this occurs, setting the HPM terminal to L (high power mode) can improve the quality of the display. We recommend that the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, it is necessary to add a liquid crystal drive power supply externally The Internal Power Supply Shutdown Command Sequence The sequence shown in Figure is recommended for shutting down the internal power supply. First place the power supply in power saver mode and then turn the power supply OFF. Sequence Step Step2 END Details (Command, status) Display OFF Display all points ON Internal power supply OFF Figure Command address D7 D6 D5 D4 D3 D2 D D Power saver commands (compound) 9 MAR. 5, 24

20 SPLC5C 5.4. Reference Circuit Examples Figure 2 shows reference circuit examples When using all of the stepup circuit, voltage regulating circuit and V/F circuit A. When the voltage regulator internal resistor is used. Example where VSS2 = VSS, with 4x stepup B. When the voltage regulator internal resistor is not used. Example where VSS2 = VSS, with 4x stepup IRS REF MS IRS REF MS VSS2 VSS2 C V OUT C V OUT VSS C C C V 5 SPLC5C VSS C C C R 3 CAP3 CAP+ CAP CAP2+ CAP2 CAP3 CAP+ CAP CAP2+ CAP2 V 5 SPLC5C R 2 V R V R C 2 C 2 C 2 V V 2 V 3 C 2 R C 2 C 2 C 2 C 2 V V 2 V 3 C 2 V 4 V 5 For NEWHAVENGARY Use Only Figure 2 C 2 V 4 V 5 2 MAR. 5, 24

21 SPLC5C When the voltage regulator circuit and V/F circuit alone are used A. When the V 5 voltage regulator internal resistor is not used. B. When the voltage regulator internal resistor is used. VSS External power supply R 3 R 2 R C2 C2 C2 C2 C2 IRS MS REF VSS2 VOUT CAP3N CAPP CAPN CAP2P CAP2N V5 VR V V2 V3 V4 V5 SPLC5C Figure 3 VSS External power supply C2 C2 C2 C2 C2 IRS REF VSS2 VOUT CAP3N CAPP CAPN CAP2P CAP2N V5 VR V V2 V3 V4 V5 MS SPLC5C For NEWHAVENGARY Use Only 2 MAR. 5, 24

22 SPLC5C C. When the V/F circuit alone are used. D. When the builtin power is not used. REF IRS MS REF IRS MS VSS2 VSS2 VSS External power supply VOUT CAP3N CAPP CAPN VSS VOUT CAP3N CAPP CAPN CAP2P CAP2P CAP2N V5 VR SPLC5C CAP2N V5 VR SPLC5C C2 V V C2 C2 C2 C2 V2 V3 V4 V5 Figure 4 External power supply V2 V3 V4 V5 For NEWHAVENGARY Use Only 22 MAR. 5, 24

23 SPLC5C 5.5. The Reset Circuit When the RESET input comes to the L level, these LSIs return to the default state. Their default states are as follows: ). Display OFF 2). Normal display 3). ADC select: Normal (ADC command DB = L ) 4). Power control register: (DB2, DB, DB) = (,, ) 5). Serial interface internal register data clear 6). LCD power supply bias rate: SPLC5C.../9 bias 7). Allindicator lampson OFF (Allindicator lamps ON/OFF command DB = L ) 8). Power saving clear 9). V 5 voltage regulator internal resistors, Ra and Rb, are connected. ). Output conditio of SEG and COM terminals SEG:, COM: ). Read modify write OFF 2). Static indicator OFF Static indicator register: (DB, DB2) = (, ) 3). Display start line set to first line 4). Column address set to Address 5). Page address set to Page 6). Common output status normal 7). V5 voltage regulator internal resistor ratio set mode clear 8). Electronic volume register set mode clear Electronic volume register: (DB5, DB4, DB3, DB2, DB, DB) = (,.,,, ) 9). Test mode clear 2). Driving mode register: (DB7, DB6)=(, ) On the other hand, when the reset command is used, only above default settings from to 9 are executed. When the power is turned on, the IC internal state becomes utable, and it is necessary to initialize it using the RESET terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control signal from the MPU is in the high For NEWHAVENGARY Use Only impedance, an overcurrent may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used on SPLC5C, it is necessary that RESET is H when the external liquid crystal power supply is turned on. This IC has the function to discharge V 5 when RESET is L, and the external power supply shortcircuits to when RESET is L.. While RESET is L, the oscillator and the display timing generator stop, and the CL, FR, FRS and DOF terminals are fixed to H. The terminals DB7 are not affected. The level is output from the SEG and COM output terminals. It mea that an internal resistor is connected between and V 5. When the internal liquid crystal power supply circuit is not used on other models of SPLC5C, it is necessary that RESET is L when the external liquid crystal power supply is turned on. While RESET is L, the oscillator works, but the display timing generator stops, and the CL, FR, FRS and DOF terminals are fixed to H. The terminals DB7 are not affected. 6. COMMANDS The SPLC5C chips identify the data bus signals by a combination of AP, RD (EP), WR (RWP) signals. Command interpretation and execution do not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 88 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low pulse to the WR terminal for writing. In the 68 Series MPU interface, the interface is placed in a read mode when a H signal is input to the RWP terminal. It is placed in a write mode when a L signal is input to the RWP terminal. Then, the command is launched by inputting a high pulse to the EP terminal (See. Timing Characteristics regarding the timing). Coequently, the 68 Series MPU interface is different from the 8x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read RD (EP) becomes (H). In the explanatio below, the commands are explained using the 88 Series MPU interface as the example. When the serial interface is selected, the data is inputted in the sequence starting from DB7. 23 MAR. 5, 24

24 SPLC5C <Explanation of Commands> 6.. Display ON/OFF This command tur the display ON and OFF. EP RWP AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB Setting Display ON Display OFF When the display OFF command is executed and when in the display all points ON mode, power saver mode is entered. See the section on the power saver for details Display Start Line Set This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details, see the explanation of this function in The Line Address Circuit. EP RWP AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB Line Address Page Address Set This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Changing the page address does not accompany a change in the status display. See the page address circuit in the Function Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. EP RWP Description (page 2) for the detail. AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB Page Address 2 7 For NEWHAVENGARY Use Only 8 24 MAR. 5, 24

25 SPLC5C 6.4. Column Address Set This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sectio (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically incremented (+), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See the function explanation in The Column Address Circuit for details. EP RWP Column AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB A7 A6 A5 A4 A3 A2 A A Address High bits A7 A6 A5 A4 Low bits A3 A2 A A Status Read EP RWP AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB BUSY ADC ON/OFF RESET BUSY When BUSY =, it indicates that either processing is occurring internally or a reset condition is in process. While the chip does not accept commands until BUSY =, if the cycle time can be satisfied, there is no need to check for BUSY condition. ADC This shows the relatiohip between the column address and the segment driver. : Reverse (column address 3n SEG n) : Normal (column address n SEG n) (The ADC command switches the polarity.) ON/OFF RESET ON/OFF: indicates the display ON/OFF state. : Display ON : Display OFF (This display ON/OFF command switches the polarity.) This indicates that the chip is in the process of initialization either because of a RESET signal or because of a reset command. : Operating state : Reset in progress For NEWHAVENGARY Use Only 25 MAR. 5, 24

26 SPLC5C 6.6. Display Data Write This command writes 8bit data to the specified display data RAM by one after the write, the MPU can write the display data. address. Since the column address is automatically incremented EP RWP AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB Write data 6.7. Display Data Read This command reads 8bit data from the specified display data after the column address being set. See the function explanation RAM address. Since the column address is automatically in Display Data RAM for the explanation of accessing the internal incremented by one after the read, the CPU can continuously read multipleword data. One dummy read is required immediately registers. When the serial interface is used, reading the display data becomes unavailable. EP RWP AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB Read Data 6.8. ADC Select (Segment Driver Direction Select) This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pi may be 2) for the detail. Increment of the column address (by ) accompanying the reading or writing the display data is done according to the column address indicated in Figure 4. reversed by the command. See the column address circuit (page EP RWP AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB Setting Normal Reverse 6.9. Display Normal/Reverse This command can reverse the lit and unlit display without done, the display data RAM contents are maintained. overwriting the contents of the display data RAM. When this is EP RWP AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB Setting RAM Data H LCD ON voltage (normal RAM Data L LCD ON voltage (reverse) For NEWHAVENGARY Use Only 26 MAR. 5, 24

27 SPLC5C 6.. Display All Points ON/OFF This command makes it possible to force all display points ON command takes priority over the display normal/reverse regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command. EP RWP AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB Setting Normal display mode Display all points ON When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For more details, see the Power Save Section. 6.. LCD Bias Set This command selects the voltage bias ratio for the liquid crystal display. EP RWP Select Status AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB SPLC5C /9 bias /7 bias 6.2. Read/Modify/Write This command is used paired with the END command. Once command is inputted, the column address retur to the address this command has been inputted, the display data read command at when the read/modify/write command was entered. This does not change the column address, but only the display data function makes it possible to reduce the load on the MPU when write command increment (+) the column address. This mode there is repeating data changes in a specified display region, such remai until the END command is inputted. When the END as when there is a blanking cursor. EP RWP AP RD WR DB7 DB6 DB5 DB4 DB3 DB2 DB DB Note: Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. However, the column address set command cannot be used. For NEWHAVENGARY Use Only 27 MAR. 5, 24