ILI9225G. a-si TFT LCD Single Chip Driver 176RGBx220 Resolution and 262K color. Specification Preliminary I LI TECHNOLOGY CORP.

Transcription

1 a-si TFT LC Single Chip river 76RGBx Resolution and 6K color Specification Preliminary Version: V6 ocument No: _S_V6pdf I LI TECHNOLOGY CORP 8F, No 38, Taiyuan St, Jhubei Cit y, Hsinchu Count y, Taiwan 3, R O C Tel ; Fax

2 Section Table of Contents Introduction 5 Features 5 3 Block iagram 7 4 Pin escriptions 8 5 Pad Arrangement and Coordination 3 6 Block escription 9 7 System Interface The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page of 7 Version: Page 7 Interface Specifications 7 Input Interfaces 7 8-bit System Interface bit System Interface bit System Interface bit System Interface 8 73 Serial Peripheral Interface (SPI) bit 4 wires Serial Peripherial Interface wire 9-bit Serial Interface wire 8-bit Serial Interface ata Transfer Recovery RGB Input Interface RGB Interface 4 74 RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface Interface Timing 48 8 Register escriptions 49 8 Registers Access 49 8 Instruction escriptions 53 8 Index (IR) 56 8 Chip I Code (Rh) river Output Control (Rh) LC riving Waveform Control (Rh) Entry Mode (R3h) 6 86 isplay Control (R7h) isplay Control (R8h) Frame Cycle Control (RBh) RGB Input Interface Control (RCh) 67

3 8 Oscillator Control (RFh) 68 8 Power Control (Rh) 69 8 Power Control (Rh) Power Control 3 (Rh) Power Control 4 (R3h) 7 85 Power Control 5 (R4h) 7 86 RAM Address Set (Rh, Rh) 7 87 Write ata to GRAM (Rh) 7 88 Read ata from GRAM (Rh) 7 89 Gate Scan Control (R3h) 73 8 Vertical Scroll Control (R3h, R3h) 74 8 Vertical Scroll Control (R33h) 74 8 Partial Screen riving Position (R34h, R35h) Horizontal and Vertical RAM Address Position (R36h/R37h, R38h/R39h) Gamma Control (R5h ~ R59h) NV Memory ata Programming (R6h) NV Memory Control (R6h) NV Memory Status (R6h) NV memory Protection Key (R63h) I Code (R65h, Read Only) SPI Read/Write Control (R66h, Write Only) 79 9 NV Memory Programming Flow 8 GRAM Address Map & Read/Write 8 Window Address Function 85 Gamma Correction 86 3 Application 3 3 Configuration of Power Supply Circuit 3 3 Voltage Generation 5 33 Power Supply Configuration 6 34 STB Mode 7 4 Electrical Characteristics 8 4 Absolute Maximum Ratings 8 4 C Characteristics 9 43 Reset Timing Characteristics 9 44 AC Characteristics 44 i8-system Interface Timing Characteristics 44 M68-System Interface Timing Characteristics 443 Serial ata Transfer Interface Timing Characteristics RGB Interface Timing Characteristics 4 The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page of 7 Version:

4 Figures FIGURE SYSTEM INTERFACE AN RGB INTERFACE CONNECTION FIGURE 8-BIT SYSTEM INTERFACE ATA FORMAT 3 FIGURE3 6-BIT SYSTEM INTERFACE ATA FORMAT 5 FIGURE4 I8 6/8-BIT SYSTEM INTERFACE TIMING 6 FIGURE5 M68 6/8-BIT SYSTEM INTERFACE TIMING 6 FIGURE6 9-BIT SYSTEM INTERFACE ATA FORMAT 7 FIGURE7 8-BIT SYSTEM INTERFACE ATA FORMAT 8 FIGURE8 ATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE 9 FIGURE9 ATA FORMAT OF SPI INTERFACE 3 FIGURE ATA TRANSMISSION THROUGH SPI, 65 COLOR 3 FIGURE ATA TRANSMISSION THROUGH SPI, 6K COLOR 33 FIGURE RGB INTERFACE ATA FORMAT 39 FIGURE3 GRAM ACCESS AREA BY RGB INTERFACE 4 FIGURE4 TIMING CHART OF SIGNALS IN 8-/6-BIT RGB INTERFACE MOE 4 FIGURE5 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MOE 4 FIGURE6 EXAMPLE OF UPATE THE STILL AN MOVING PICTURE 43 FIGURE7 INTERNAL CLOCK OPERATION/RGB INTERFACE MOE SWITCHING 46 FIGURE8 GRAM ACCESS BETWEEN SYSTEM INTERFACE AN RGB INTERFACE 47 FIGURE9 RELATIONSHIP BETWEEN RGB I/F SIGNALS AN LC RIVING SIGNALS FOR PANEL 48 FIGURE REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 49 FIGURE REGISTER SETTING WITH I8/M68 SYSTEM INTERFACE 5 FIGURE REGISTER REA/WRITE TIMING OF I8 SYSTEM INTERFACE 5 FIGURE3 REGISTER REA/WRITE TIMING OF M68 SYSTEM INTERFACE 5 FIGURE4 INTERLACE SCAN OF AC RIVE 6 FIGURE5 OUTPUT TIMING OF INTERLACE GATE SIGNALS (THREE-FIEL IS SELECTE) 6 FIGURE6 AC RIVING ALTERNATING TIMING 6 FIGURE7 GRAM ACCESS IRECTION SETTING 6 FIGURE8 SCANNING START POSITION FOR GATE RIVER 73 FIGURE9 GRAM ACCESS RANGE CONFIGURATION 76 FIGURE3 GRAM REA/WRITE TIMING OF I8-SYSTEM INTERFACE 8 FIGURE3 GRAM REA/WRITE TIMING OF M68-SYSTEM INTERFACE 8 FIGURE3 I8-SYSTEM INTERFACE WITH 8-/9-BIT ATA BUS (SS=, BGR= ) 83 FIGURE33 I8-SYSTEM INTERFACE WITH 8-/9-BIT ATA BUS (SS=, BGR= ) 84 FIGURE34 GRAM ACCESS WINOW MAP 85 FIGURE35 GRAYSCALE MAPPING 86 FIGURE36 GRAYSCALE VOLTAGE GENERATION 87 FIGURE37 GRAYSCALE VOLTAGE AJUSTMENT 88 The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 3 of 7 Version:

5 FIGURE38 GRAYSCALE VOLTAGE AJUSTMENT 89 FIGURE39 GAMMA CURVE AJUSTMENT 9 FIGURE4 RELATIONSHIP BETWEEN GRAM ATA AN OUTPUT LEVEL FIGURE4 POWER SUPPLY CIRCUIT BLOCK 4 FIGURE4 VOLTAGE CONFIGURATION IAGRAM 5 FIGURE43 POWER ON/OFF SEQUENCE 6 FIGURE44 STB MOE REGISTER SETTING SEQUENCE 7 FIGURE45 I8-SYSTEM BUS TIMING FIGURE46 M68-SYSTEM BUS TIMING FIGURE47 M68-SYSTEM INTERFACE TIMING FIGURE48 SPI SYSTEM BUS TIMING 3 FIGURE49 RGB INTERFACE TIMING 4 The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 4 of 7 Version:

6 Introduction a-si TFT LC Single Chip river is a 6,44-color one-chip SoC driver for a-tft liquid crystal display with resolution of 76RGBx dots, comprising a 58-channel source driver, a -channel gate driver, 87 bytes RAM for graphic data of 76RGBx dots, and power supply circuit has four kinds of system interfaces which are i8/m68-system MPU interface (8-/9-/6-/8-bit bus width), serial data transfer interface (SPI) and RGB 6-/6-/8-bit interface (OTCLK, VSYNC, HSYNC, ENABLE, [7:]) In RGB interface, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with low I/O interface power supply up to 65V, with an incorporated voltage follower circuit to generate voltage levels for driving an LC The also supports a function to display in 8 colors and a standby mode, allowing for precise power control by software These features make the an ideal LC driver for medium or small size portable products such as digital cellular phones or small PA, where long battery life is a major concern Features Single chip solution for a liquid crystal QCIF+ TFT LC display 76RGBx-dot resolution capable of graphics display in 6,44 color Incorporate 58-channel source driver and -channel gate driver Internal 87, bytes graphic RAM High-speed RAM burst write function System interfaces i8 system interface with 8-/ 9-/6-/8-bit bus width M68 system interface with 8-/ 9-/6-/8-bit bus width Serial Peripheral Interface (SPI) RGB interface with 8-/6-/8-bit bus width (VSYNC, HSYNC, OTCLK, ENABLE, [7:]) Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Abundant functions for color display control γ-correction function enabling display in 6,44 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LC panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 5 of 7 Version:

7 Low -power consumption architecture Low operating power supplies: IOVcc (V3) = 65 ~ 33 V (interface I/O) Vci = 5 ~ 33 V Low voltage drive: AV (AV) = 45 ~ 55 V The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 6 of 7 Version:

8 3 Block iagram a-si TFT LC Single Chip river IOVCC IM[3:] nreset ncs nwr nr RS [7:] SI SO SCL ENABLE HSYNC VSYNC MPU I/F 8-bit 6-bit 9-bit 8-bit SPI I/F RGB I/F 8-bit 6-bit 6-bit 8 8 Index Register (IR) 7 Control Register (CR) Graphics Operation 8 Address Counter (AC) V63 ~ LC Source river S[58:] OTCLK TEST_MOE[:] TEST_MUX[:] TEST_CSN[:] VSYNC I/F 8 Read Latch 7 Write Latch 7 Grayscale Reference Voltage VREGOUT VGS VCI V RV GN Regulator Graphics RAM (GRAM) M FLM CL RC-OSC Timing Controller LC Gate river G[:] VCI GN Charge-pump Power Circuit VCOM Generator VCOM The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 7 of 7 Version:

9 4 Pin escriptions a-si TFT LC Single Chip river Pin Name I/O Type escriptions Input Interface Select the MPU system interface mode IM3 IM IM IM MPU-Interface Mode Pin in use M68-system 6-bit interface [7:], [8:] M68-system 8-bit interface [7:] i8-system 6-bit interface [7:], [8:] i8-system 8-bit interface [7:] IM3, IM, IM, IM/I I IOVcc I 4-bit 4 wires Serial Peripheral Interface (SPI) SI, SO, SCL, ncs 9-bit 3 wires Serial Peripheral SA, SCL, ncs Interface 8-bit 4 wires Serial Peripheral Interface SA, SCL, ncs, RS (/CX) M68-system 8-bit interface [7:] M68-system 9-bit interface [7:9] i8-system 8-bit interface [7:] i8-system 9-bit interface [7:9] * * Setting invalid When the serial peripheral interface is selected, IM pin is used for the device code I setting A chip select signal ncs I MPU IOVcc Low: the is selected and accessible High: the is not selected and not accessible Fix to IOVCC level when not in use A register select signal RS (/CX) I MPU IOVcc Low: select an index or status register High: select a control register Fix to GN level when not in use RW_nWR /SCL I MPU IOVcc In 68-system mode, this is used to select operation, read or write (RW) In 8-system mode, this serves as a write strobe signal (nwr) In SPI mode, it serves as a synchronous clock (SCL) E_nR I MPU IOVcc In 68-system mode, this serves as write/read enable strobe (E) In 8-system mode, this serves as a read strobe signal (nr) Must be fixed to GN level when SPI mode nreset I MPU IOVcc A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power 8-bit parallel bi-directional data bus for MPU system interface mode [7:] I/O MPU IOVcc Serves as an input data bus for MPU I/F 8-bit I/F: [7:] is used The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 8 of 7 Version:

10 Pin Name I/O Type escriptions 9-bit I/F: [7:9] is used 6-bit I/F: [7:] and [8:] is used 8-bit I/F: [7:] is used Serves as an input data bus for RGB I/F 6-bit interface: [7:] 6-bit interface: {[7:3], [:]} 8-bit interface: [7:] Unused pins must be fixed GN level In the 4-bit 4 wires serial peripheral interface, this pin is used as input SI/SA I/O MPU IOVcc pin In the 8/9-bit serial peripheral interface, this pin is used as bi-directional data pin Fix to GN level when not in use Serial data output (SO) pin in serial interface operation The data is SO O MPU IOVcc outputted on the falling edge of the SCL signal When the SPI interface is not used, please let SO as floating A dot clock signal OTCLK I MPU IOVcc PL = : Input data on the rising edge of OTCLK PL = : Input data on the falling edge of OTCLK Fix to GN level when not in use A frame synchronizing signal VSYNC I MPU IOVcc VSPL = : Active low VSPL = : Active high Fix to GN level when not in use A line synchronizing signal HSYNC I MPU IOVcc HSPL = : Active low HSPL = : Active high Fix to GN level when not in use A data ENEABLE signal in RGB interface mode ENABLE I MPU IOVcc Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal Fix to GN level when not in use LC riving signals S58~S O LC Source output voltage signals applied to liquid crystal The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 9 of 7 Version:

11 Pin Name I/O Type escriptions G~G O LC TFT VCOM O common electrode To change the shift direction of signal outputs, use the SS bit SS =, the data in the RAM address h is output from S SS =, the data in the RAM address h is output from S58 S, S4, S7, display red (R), S, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = ) Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels Charge-pump and Regulator Circuit VCOMH O - The high level of VCOM AC voltage VCOML O - The low level of VCOM AC voltage Adjust the VCOML level with the VML[6:] bits To fix the VCOML level to GN and set VCOMG = VCOMR - open This is a floating pad Leave this pin open CP, CM CP, CM - open Generating AV level CP, CM CP, CM - open Generating VGH, VGL level C3P, C3M - open Generating VCL level AV O Stabilizing capacitor, AV VGH O - Stabilizing VGL O capacitor, VGL Stabilizing VCL O capacitor, VCL An output voltage from the step-up circuit, twice the Vci level See Configurations of Power supply circuit AV = 45 ~ 55V An output voltage from the step-up circuit, 6 ~ 7 times the Vci level The step-up rate is set with the BT bits See Configurations of Power supply circuit VGH = max 55V An output voltage from the step-up circuit, -5 ~ -7 times the Vci level The step-up rate is set with the BT bits See Configurations of Power supply circuit VGL = min 3V An output voltage from the step-up circuit 3, times the Vci level Connect to a stabilizing capacitor VCL = ~ Vci The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page of 7 Version:

12 Pin Name I/O Type escriptions GV (GV) I/O - GN or VGS I external resistor VREF - - A reference voltage level The voltage level of GV can be adjusted by the GV[6:] bits GV is a source driver grayscale reference voltage GV = (Vci+3) ~ (AV 5)V A reference level for the grayscale voltage generating circuit The VGS level can be changed by connecting to an external resistor Floating pin This pin is a floating pin Power Pads Vci I Power supply A supply voltage to the analog circuit Connect to an external power supply of 5 ~ 33V IOVCC (V3) I Power supply A supply voltage to the interface pins (IOVcc = 65 ~ 33V) AVSS (GN) P - GN for analog circuits VSSC (GN) P - GN for booster circuits VSS (GN) P - GN for logic circuits RV P - Voltage regulator output for V Connect to V pad for supplying power Power supply for memory and internal logic circuit V P RV Connect this pin to regulated voltage output RV o not apply any external power to this pin over 8V Test Pads CL O - Output pins used only for test purpose at vendor-side In normal operation, leave this pin open Tearing effect output pin to synchronize MCU to frame writing, activated by FLM O - S/W command When this pin is not activated, this pin is low If not used, open this pin M O - TEST_MOE[:] I - Output pins used only for test purpose at vendor-side In normal operation, leave this pin open Input pins used only for test purpose In normal operation, connect this pin to VSS or IOVCC Input pins used only for test purpose TEST_MUX[] I - This pin is internal pull low In normal operation, please connect this pin to GN or leave this pin as open TEST_MUX[:] I - Input pins used only for test purpose In normal operation, connect this pin to VSS or IOVCC The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page of 7 Version:

13 Pin Name I/O Type escriptions TEST_A I - Input pins used only for test purpose In normal operation, connect this pin to VSS or IOVCC Contact - - Contact resistance measurement pin EXCLK I - EN_EXCLK I - Test pin In normal operation, connect this pin to VSS or IOVCC Test pin In normal operation, connect this pin to VSS or IOVCC Liquid crystal power supply specifications Table No Item escription TFT data lines 58 pins (76 x RGB) TFT gate lines pins 3 TFT display s capacitor structure Cst structure only (Common VCOM) 4 Liquid crystal drive output 5 Input voltage 6 Internal step-up circuits S ~ S58 V ~ V63 grayscales G ~ G VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes IOVcc 65V ~ 33V Vci 5V ~ 33V AV Vci x VGH Vci x 6, x 7 VGL Vci x -5, x -6, x -7 VCL Vci x - The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page of 7 Version:

14 a-si TFT LC Single Chip river 5 Pad Arrangement and Coordination Y X 6um Chip Center The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 3 of 7 Version:

15 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y UMMY CP VCI TEST_MUX<> GV UMMY CP VCI TEST_MUX<> VCOMH VCOM CP VCI TEST_MUX<> VCOMH VCOM CP VCI TEST_A VCOML VCOM CP VCI EN_EXCLK VCOML VCOM CP VCL EXCLK VCOMR UMMY CP VCL AVSS CONTACT VGH CM VCL AVSS CONTACT VGH CM VCL AVSS UMMY VGH CM VCL AVSS VCOM VGH CM UMMY AVSS VCOM VGH CM RS AVSS VCOM UMMY CM CSB AVSS VCOM VGL CM VSYNC AVSS UMMY VGL CM HSYNC AVSS UMMY VGL CP OTCLK VSS UMMY VGL CP ENABLE VSS UMMY VGL CP RESETB VSS UMMY UMMY CP SI VSS UMMY CP CP E_R VSS G<> CP CP RW_WRB VSS G<4> CP CM <7> VSS G<6> CM CM <6> VSS G<8> CM CM <5> VSS G<> CM CM <4> VSS G<> CP CM <3> VGS G<4> CP CM <> VGS G<6> CP C3P <> RV G<8> CM C3P <> RV G<> CM C3P <9> RV G<> CM C3P <8> RV G<4> UMMY C3P <7> RV G<6> UMMY C3M <6> RV G<8> VSSC C3M <5> V G<3> VSSC C3M <4> V G<3> VSSC C3M <3> V G<34> VSSC C3M <> V G<36> VSSC AV <> V G<38> VSSC AV <> V G<4> VSSC AV IM<3> V G<4> VSSC AV IM<> V G<44> VSSC AV IM<> V G<46> VSSC AV IM<> V G<48> VCI AV SO V G<5> VCI AV M V G<5> VCI VCI FLM UMMY G<54> VCI VCI CL VREF G<56> VCI VCI TEST_MOE<> GV G<58> VCI VCI TEST_MOE<> GV G<6> CP VCI TEST_MOE<> GV G<6> 68 3 The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 4 of 7 Version:

16 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 5 G<64> G<64> S<56> S<466> S<46> G<66> G<66> S<55> S<465> S<45> G<68> G<68> S<54> S<464> S<44> G<7> G<7> S<53> S<463> S<43> G<7> G<7> S<5> S<46> S<4> G<74> G<74> S<5> S<46> S<4> G<76> G<76> S<5> S<46> S<4> G<78> G<78> S<59> S<459> S<49> G<8> G<8> S<58> S<458> S<48> G<8> G<8> S<57> S<457> S<47> G<84> G<84> S<56> S<456> S<46> G<86> G<86> S<55> S<455> S<45> G<88> G<88> S<54> S<454> S<44> G<9> G<9> S<53> S<453> S<43> G<9> G<9> S<5> S<45> S<4> G<94> G<94> S<5> S<45> S<4> G<96> G<96> S<5> S<45> S<4> G<98> G<98> S<499> S<449> S<399> G<> G<> S<498> S<448> S<398> G<> G<> S<497> S<447> S<397> G<4> G<4> S<496> S<446> S<396> G<6> G<6> S<495> S<445> S<395> G<8> G<8> S<494> S<444> S<394> G<> G<> S<493> S<443> S<393> G<> G<> S<49> S<44> S<39> G<4> G<4> S<49> S<44> S<39> G<6> G<6> S<49> S<44> S<39> G<8> G<8> S<489> S<439> S<389> G<> G<> S<488> S<438> S<388> G<> UMMY S<487> S<437> S<387> G<4> UMMY S<486> S<436> S<386> G<6> UMMY S<485> S<435> S<385> G<8> UMMY S<484> S<434> S<384> G<3> UMMY S<483> S<433> S<383> G<3> UMMY S<48> S<43> S<38> G<34> UMMY S<48> S<43> S<38> G<36> UMMY S<48> S<43> S<38> G<38> UMMY S<479> S<49> S<379> G<4> S<58> S<478> S<48> S<378> G<4> S<57> S<477> S<47> S<377> G<44> S<56> S<476> S<46> S<376> G<46> S<55> S<475> S<45> S<375> G<48> S<54> S<474> S<44> S<374> G<5> S<53> S<473> S<43> S<373> G<5> S<5> S<47> S<4> S<37> G<54> S<5> S<47> S<4> S<37> G<56> S<5> S<47> S<4> S<37> G<58> S<59> S<469> S<49> S<369> 3 99 G<6> S<58> S<468> S<48> S<368> G<6> S<57> S<467> S<47> S<367> 78 3 The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 5 of 7 Version:

17 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 5 S<366> S<36> S<66> S<6> S<66> S<365> S<35> S<65> S<5> S<65> S<364> S<34> S<64> S<4> S<64> S<363> S<33> S<63> S<3> S<63> S<36> S<3> S<6> S<> S<6> S<36> S<3> S<6> S<> S<6> S<36> S<3> S<6> S<> S<6> S<359> S<39> S<59> S<9> S<59> S<358> S<38> S<58> S<8> S<58> S<357> S<37> S<57> S<7> S<57> S<356> 7 56 S<36> 7 6 S<56> S<6> S<56> S<355> S<35> S<55> S<5> S<55> S<354> S<34> S<54> S<4> S<54> S<353> S<33> S<53> S<3> S<53> S<35> S<3> S<5> S<> S<5> S<35> S<3> 3 66 S<5> S<> S<5> S<35> S<3> S<5> S<> S<5> S<349> S<99> S<49> S<99> S<49> S<348> S<98> S<48> S<98> S<48> S<347> S<97> S<47> S<97> S<47> S<346> S<96> S<46> S<96> S<46> S<345> S<95> S<45> S<95> S<45> S<344> S<94> 7 63 S<44> S<94> S<44> S<343> S<93> S<43> S<93> S<43> S<34> S<9> S<4> S<9> S<4> S<34> S<9> S<4> S<9> S<4> S<34> S<9> S<4> S<9> S<4> S<339> S<89> S<39> S<89> S<39> S<338> S<88> S<38> S<88> S<38> S<337> S<87> S<37> S<87> S<37> S<336> S<86> S<36> S<86> S<36> S<335> S<85> S<35> S<85> S<35> S<334> S<84> S<34> S<84> S<34> S<333> S<83> S<33> S<83> S<33> S<33> S<8> S<3> S<8> S<3> S<33> S<8> S<3> S<8> S<3> S<33> S<8> S<3> S<8> S<3> S<39> S<79> S<9> S<79> S<9> S<38> S<78> S<8> S<78> S<8> S<37> S<77> S<7> S<77> S<7> S<36> S<76> S<6> S<76> S<6> S<35> S<75> S<5> S<75> S<5> S<34> S<74> S<4> S<74> S<4> S<33> S<73> S<3> S<73> S<3> S<3> S<7> S<> S<7> S<> S<3> S<7> S<> S<7> S<> S<3> S<7> S<> S<7> S<> S<39> S<69> S<9> S<69> S<9> S<38> S<68> S<8> S<68> S<8> S<37> S<67> S<7> S<67> S<7> The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 6 of 7 Version:

18 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 75 S<6> S<66> S<6> G<67> G<67> S<5> S<65> S<5> G<65> G<65> S<4> S<64> S<4> G<63> G<63> S<3> S<63> S<3> G<6> G<6> S<> S<6> S<> G<59> G<59> S<> S<6> S<> G<57> G<57> S<> S<6> S<> G<55> G<55> S<9> S<59> S<9> G<53> G<53> S<8> S<58> S<8> G<5> G<5> S<7> S<57> S<7> G<49> G<49> S<6> S<56> S<6> G<47> G<47> S<5> S<55> S<5> G<45> G<45> S<4> S<54> S<4> G<43> G<43> S<3> S<53> S<3> G<4> G<4> S<> S<5> S<> G<39> G<39> S<> S<5> S<> G<37> G<37> S<> S<5> UMMY G<35> G<35> S<99> S<49> UMMY G<33> G<33> S<98> S<48> UMMY G<3> G<3> S<97> S<47> UMMY G<9> G<9> S<96> S<46> UMMY G<7> G<7> S<95> S<45> UMMY G<5> G<5> S<94> S<44> UMMY G<3> G<3> S<93> S<43> UMMY G<> G<> S<9> S<4> G<9> G<9> G<9> S<9> S<4> G<7> G<7> G<7> S<9> S<4> G<5> G<5> G<5> S<89> S<39> G<3> G<3> G<3> S<88> S<38> G<> G<> G<> S<87> S<37> G<9> G<9> G<9> S<86> S<36> G<7> G<7> G<7> S<85> S<35> G<5> G<5> G<5> S<84> S<34> G<3> G<3> G<3> S<83> S<33> G<> G<> G<> S<8> S<3> G<99> G<99> UMMY S<8> S<3> G<97> G<97> UMMY S<8> S<3> G<95> G<95> UMMY S<79> S<9> G<93> G<93> UMMY S<78> S<8> G<9> G<9> Alignment Mark Left S<77> S<7> G<89> G<89> Alignment Mark Right S<76> S<6> G<87> G<87> S<75> S<5> G<85> G<85> S<74> S<4> G<83> G<83> S<73> S<3> G<8> G<8> S<7> S<> G<79> G<79> S<7> S<> G<77> G<77> S<7> S<> G<75> G<75> S<69> S<9> G<73> G<73> S<68> S<8> G<7> G<7> S<67> S<7> G<69> G<69> The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 7 of 7 Version:

19 S ~ S58 G ~ G (pin 6 ~ 988) I/O Pads (pin ~ 5) Pad Pump Pad Pump 48 The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 8 of 7 Version:

20 6 Block escription a-si TFT LC Single Chip river MPU System Interface supports three system high-speed interfaces: i8/m68-system high-speed interfaces to 8-, 9-, 6-, 8-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:] pins has a 6-bit index register (IR), an 8-bit write-data register (WR), and an 8-bit read-data register (RR) The IR is the register to store index information from control registers and the internal GRAM The WR is the register to temporarily store data to be written to control registers and the internal GRAM The RR is the register to temporarily store data read from the GRAM ata from the MPU to be written to the internal GRAM are first written to the WR and then automatically written to the internal GRAM in internal operation ata are read via the RR from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time except starting oscillator takes clock cycle Registers selection by system interface (8-/9-/6-/8-bit bus width) I8 M68 Function RS nwr nr E RW Write an index to IR register Read an internal status Write to control registers or the internal GRAM by WR register Read from the internal GRAM by RR register Registers selection by the SPI system interface Function R/W RS Write an index to IR register Read an internal status Write to control registers or the internal GRAM by WR register Read from the internal GRAM by RR register Parallel RGB Interface supports the RGB interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and OTCLK In RGB interface mode, data (7-) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 9 of 7 Version:

21 Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 87, (76 x x 8/8) bytes, using 8 bits for each pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 6,44 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) The can provide R-C oscillation without external resistor The appropriate oscillation frequency for operation voltage, display size, and frame frequency can be obtained by adjusting the register setting value[rfh] Clock pulse can also be supplied externally Since R-C oscillation stops during the standby mode, currentconsumption can be reduced For details, see the Oscillation Circuit section LC river Circuit The LC driver circuit of consists of a 58-output source driver (S ~ S58) and a -output gate driver (G~G) isplay pattern data are latched when the 58th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH or VGL level The shift direction of 58-bit source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LC module LC river Power Supply Circuit The LC drive power supply circuit generates the voltage levels GV, VGH, VGL and Vcom for driving an LC The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page of 7 Version:

22 7 System Interface a-si TFT LC Single Chip river 7 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, OTCLK and data bus [7:] operates in one of the following 3 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB interfaces Operation Mode RAM Access Setting (RM) isplay Operation Mode (M) Internal operating clock only (isplaying still pictures) RGB interface () (isplaying moving pictures) RGB interface () (Rewriting still pictures while displaying moving pictures) System interface (RM = ) RGB interface (RM = ) System interface (RM = ) Note ) Registers are set only via the system interface Note ) The RGB-I/F is not available simultaneously Internal operating clock (M=) RGB interface (M=) RGB interface (M=) The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page of 7 Version:

23 System System Interface 8/6/6 ncs RS nwr nr [7:] LC IC RGB Interface ENABLE VSYNC HSYNC OTCLK Figure System Interface and RGB Interface connection 7 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:] pins The system interface is used for setting instructions and RAM access IM3 IM IM IM/I Interface Mode Pin M68-system 6-bit interface [7:], [8:] M68-system 8-bit interface [7:] i8-system 6-bit interface [7:], [8:] i8-system 8-bit interface [7:] I Serial Peripheral Interface (SPI) SI, SO,SCL,nCS 3-wire 9-bit serial interface ncs, SCL, SA 4-wire 8-bit serial interface ncs, SCL, SA, RS (/CX) M68-system8-bit interface [7:] M68-system 9-bit interface [7:9] i8-system8-bit interface [7:] i8-system 9-bit interface [7:9] * * Setting invalid The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page of 7 Version:

24 7 8-bit System Interface The data format for 8-bit data bus is as following, Read/Write Register ata format: ata Bus ([7:]) Register Bit ([5:]) Read/Write GRAM ata format: 8-bit S ys te m Inte rfa ce (6 6K colors ) Input a ta GRAM a ta R 5 R 4 R 3 R R R G5 G 4 G3 G G G B5 B4 B3 B B B Figure 8-bit System Interface ata Format The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 3 of 7 Version:

25 7 6-bit System Interface The data format for 6-bit data bus is as following, Read/Write Register ata format: ata Bus ([7:]), ([8:]) Register Bit ([5:]) The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 4 of 7 Version:

26 Read/Write GRAM ata format: 6-bit S yste m Inte rfa ce (65 65K colors ) MT[:]= Input ata GRAM ata R 5 R 4 R 3 R R R G 5 G 4 G 3 G G G B5 B4 B3 B B B 6-bit S yste m Inte rfa ce MS B Mode (6 6K colors, Tra nsfe rs /pixe l) l MT[:]= " s t Tra ns fe r n d Tra n s fe r Input ata GRAM ata R 5 R 4 R 3 R R R G 5 G 4 G 3 G G G B5 B4 B3 B B B S (3n +) S (3n +) S (3n +3) n d Tra n s fe r 3 rd Tra n s fe r Input ata GRAM ata R 5 R 4 R 3 R R R G 5 G 4 G 3 G G G B5 B4 B3 B B B S (3n +4) S (3n +5) S (3n +6) 6-bit S yste m Inte rfa ce MS B Mode (6 6K colors, Tra nsfe rs /pixe l) l MT[:]= " s t Tra n s fe r n d Tra n s fe r Input ata GRAM ata R 5 R 4 R 3 R R R G 5 G 4 G 3 G G G B5 B4 B3 B B B 6-bit S yste m Inte rfa ce LS B Mode (6 6K colors, Tra ns fe rs /pixe l) l MT[:]= " s t Tra n s fe r n d Tra ns fe r Input ata GRAM ata R 5 R 4 R 3 R R R G 5 G 4 G 3 G G G B5 B4 B3 B B B Figure3 6-bit System Interface ata Format The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 5 of 7 Version:

27 i8 Read/Write Timing: (a ) Write to GRAM ncs RS nr nwr [7:] Write h to index register Write GRAM data Nth pixel Write GRAM data (N+)th pixel Write GRAM da ta (N+)th pixel Write GRAM data (N+3)th pixel (b) Re a d from GRAM ncs RS nr nwr [7:] Write h to index register ummy Re a d st Read data Nth pixel nd Read data (N+)th pixel 3rd Read data (N+)th pixel Figure4 i8 6/8-bit System Interface Timing M68 Read/Write Timing: (a ) Write to GRAM ncs RS R/W E [7:] Write h to index register Write GRAM data Nth pixel Write GRAM data (N+)th pixel Write GRAM da ta (N+)th pixel Write GRAM data (N+3)th pixel (b) Re a d from GRAM ncs RS R/W E [7:] Write h to index register ummy Re a d st Read data Nth pixel nd Read data (N+)th pixel 3rd Read data (N+)th pixel Figure5 M68 6/8-bit System Interface Timing The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 6 of 7 Version:

28 73 9-bit System Interface The 7~9 pins are used to transfer the data When writing the 6-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first The unused [8:] pins must be tied to ground Read/Write Register ata format: ata Bus ([7:9]) st Transfer nd Transfer 3 9 Register Bit ([5:]) Read/Write GRAM ata format: 9-bit S ys te m Inte rfa ce (6 6K colors ) st Transfer (Upper bits ) nd Transfer (Lower bits ) Input a ta Write a ta Re gis te r W 7 W 6 W 5 W 4 W 3 W W W W 9 W 8 W 7 W 6 W 5 W 4 W 3 W W W GRAM a ta & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B Figure6 9-bit System Interface ata Format B The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 7 of 7 Version:

29 74 8-bit System Interface The 7~ pins are used to transfer the data When writing the 6-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first The written data is expanded into 8 bits internally (see the figure below) and then written into GRAM The unused [9:] pins must be tied to ground Read/Write Register ata format: ata Bus ([7:]) st Transfer nd Transfer 4 3 Register Bit ([5:]) Read/Write GRAM ata format: 8-bit S yste m Inte rfa ce (65 65K colors ) MT[:]= ]= st Transfer (Upper bits ) nd Transfer (Lower bits ) Input ata GRAM ata R 5 R 4 R 3 R R R G 5 G 4 G 3 G G G B5 B4 B3 B B B 8-bit S yste m Inte rfa ce (6 6K colors) MT[:]= ]= st Transfer nd Transfer 3rd Transfer Input ata GRAM ata R 5 R 4 R 3 R R R G 5 G 4 G 3 G G G B5 B4 B3 B B B 8-bit S ys te m Inte rfa ce (65 65K colors ) MT[:]= ]= st Transfer nd Transfer 3rd Transfer Input ata GRAM ata R 5 R 4 R 3 R R R G 5 G 4 G 3 G G G B5 B4 B3 B B B Figure7 8-bit System Interface ata Format The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 8 of 7 Version:

30 ata transfer synchronization in 8/9-bit bus interface mode supports a data transfer synchronization function to reset upper and lower counters which count the transfers umner of upper and lower byte in 8/9-bit interface mode If a mismatch arises in then numbers of transfers between the upper and lower byte counters due to noise and so on, the h register is written 4 times consecutively to reset the upper and lower counters so that data transfer will restart with a transfer of upper byte This synchronization function can effectively prevent display error if the upper/lower counters are periodically reset RS R nwr [7:9] Uppe r/ Lowe r h h h h Uppe r Lowe r 8-/9-bit tra ns fe r s ynchroniza tion Figure8 ata Transfer Synchronization in 8/9-bit System Interface The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 9 of 7 Version:

31 73 Serial Peripheral Interface (SPI) 73 4-bit 4 wires Serial Peripherial Interface The Serial Peripheral Interface (SPI) is selected by setting the IM[3:] pins as x level The chip select pin (ncs), the serial transfer clock pin (SCL), the serial data input pin (SI) and the serial data output pin (SO) are used in SPI mode The I pin sets the least significant bit of the identification codethe [7:] pins, which are not used, must be tied to ground The SPI interface operation enables from the falling edge of ncs and ends of data transfer on the rising edge of ncs The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte When the start byte is matched, the subsequent data is received by The seventh bit of start byte is RS bit When RS =, either index write operation or status read operation is executed When RS =, either register write operation or RAM read/write operation is executed The eighth bit of the start byte is used to select either read or write operation (R/W bit) ata is written when the R/W bit is and read back when the R/W bit is After receiving the start byte, starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit All the registers of the are 6-bit format and receive the first and the second byte datat as the upper and the lower eight bits of the 6-bit register respectively In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6 th byte of read back data Start Byte Format Transferred bits S Start byte format Transfer start evice I code RS R/W I / / Note: I bit is selected by setting the IM/I pin RS and R/W Bit Function RS R/W Function Set an index register Read a status Write a register or GRAM data Read a register or GRAM data The information contained herein is the exclusive property of ILI Technology Corp and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 3 of 7 Version: