ILI /900/864/816-Output Channels TFT LCD Gate Driver. Specification Preliminary

Transcription

1 960/900/864/816-Output Channels TFT LCD Gate Driver Specification Preliminary Version: V0.05 Document No.: _SPEC_V0.05.pdf ILI TECHNOLOGY CORP. 8F, No.38, Taiyuan St., Jhubei City, Hsinchu County 302, Taiwan, R.O.C Tel ; Fax

2 Table of Contents Section Page 1. Introduction Features Pin Descriptions Operation Description Device operation principle Device operation Mode (output channel) selection Relationship between RL, STVR and STVL Device power supply Power ON/OFF Sequence Start Pulse Input Limitation DC Characteristic Absolute Maximum Rating Recommended operating conditions Electrical Characteristics AC Characteristic Timing Chart Pin Assignment (IC Face View) Pad Location Bump Mask Information Revision History Page 1 of 29 Version: 0.05

3 1. Introduction is a 960/900/864/816-channel outputs gate driver used for driving the gate of TFT LCD panel. After a start pulse is triggered, output pins will output high-driving voltage pulses sequentially for the gate signals of the LCD Panel. This chip also provides shift up/down selection and cascade functions for dot expansion. 2. Features 2-level output gate driver for TFT LCD panel High voltage CMOS process technology COG package 960/900/864/816 channels output and 2 channel outputs which are fixed to VEE Bi-directional data shift capability Double gate sequence control function Maximum +40V output driving voltage 200KHz maximum operation frequency Cascade function for dot-expansion 2.7 ~ 3.6V logical interface Page 2 of 29 Version: 0.05

4 3. Block Diagram (1) G0 G960 G959 G2 G Output Buffer Level Shift Bi-directional Shift Register Input Buffer MODE1 XON OE STVL STVR RL SEL CPV G961 (1) MODE0 VGH VDD VSS VEE * Note: (1) G0 and G961 are LCD panel auxiliary pins. These pins always keep at VEE. Page 3 of 29 Version: 0.05

5 4. Pin Descriptions Pin Name I/O Function Descriptions CPV I Shift clock input SEL Opertaing or I (Pull-high) testing Shift direction RL I control pin This is the clock input for chip internal shift register. Data is shifted at each rising edge of this clock. SEL=H:Normal Operating. Normal pull up. SEL=L:for testing. This pin controls the output shifting direction as listed below. RL =H:STVR G1 G2 G959 G960 STVL RL =L:STVL G960 G959 G2 G1 STVR These two pins are the device start pulse input or output pin. The STVR STVL I/O Start pulse input/output pin function of these two pins depends on the status of RL pin. STVR STVL RL=H input output RL=L output input OE I The OE signal controls the output enable. OE=L: Normal operation. Output enable OE=H: All driver outputs are fixed to VEE regardless of CPV. However, control the content of shift register is not cleared. When XON input pin is L, all the output pins are forced to VGH level. Note that this pin has higher priority than OE. The chip internal shift XON Output all-on I register is not cleared when XON input is active. (Pull-high) control Remark: Also it has an internal pull high resistor, keep it to VDD is preferred when unused. They is the output channel number selection pin: Output MODE1 MODE0 channel Disable Channel MODE Output Channel H H Default I (pull-high) number selection H L 900 G453~G512 L H 864 G433~G528 L L 816 G409~G552 Remark: Internal normal pull high. G1 ~ G960 O Driver output pins for driving gate electrode of LCD The output voltage is either VGH or VEE for driving the gate electrode of TFT LCD panel depending on the data stored in shift register and the state of OE G0 G961 O Auxiliary pins LCD panel auxiliary pins, these pins always output VEE level. VGH P Power supply Power supply for Gate drive output High VDD P Power supply Digital power Page 4 of 29 Version: 0.05

6 Pin Name I/O Function Descriptions VSS P Power supply Digital ground VEE P Power supply Power supply for Gate drive output low. PASS S Internal link Linked together internal. SHIELDING1 ~ SHIELDING187 SD Auxiliary pins This pin is connected to VEE internally. Not connected. Note1: I: Input; O: Output; I/O: Input/Output; P: Power; S: Shorted line; SD: Shielding pad Note2: The unused input pins are recommended that this pin be connected to either VDD or VSS. 5. Operation Description 5.1 Device operation principle In the condition of MODE=Default & RL=H, the STVR start pulse input is sensed at the rising edge of CPV and stored in the first stage of shift register, which causes the first scan signal is outputted from the OUT1 output pin. While stored data is transferred to the next stage shift register at the rising edge of next CPV, new data of STVR is sensed and stored simultaneously. The output pin ( G1 to G960 ) supplies VGH voltage or VEE voltage to the LCD panel depending on the data stored in the shift register. For normal operation, a VGH voltage is outputted one by one from G1 to G960 in sync with CPV pulse. After 960 CLK rising edge are past, the STVL goes up to high level at the 960th falling edge of CPV and goes down to low level at the 961st falling edge of CPV. This STVL output signal becomes the STVR start pulse input of next cascaded gate driver device. During any H state of OE, the corresponding output channels are forced to VEE level regardless of CPV. The channel output returns to normal status as soon as OE go back to L. The mechanism is as shown below! Page 5 of 29 Version: 0.05

7 5.2 Device operation MODE=Default, RL=H CPV STVR G1 G2 G G959 G960 STVL MODE=Default, RL=L CPV STVL G960 G959 G G2 G1 STVR Page 6 of 29 Version: 0.05

8 MODE=Default, RL=H with OE and XON CPV STVR OE XON G1 G2 G3 G959 G960 STVL Page 7 of 29 Version: 0.05

9 5.3 Mode (output channel) selection Output channel number can choose between by MODE1 and MODE0 pin. The following table explains the relationship! MODE1=H MODE1=H MODE1=L MODE1=L Output MODE0=H MODE0=L MODE0=H MODE0=L Channel 960CH 900CH 864CH 816CH G1 1st 1st 1st 1st G2 2nd 2nd 2nd 2nd : : : : : G th 408th 408th 408th G th 409th 409th Fix to VEE : : : : : G th 430th 430th Fix to VEE G th 431th 431th Fix to VEE G th 432th 432th Fix to VEE G th 433th Fix to VEE Fix to VEE G th 434th Fix to VEE Fix to VEE : : : : : G th 451th Fix to VEE Fix to VEE G th 452th Fix to VEE Fix to VEE G th Fix to VEE Fix to VEE Fix to VEE G th Fix to VEE Fix to VEE Fix to VEE : : : : : G th Fix to VEE Fix to VEE Fix to VEE G th Fix to VEE Fix to VEE Fix to VEE G th 513th Fix to VEE Fix to VEE G th 514th Fix to VEE Fix to VEE G th 515th Fix to VEE Fix to VEE : : : Fix to VEE Fix to VEE : : : : : G th 528th Fix to VEE Fix to VEE G th 529th 529th Fix to VEE : : : : : G th 552th 552th Fix to VEE G th 553th 553th 553th : : : : : G th 959th 959th 959th G th 960th 960th 960th Page 8 of 29 Version: 0.05

10 5.4 Relationship between RL, STVR and STVL RL MODE1=H MODE0=H 960CH Start pulse Data transfer direction Input Output H STVR STVL G001 G002 G452 G513 G959 G960 L STVL STVR G960 G959 G513 G452 G002 G001 RL MODE1=H MODE0=L 900CH Start pulse Data transfer direction Input Output H STVR STVL G001 G002 G452 G513 G959 G960 L STVL STVR G960 G959 G513 G452 G002 G001 RL MODE1=L MODE0=H 864CH Start pulse Data transfer direction Input Output H STVR STVL G001 G002 G432 G529 G959 G960 L STVL STVR G960 G959 G529 G432 G002 G001 RL MODE1=L MODE0=L 816CH Start pulse Data transfer direction Input Output H STVR STVL G001 G002 G408 G553 G959 G960 L STVL STVR G960 G959 G553 G408 G002 G001 Page 9 of 29 Version: 0.05

11 5.5 Device power supply The input signal level of CPV, RL, OE, STVR and STVL have to swing between VDD and VSS. The signal output level of start pulse (STVR or STVL) to the next stage cascaded device is VDD for H and VSS for L. The following conditions should be followed. VGH VEE=40V (max) VGH VSS =7~35V VGH VGH VDD VDD VDD VEE VGH VSS VEE VEE VSS VGH VEE VDD VGH VDD VSS Logic input G1 to G960 VEE Note: (1). Input signals of CPV, XON, OE, RL, STVR & STVL, MODE. (2). The High level=vdd and Low level=vss. Page 10 of 29 Version: 0.05

12 5.6 Power ON/OFF Sequence To prevent the device damage from latch up, the power ON/OFF sequence shown below must be followed. Power ON: VDD VEE VGH Power OFF: VGH VEE VDD Power ON: VDD VGH VEE Power OFF: VEE VGH VDD Page 11 of 29 Version: 0.05

13 Power on sequence (VDD VEE VGH) Power on sequence (VDD VGH VEE) Power off sequence (VGH VEE VDD) Power off sequence (VEE VGH VDD) Page 12 of 29 Version: 0.05

14 5.7 Start Pulse Input Limitation The available start pulse is in the following diagram. CPV STVR G1 G2 G3 G4 G5 Long Start Pulse Mode (2 CPV Period) CPV STVR G1 G2 G3 G4 G5 Long Start Pulse Mode (More Than 2 CPV Period) Page 13 of 29 Version: 0.05

15 6. DC Characteristic 6.1 Absolute Maximum Rating Parameter Symbol Rating Unit Min Typ Max Power supply voltage (1) VGH V Power supply voltage (2) VDD V Power supply voltage (3) VEE VGH V Input voltage Vin VDD+0.3 V Operating temperature TOTG C Storage temperature TSTG C Note: (1)All of the voltages listed above are with respective to VSS=0V. (2)Device is subject to be damaged permanently if stresses beyond those absolute maximum ratings listed above. (3)Condition VDD = 3.3V 6.2 Recommended operating conditions ( VSS=0V, TA= -20 ~ +85 C) Parameter Symbol Rating Unit Min Typ Max Power supply voltage (1) VGH 7 - VEE+40 V Power supply voltage (2) VDD V Power supply voltage (3) VEE V Power supply voltage (4) VGH-VEE V Operation frequency Fcpv KHz Operation temperature Ta C Page 14 of 29 Version: 0.05

16 6.3 Electrical Characteristics ( VGH=25V, VEE=-15V, VDD=3.3V, VSS=0V, TA=25 C) Parameter Symbol Condition Rating Unit Application Min Typ Max pin Input H voltage VIH - 0.7VDD - VDD V All input Input L voltage VIL - VSS - 0.3VDD V All input Output H voltage VOH IOH=40µA VDD VDD V STVR,L Output L voltage) VOL IOL=40µA VSS - VSS+0.4 V STVR,L Output H resistance ROH VOUT= VGH-0.5V Ω G0~961 Output L resistance ROL VOUT= VEE+0.5V Ω G0~961 Input leakage current IIN ±1 µa Note (b) Pull-up resistance RIN VIN=VDD kω XON, Mode,SEL pin,when VDD=3.3V and TA=25 C VDD operating current VGH operating current VEE operating current IVDD Note (a) - - T.B.D µa - IVGH Note (a) - - T.B.D µa - IVEE Note (a) - - T.B.D µa - Note (a) Power consumption with the following condition: Output no load, VGH=+25V, VEE= -15V, VDD=3.3V, VIH=VDD, VIL=VSS, FCPV=60 khz, OE=VIL, XON=VIH, Mode= VIH. (b) All input except XON and Mode pin. Page 15 of 29 Version: 0.05

17 7. AC Characteristic ( VGH=25V, VEE=-15V, VDD=3.3V, VSS=0V, TA=25 C) Parameter Symbol Condition Spec Unit Min Typ Max CPV period tcpv µs CPV pulse width tcpvh, tcpvl 50% duty cycle µs OE pulse width twoe µs XON pulse width txon µs Data setup time tsu µs Data hold time thd µs CPV to output delay time tpd1 CL=200pF µs Start pulse output delay time tpd2 CL=20pF µs OE to output delay time tpd3 CL=200pF µs XON to output delay time tpd4 CL=200pF µs Power-On Reset Slew Time tpor From 10% to 90% VDD - - ms VDD to VEE Time tdte From 10% VDD to 90% VEE 0 ms VEE to VDD Time tetd From 10% VEE to 90% VDD 0 ms VEE to VGH Time tetg From 10% VEE to 10% VGH 1 ms VGH to VEE Time tgte From 10% VGH to 10% VEE 1 ms VGH Rising Time tggr From 10% to (1) 90% VGH teef ms Note: The measurement point for all of signals is 50% with input and output amplitude. Note(1):teef=> VEE Falling Time, From 10% to 90% VEE Page 16 of 29 Version: 0.05

18 8. Timing Chart tcpv tcpvh tcpvl CPV 50% tsu thd STVR 50% tpd1 tpd1 G1 50% tpd1 tpd1 G2~G960 50% CPV 50% G960 50% tpd2 tpd2 STVL 50% twoe OE 50% G1~ G960 50% XON tpd3 tpd3 tpd4 tpd4 50% txon Page 17 of 29 Version: 0.05

19 9. Pin Assignment (IC Face View) Page 18 of 29 Version: 0.05

20 10. Pad Location Pad No. Name X Y Pad No. Name X Y Pad Name X Y 1 VSS SHIELDING SHIELDING VSS SHIELDING SHIELDING VSS SHIELDING SHIELDING VSS SHIELDING SHIELDING MODE SHIELDING SHIELDING MODE SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING SHIELDING Page 19 of 29 Version: 0.05

21 Pad No. Name X Y Pad No. Name X Y Pad Name X Y 181 SHIELDING G G SHIELDING G G SHIELDING G G SHIELDING G G SHIELDING G G SHIELDING G G SHIELDING G G SHIELDING G G SHIELDING G G SHIELDING G G SHIELDING G G MODE G G MODE G G VSS G G VSS G G VSS G G VSS G G VEE G G VEE G G VEE G G VDD G G VDD G G VDD G G VGH G G VGH G G VGH G G SEL G G SEL G G SEL G G STVR G G STVR G G STVR G G PASS G G PASS G G PASS G G CPV G G CPV G G CPV G G RL G G RL G G RL G G OE G G OE G G OE G G XON G G XON G G XON G G XON G G SHIELDING G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G Page 20 of 29 Version: 0.05

22 Pad Name X Y Pad No. Name X Y Pad Name X Y 361 G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G Page 21 of 29 Version: 0.05

23 Pad Name X Y Pad No. Name X Y Pad Name X Y 541 G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G Page 22 of 29 Version: 0.05

24 Pad Name X Y Pad No. Name X Y Pad Name X Y 721 G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G Page 23 of 29 Version: 0.05

25 Pad Name X Y Pad No. Name X Y Pad Name X Y 901 G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G Page 24 of 29 Version: 0.05

26 Pad Name X Y Pad No. Name X Y Pad Name X Y 1081 G G RL G G RL G G CPV G G CPV G G CPV G G PASS G G PASS G G PASS G G STVL G G STVL G G STVL G G SEL G G SEL G G SEL G G VGH G G VGH G G VGH G G VDD G G VDD G G VDD G G VEE G G VEE G G VEE G G AL_MARK_L G G AL_MARK_R G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G SHIELDING G XON G XON G XON G XON G OE G OE G OE G RL Page 25 of 29 Version: 0.05

27 11. Bump Mask Information Chip size: Symbol Dimensions(um) Symbol Dimensions(um) Symbol Dimensions(um) A 32 B2 40 C2 86 A1 52 B3 25 C3 86 A2 90 B4 70 C4 287 A3 70 B5 57 C5 663 A4 57 B6 80 C A5 54 B7 20 L B 20 C 291 W 670 B1 85 C1 57 Note: Chip dimension include scribe line Alignment Mark type and coordinate Page 26 of 29 Version: 0.05

28 Page 27 of 29 Version: 0.05

29 12. Revision History Version No. Date Page Description /05/12 All New set up /06/ MODE Pull high & Bump Mask Information /06/ Die size & Pin Assignment(STVR&STVL) /04/07 10~12 Modify Power Sequence /10/01 26 Bump Mask Information Page 28 of 29 Version: 0.05