OTi APPROVED SHEET. OTi 6858 Data Sheet USB To RS232 Bridge Controller. OTi-6858 Data Sheet
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1 Last update: 09/28/2005 OTi OTi 6858 Data Sheet USB To RS232 Bridge Controller APPROVED SHEET Ours Technology Inc. No. 85, Guangming 6 th Rd.,Jhubei City Hsinchu County 302, Taiwan R.O.C. TEL: FAX: http: Our Technologies are Yours!
2 OVERVIEW The OTi 6858 is a powerful RS232 port to USB port bridge controller. The two on-chip large buffers can support high speed RS232 Baud Rate up to 3Mbps, and support software programmable Baud Rate. The RS232 flow control can be handled either by software or hardware, which makes it more flexible for applications. On chip Regulator and ROM reduce the cost of system product.. The shutdown mode of the RS232 transceiver is controlled by software, such that various type of transceivers can be used. The USB port is fully compliant with USB. full speed Specifications and supports suspend and resume functions for power management. The Bulk Only transfer type and smart buffer control scheme are adopted for maximum data transfer. The OTi-6858 is available in package: 28-pin SSOP for low cost. FEATURES USB Specification Compliant (as device) Conform to full-speed (2Mb/s) USB Specification, Version. Support Suspend and Resume power management RS232 Serial interface Date format: 5,6,7,8 and 6 Parity Type: Even, Odd, Mark, Space and None Stop Bit:,.5 and 2 bit time Support Software/Hardware RS232 flow control Large buffer on each Transmitting and Receiving port for high speed RS232 transfer Automatic RS232 transceiver shutdown control Software programmable baud rate up to 3M baud Smart buffer control scheme On-chip ROM and External EEPROM for device configuration 2/3
3 On-chip USB transceiver and 5V to 3.3V Regulator LED indicator: Transmitting/Receiving busy or software programmable. Supports Windows 98/SE, ME, 2000, XP 28 Pins SSOP package 3/3
4 BLOCK DIAGARAM 4/3
5 PIN CONFIGUARTION SSOP-28 5/3
6 PIN DESCRIPTION OTi-6858 is available in package: 28-pin SSOP. Pin No. Name Type Description Pin Status at Power On Pin Status at Suspend VSS G Ground NA NA 2 VDD P Power NA NA 3 DSR I Data Set Ready High Impedance High Impedance with pull high with pull high 4 I2C_CLK O EEPROM Clock Output mode Output mode 5 I2C_DATA I/O EEPROM Data High Impedance High Impedance 6 CTS I Clear To Send High Impedance High Impedance with pull high with pull high Shut Down RS232 7 SDT_N O Transceiver low active Output mode Output mode 8 DCD I Data Carrier Detect High Impedance High Impedance with pull high with pull high 9 PON_RST I Low active Power On Reset High Impedance High Impedance 0 DPLS_IO I/O USB D+ High Impedance High Impedance DMNS_IO I/O USB D- High Impedance High Impedance 2 VDD P Power NA NA 3 VSS G Ground NA NA 4 RI I Ring Indicator High Impedance High Impedance with pull high with pull high Shut Down RS232 5 SDT O Transceiver high active/led Output mode Output mode 6 Xtal_In I Crystal pad Input High Impedance High Impedance 7 Xtal_Out O Crystal Pad Output Output mode Output mode 8 VDD P Power NA NA 9 VSS G Ground NA NA 20 AVDD_PLL P PLL Power NA NA 2 AVSS_PLL G PLL Ground NA NA 22 VDD5V P Regulator 5V power In NA NA 23 VSS5V G Regulator GND NA NA 24 VOUT P Regulator 3V power Out NA NA 25 TxD O Data transmitted Output mode Output mode 6/3
7 26 DTR O Data Terminal Ready Output mode Output mode 27 RTS O Request To Send Output mode Output mode 28 RxD I Data received High Impedance with pull high High Impedance with pull high Programmable Baud Rate Generator A 96Mhz clock is input to the Baud Rate synthesis module. The required Baud Rate can be obtained by setting the divider register according to the input clock rate. For example, if the target baud rate is /(38400*6) = 56 the baud rate divider register will be set to (009C)h, and bits 23 to 20 are set to don t care. EEPROM DESCRIPTION EEPROM Content Offset Byte# Name Description 0: CID Check ID 2:3 PID Product ID 4:5 VID Vendor ID 6 EDCR Enable Device Configuration Register 7 DCR Device Configuration Register 8 EMP Enable USB Max Power Description 9 MP USB Max Power Description 0 EIV Enable IC Version Set :2 OF IC Obsolete field 3:4 PC IC Project code 5:6 RN IC Revision Number 7 EDCR0 Enable Device Configuration Register 0 8 DCR0 Device Configuration Register 0 9:50 SN Serial Number 7/3
8 DEVICE CONFIGURATION REGISTER DESCRIPTION Device Configuration Register (DCR) Offset Bit# Name Definition Default 0 VOL SDMS 2 LMS 3 POFS 4 SDS 5 LO Voltage Output Level: RS232 Output Normal Voltage 0 RS232 Output Special Voltage Shutdown Mode Select: Shutdown Output 0 Led Output Led Mode Select: Hardware Control Output 0 Software Control Output PLL Output Frequency Select: 96MHz 0 48MHz Shutdown Select: Normal 0 Shutdown Output Led Output: Output High 0 Output Low Device Configuration Register0 (DCR0) Offset Bit# Name Definition Default 0 ESN Enable USB Serial Number : Off 0 On Electric characteristics Absolute Maximum Ratings Item Regulator Input Voltage Digital Power Voltage Analog Power Voltage Rating 5V±0.5V 3.3V±0.3V 3.3V±0.3V 8/3
9 DC Characteristics Parameter Symbol Min Typ Max Units Regulator Output voltage V RO V Regulator supply current I RO ma Regulator Standby current I RSB µa Input Voltage High Low Schmitt Trigger Threshold voltage Low to High High to Low Output Voltage High Low V ih V il V t+ V t- V oh V ol V V V Input Capacitance C il pf Output Capacitance C ol pf Bi-direction Capacitance C bl pf RS232 Output pin current I RSO 8 ma Normal Output pin current I NO 4 ma AC Characteristics Parameter Symbol Min Typ Max Units Output Rising Time Tlh.43(0pF) 2.6(0pF) 3.44(0pF) ns Output Falling Time Thl 2.48(0pF) 3.77(0pF) 6.7(0pF) ns Temperature Characteristics Parameter Symbol Min Typ Max Units Operating Ta 0 70 C Storage Ts C 9/3
10 APPLICATION CIRCUIT 0/3
11 PACKAGE INFORMATION SSOP-28: plastic shrink small outline package; 28 leads; body width 5.3 mm DIMENSIONS (mm are the original dimensions) UNIT A Max. A A2 b P c D E H E e L P θ mm BSC /3
12 MARKING INFORMATION LINE A OTI LINE B X X X X X X X X X X X X X X X Product code Date code: yyww Second version code First version code 2/3
13 PACKING INFORMATION 3/3
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MK AMD GEODE GX2 CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK1491-09 Description The MK1491-09 is a low-cost, low-jitter, high-performance clock synthesizer for AMD s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked
LMS75LBC176 Differential Bus Transceivers
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Datasheet. Conditions
Features Macroblock Datasheet 16 constant-current output channels Constant output current invariant to load voltage change Excellent output current accuracy: between channels:
ICS Low EMI, Spread Modulating, Clock Generator. Integrated Circuit Systems, Inc. Pin Configuration. Functionality. Block Diagram FSIN_1 FSIN_0
Integrated Circuit Systems, Inc. ICS9720 Low EMI, Spread Modulating, Clock Generator Features: ICS9720 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications that generates an EMI-optimized
NJU3714A 12-BIT SERIAL TO PARALLEL CONVERTER PACKAGE OUTLINE GENERAL DESCRIPTION PIN CONFIGURATION FEATURES BLOCK DIAGRAM
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ICS2510C. 3.3V Phase-Lock Loop Clock Driver. Integrated Circuit Systems, Inc. General Description. Pin Configuration.
Integrated Circuit Systems, Inc. ICS250C 3.3V Phase-Lock Loop Clock Driver General Description The ICS250C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology
NJU3712A 8-BIT SERIAL TO PARALLEL CONVERTER PACKAGE OUTLINE GENERAL DESCRIPTION PIN CONFIGURATION FEATURES BLOCK DIAGRAM
8-BIT SERIAL TO PARALLEL CONVERTER GENERAL DESCRIPTION The NJU3712A is an 8-bit serial to parallel converter especially applying to MPU outport expander. It can operate from 2.4V to 5.5V. The effective
MK1413 MPEG AUDIO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET
DATASHEET MK1413 Description The MK1413 is the ideal way to generate clocks for MPEG audio devices in computers. The device uses IDT s proprietary mixture of analog and digital Phase-Locked Loop (PLL)
SN75C185 LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial-Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
P1P Portable Gaming Audio/Video Multimedia. MARKING DIAGRAM. Features
.8V, 4-PLL Low Power Clock Generator with Spread Spectrum Functional Description The PP4067 is a high precision frequency synthesizer designed to operate with a 27 MHz fundamental mode crystal. Device
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER. Features VDD PLL1 PLL2 GND
DATASHEET ICS252 Description The ICS252 is a low cost, dual-output, field programmable clock synthesizer. The ICS252 can generate two output frequencies from 314 khz to 200 MHz using up to two independently
Catalog
- 1 - Catalog 1. Overview... - 3-2. Feature...- 3-3. Application... - 3-4. Block Diagram... - 3-5. Electrical Characteristics...- 4-6. Operation...- 4-1) Power on Reset... - 4-2) Sleep mode...- 4-3) Working
MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET MK1714-02 Description The MK1714-02 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread designed to generate high frequency clocks with low
HI-3000H, HI-3001H. 1Mbps Avionics CAN Transceiver with High Operating Temperature. PIN CONFIGURATIONS (Top Views) GENERAL DESCRIPTION FEATURES
December 2012 HI-3000H, HI-3001H 1Mbps Avionics CAN Transceiver with High Operating Temperature GENERAL DESCRIPTION PIN CONFIGURATIONS (Top Views) The HI-3000H is a 1 Mbps Controller Area Network (CAN)
Application Circuits 3. 3V R2. C4 100n G PI O. 0 G PI O S e t u p d a ta G PI O. 5 G PI O M o t i o n I n t G PI O. 4 G PI O.
General Description The is an ultra-low power motion detector controller integrated circuit. The device is ideally suited for battery operated wireless motion sensors that make use of an MCU for handling
RT9199. Cost-Effective, 2A Peak Sink/Source Bus Termination Regulator. General Description. Features. Applications. Ordering Information
General Description The is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the devices requirements.
CONDOR C1919 GPS RECEIVER MODULE technical notes GENERAL OVERVIEW
CONDOR C1919 GPS RECEIVER MODULE TECHNICAL HIGHLIGHTS Receiver: GPS L1 frequency (17. MHz), C/A code, -channel continuous tracking NMEA output and input: serial port On-board low noise amplifier GENERAL