RT9199. Cost-Effective, 2A Peak Sink/Source Bus Termination Regulator. General Description. Features. Applications. Ordering Information

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1 General Description The is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the devices requirements. The regulator is capable of actively sinking or sourcing up to A peak while regulating an output voltage to within mv. The output termination voltage can be tightly regulated to track 1/V DDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the pin voltage. The also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The are available in both SOP- and SOP- (Exposed Pad) surface mount packages. Ordering Information Package Type S : SOP- SP : SOP- (Exposed Pad) Operating Temperature Range C : Commercial Standard P : Pb Free with Commercial Standard Note : RichTek Pb-free products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-. Suitable for use in SnPb or Pb-free soldering processes. 1%matte tin (Sn) plating. Pin Configurations Cost-Effective, A Peak Sink/Source Bus Termination Regulator Features Ideal for DDR-II V TT Applications Sink and Source A Peak Current Integrated Power MOSFETs Generate Termination Voltage for DDR Memory Interfaces High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Low External Component Count Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection RoHS Compliant and 1% Lead (Pb)-Free Applications Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR/II Memory Systems (TOP VIEW) SOP- SOP- (Exposed Pad) NC NC NC 1

2 Typical Application Circuit V CNTL = 5V V IN = 1.V R TT R 1 C IN C CNTL N7 EN R C SS C OUT R DUMMY R 1 = R = 1kΩ, R TT = 5Ω / 33Ω / 5Ω C OUT(MIN) = 1μF (Ceramic) + 1μF under the worst case testing condition R DUMMY = 1kΩ as for discharge when V IN is not presented but V CNTL is presented C SS = 1μF, C IN = 47μF (Low ESR), C CNTL = 47μF Test Circuit V IN = 1.V V CNTL = 5V 1.5V C OUT V I L Figure 1. Output Voltage Tolerance, ΔV LOAD V IN = 1.V A V CNTL = 5V.9V.15V R L C OUT.9V V V R L and C OUT Time deleay Figure. Current in Shutdown Mode, I STBY

3 V IN = 1.V V CNTL = 5V.9V A C OUT V I L Figure 3. Current Limit for High Side, I LIM Power Supply with Current Limit V CNTL = 5V V IN = 1.V A.9V I L C OUT V Figure 4. Current Limit for Low Side, I LIM V CNTL = 5V V IN = 1.V.9V V.15V R L C OUT V.9V V would be low if V <.15V would be high if V >.6V R L and C OUT Time deleay Figure 5. Pin Shutdown Threshold, V IH & V IL 3

4 Functional Pin Description Input voltage which supplies current to the output pin. Connect this pin to a well-decoupled supply voltage. To prevent the input rail from dropping during large load transient, a large, low ESR capacitor is recommended to use. The capacitor should be placed as close as possible to the pin. Common Ground. supplies the internal control circuitry and provides the drive voltage. The driving capability of output current is proportioned to the. Connect this pin to 5V bias supply to handle large output current with at least 1μF capacitor from this pin to. An important note to be aware of the always should be exposed to voltages that exceed (i.e. ). Reference voltage input and active low shutdown control pin. Two resistors dividing down the voltage on the pin to create the regulated output voltage. Pulling the pin to ground turns off the device by an open-drain, such as N7, signal N-Channel MOSFET. Regulator output. is regulated to voltage that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output rail. To maintain adequate large signal transient response, typical value of 1μF Al electrolytic capacitor with 1μF ceramic capacitors are recommended to reduce the effects of current transients on. Function Block Diagram Current Limit Thermal Protection + EA - 4

5 Absolute Maximum Ratings (Note 1) Input Voltage, V IN V Control Voltage, V CNTL V Power Dissipation, P T A = 5 C SOP W SOP- (Exposed Pad) W Package Thermal Resistance (Note 4) SOP-, θ JA C/W SOP-, θ JC C/W SOP- (Exposed Pad), θ JA C/W SOP- (Exposed Pad), θ JC C/W Junction Temperature C Lead Temperature (Soldering, 1 sec.) C Storage Temperature Range C to 15 C ESD Susceptibility (Note ) HBM (Human Body Mode) kv MM (Machine Mode) V Recommended Operating Conditions (Note 3) Input Voltage, V IN V to 5.5V Control Voltage, V CNTL V ± 5% Junction Temperature Range C to 15 C Electrical Characteristics ( = 1.V, = 5V, V =.9V, COUT = 1μF (Ceramic), TA = 5 C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units Input Operation Current I CNTL I OUT = A ma Standby Current (Note 7) I STBY V <.V (Shutdown), R LOAD = 1Ω μa Output (DDR II) Output Offset Voltage (Note 5) V OS I OUT = A -- + mv Load Regulation (Note 6) ΔV LOAD I OUT = +1.5A I OUT = 1.5A -- + mv Protection Current limit I LIM A Thermal Shutdown Temperature T SD V CNTL = 5V C Thermal Shutdown Hysteresis ΔT SD V CNTL = 5V C Shutdown Shutdown Threshold V IH Enable V IL Shutdown V 5

6 Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θ JA is measured in the natural convection at T A = 5 C on a high effective thermal conductivity test board (4 Layers, SP) of JEDEC 51-7 thermal measurement standard. The case point of θ JC is on the exposed pad for SOP- (Exposed Pad) package. Note 5. V OS offset is the voltage measurement defined as subtracted from V. Note 6. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from A to A peak. Note 7. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on pin (V IL <.15V). It is measured with V IN = V CNTL = 5V. 6

7 Typical Operating Characteristics Output Voltage vs. Temperature Pin Current vs. Temperature.9 = 1.V, = 5V.6 = 1.V, = 5V.915 Output Voltage (V) Vcntl Pin Current (ma) Source Current Limit vs. Temperature Sink Current Limit vs. Temperature 3.5 = 1.V, = 5V 3.5 = 1.V, = 5V 3 3 Source Current Limit (A) Source Current Limit (A) Current vs. Temperature Shutdown Threshold vs. Temperature 3 = 1.V, = 5V.6 SP, = 5V Current (ma) Shutdown Threshold (V) Turn On Turn Off

8 Output Short-Circuit Protection Output Short-Circuit Protection 1 Sink = 1.V, = 5V 1 Sink =.5V, = 5V Output Short Circuit (A) Output Short Circuit (A) Time (1ms/Div) Time (1ms/Div) 1 Output Short-Circuit Protection Source = 1.V, = 5V Output Short-Circuit Protection Source =.5V, = 5V 1 Output Short Circuit (A) Output Short Circuit (A) Time (1ms/Div) Time (1ms/Div).9V 1.A Transient Response 1.5V 1.A Transient Response Output Voltage Transient (mv) = 1.V, = 5V, =.9V 5 Swing Frequency : 1kHz -5 Output Voltage Transient (mv) 5-5 =.5V, = 5V, = 1.5V Swing Frequency : 1kHz Output Current (A) Output Current (A) Time (5μs/Div) Time (5μs/Div)

9 Application Information Consideration while designing the resistance of voltage divider Refer to the Typical Application Circuit.Make sure the current sinking capability of pull-down NMOS is enough for the chosen voltage divider to pull-down the voltage at pin below.15v to shutdown the device. In addition, the capacitor C SS and voltage divider form the low-pass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. How to reduce power dissipation on Notebook PC or the dual channel DDR SDRAM application? In notebook application, using RichTek's Patent Distributed Bus Terminator Topology with choosing RichTek's product is encouraged. Distributed Bus Terminating Topology Terminator Resistor General Regulator The could also serves as a general linear regulator. The accepts an external reference voltage at pin and provides output voltage regulated to this reference voltage as shown in Figure 6, where = V x R1/(R1+R) As other linear regulator, dropout voltage and thermal issue should be specially considered. Figure 7 shows the R DS(ON) over temperature of. The minimum dropout voltage R R1 R R3 R4 R5 R6 R7 R R9 R(N) R(N+1) BUS() BUS(1) BUS() BUS(3) BUS(4) BUS(5) BUS(6) BUS(7) BUS() BUS(9) BUS(N) BUS(N+1) could be obtained by the product of R DS(ON) and output current. For thermal consideration, please refer to the relative sections. RDS(ON) (Ω) V R1 R Figure 6 R DS(ON) vs. Temperature = 5V, V = 1V Figure 7 Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the. A low ESR capacitor larger than 47uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between and the preceding power converter. Thermal Consideration regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continued operation, do not exceed absolute maximum operation junction temperature 15 C. The power dissipation definition in device is: P D = (V IN - ) x I OUT + V IN x I Q 9

10 The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( T J(MAX) T A ) / θ JA Where T J(MAX) is the maximum operation junction temperature 15 C, T A is the ambient temperature and the θ JA is the junction to ambient thermal resistance. The junction to ambient thermal resistance for SOP- package (Exposed Pad) is 6 C/W, on standard JEDEC 51-7 (4 layers, SP) thermal test board. The maximum power dissipation at T A = 5 C can be calculated by following formula: P D(MAX) = (15 C 5 C) / 6 C/W = 1.163W Figure shows the package sectional drawing of SOP- (Exposed Pad). Every package has several thermal dissipation paths. As show in Figure 9, the thermal resistance equivalent circuit of SOP- (Exposed Pad). The path is the main path due to these materials thermal conductivity. We define the exposed pad is the case point of the path. The thermal resistance θ JA of SOP- (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it s useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of SOP- package. Figure 1 show the relation between thermal resistance θ JA and copper area on a standard JEDEC 51-7 (4 layers, SP) thermal test board at T A = 5 C. We have to consider the copper couldn t stretch infinitely and avoid the tin overflow. We use the Dog-Bone copper patterns on the top layer as Figure 11. Thermal Resistance θja ( C/W) PCB Ambient Molding Compound Gold Line Die Pad Lead Frame Copper Area (mm ) Figure 1. Relation Between Thermal Resistance θ JA and Copper Area Case (Exposed Pad) Figure. SOP- (Exposed Pad) Package Sectional Drawing Exposed Pad R GOLD-LINE R LEAD FRAME R PCB path 1 W.mm Junction R DIE R DIE-ATTACH R DIE-PAD path R PCB Case (Exposed Pad) Ambient R MOLDING-COMPOUND Figure 11. Dog-Bone Layout path 3 Figure 9. Thermal Resistance Equivalent Circuit 1

11 As shown in Figure 1, the amount of copper area to which the SOP- (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP- (Exposed Pad) pad of oz. copper (Figure 1.a), θ JA is 6 C/W. Adding copper area of pad under the SOP- (Exposed Pad) (Figure 1.b) reduces the θ JA to 73 C/W. Even further, increasing the copper area of pad to 7mm (Figure 1.d) reduces the θ JA to 65 C/W. (a) Copper Area = 1mm, θ JA = 6 C/W (b) Copper Area = 3mm, θ JA = 73 C/W (c) Copper Area = 5mm, θ JA = 6 C/W (d) Copper Area = 7mm, θ JA = 65 C/W Figure 1. Thermal Resistance vs. Copper Area Layout Thermal Design 11

12 Outline Information A H M J B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I J M Lead SOP Plastic Package 1

13 A H M EXPOSED THERMAL PAD (Bottom of Package) J Y X B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I J M X Y Lead SOP (Exposed Pad) Plastic Package RICHTEK TECHNOLOGY CORP. Headquarter 5F, No., Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (63)55679 Fax: (63) RICHTEK TECHNOLOGY CORP. Taipei Office (Marketing) F-1, No. 137, Lane 35, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (6) Fax: (6) marketing@richtek.com 13