SPI Serial EEPROMs AT25128A AT25256A

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Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and (,) Data Sheet Describes Mode Operation Low-voltage and Standard-voltage Operation. (V CC =.V to.

1 Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and (,) Data Sheet Describes Mode Operation Low-voltage and Standard-voltage Operation. (V CC =.V to.v). (V CC =.V to.v) MHz Clock Rate (V) -byte Page Mode and Byte Write Operation Block Write Protection Protect /, /, or Entire Array Write Protect () Pin and Write Disable Itructio for Both Hardware and Software Data Protection Self-timed Write Cycle ( ms Max) High-reliability Endurance: Million Write Cycles Data Retention: > Years -lead PDIP, -lead EIAJ IC, -lead JEDEC IC, -lead TSP, -ball dbga and - lead Ultra Thin SAP Packages Lead-free/Halogen-free Available in Automotive Die Sales: Wafer Form, Waffle Pack, and Bumped Die SPI Serial EEPROMs K (, x ) K (, x ) ATA ATA Description The ATA/A provides,/, bits of serial electrically-erasable programmable read only memory (EEPROM) organized as,/, words of bits each. The device is optimized for use in many industrial and commercial applicatio where low-power and low-voltage operation are essential. The devices are available in space saving -lead PDIP, -lead EIAJ IC, -lead JEDEC IC, -lead TSP, -ball dbga and -lead SAP packages. In addition, the entire family is available in.v (.V to.v) and.v (.V to.v) versio. The ATA/A is enabled through the Chip Select pin () and accessed via a -wire interface coisting of Serial Data Input (), Serial Data Output (), and Serial Clock (). All programming cycles are completely self-timed, and no separate Erase cycle is required before Write. -lead PDIP -lead IC -lead TSP -lead Ultra Thin SAP Bottom View -ball dbga Bottom View

2 Table -. Pin Name NC Pin Configuratio Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input No Connect Block Write protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate Program Enable and Program Disable itructio are provided for additional data protection. Hardware data protection is provided via the pin to protect agait inadvertent write attempts to the status register. The pin may be used to suspend any serial communication without resetting the serial sequence.. Absolute Maximum Ratings* Operating Temperature... C to + C Storage Temperature... C to + C Voltage on Any Pin with Respect to Ground....V to +.V Maximum Operating Voltage....V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. DC Output Current.... ma ATA_A

3 ATA_A Figure -. Block Diagram / x Table -. Pin Capacitance () Applicable over recommended operating range from T A = C, f =. MHz, V CC = +.V (unless otherwise noted) Symbol Test Conditio Max Units Conditio C OUT Output Capacitance () pf V OUT = V C IN Input Capacitance (,,,, ) pf V IN = V Note:. This parameter is characterized and is not % tested.

4 Table -. DC Characteristics Applicable over recommended operating range from T AI = C to + C, V CC = +.V to +.V, T AE = C to + C, V CC = +.V to +.V(unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units V CC Supply Voltage.. V V CC Supply Voltage.. V V CC Supply Voltage.. V I CC I CC I CC Supply Current Supply Current Supply Current V CC =.V at MHz, = Open, Read V CC =.V at MHz, = Open, Read, Write V CC =.V at MHz, = Open, Read, Write Note:. V IL min and V IH max are reference only and are not tested. 9.. ma.. ma.. ma I SB Standby Current V CC =.V, = V CC.. µa I SB Standby Current V CC =.V, = V CC.. µa I SB Standby Current V CC =.V, = V CC.. µa I IL Input Leakage V IN = V to V CC.. µa I OL Output Leakage V IN = V to V CC, T AC = C to C.. µa V IL () V IH () Input Low-voltage. V CC x. V Input High-voltage V CC x. V CC +. V V OL Output Low-voltage I OL =. ma. V. V CC.V V OH Output High-voltage I OH =. ma V CC. V V OL Output Low-voltage I OL =. ma. V.V V CC.V V OH Output High-voltage I OH = µa V CC. V ATA_A

5 ATA_A Table -. AC Characteristics Applicable over recommended operating range from T AI = C to + C, T AE = C to + C, V CC = As Specified, CL = TTL Gate and pf (unless otherwise noted) Symbol Parameter Voltage Min Max Units f Clock Frequency MHz t RI Input Rise Time µs t FI Input Fall Time µs t WH High Time t WL Low Time t High Time t S Setup Time t H Hold Time t SU Data In Setup Time t H Data In Hold Time t HD Hold Setup Time t CD Hold Hold Time t V Output Valid t HO Output Hold Time t LZ Hold to Output Low Z

6 Table -. AC Characteristics (Continued) Applicable over recommended operating range from T AI = C to + C, T AE = C to + C, V CC = As Specified, CL = TTL Gate and pf (unless otherwise noted) Symbol Parameter Voltage Min Max Units t HZ Hold to Output High Z t DIS Output Disable Time t WC Write Cycle Time ms Endurance ().V, C, Page Mode M Write Cycles Notes:. This parameter is characterized and is not % tested. Contact Atmel for further information. ATA_A

7 ATA Ordering Information () Ordering Code Package Operation Range ATA-PU-. () ATA-PU-. () ATAN-SU-. () ATAN-SU-. () ATAW-SU-. () ATAW-SU-. () ATA-TU-. () ATA-TU-. () ATAU-UU-. () ATAY-YH-. () ATA-W.- () Notes:. For.V devices used in the.v to.v range, please refer to performance values in the AC and DC Characteristics tables.. U designates Green package + RoHS compliant. P P S S S S A A U- Y Die Sale Lead-free/Halogen-free/ Industrial Temperature ( C to C) Industrial Temperature ( C to C). Available in waffle pack and wafer form; order as SL for wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type P S S -lead,." Wide, Plastic Dual In-line Package (PDIP) -lead,." Wide, Plastic Gull Wing Small Outline Package (JEDEC IC) -lead,." Wide, Plastic Gull Wing Small Outline Package (EIAJ IC) U- -ball, die Ball Grid Array Package (dbga) A Y -lead,. mm Body, Thin Shrink Small Outline Package (TSP) -lead,. mm x.9 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) Optio. Low-voltage (.V to.v). Low-voltage (.V to.v) ATA_A

8 S JEDEC IC C E E N L TOP VIEW Ø END VIEW e b A COMMON DIMENONS (Unit of Measure = mm) D DE VIEW A SYMBOL MIN NOM MAX NOTE A.. A.. b.. C.. D.. E..99 E.9. e. BSC L.. θ Note: These drawings are for general information only. Refer to JEDEC Drawing MS-, Variation AA for proper dimeio, tolerances, datums, etc. R E. Cheyenne Mtn. Blvd. Colorado Springs, CO 9 TITLE S, -lead (." Wide Body), Plastic Gull Wing Small Outline (JEDEC IC) DRAWING NO. S REV. C ATA_A

256K (32K x 8) Paged Parallel EEPROM AT28C256

256K (32K x 8) Paged Parallel EEPROM AT28C256 Features Fast Read Access Time 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum