I2C Demonstration Board I 2 C-bus Protocol

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1 I2C Demonstration Board I 2 C-bus Protocol Oct, 2006

2 I 2 C Introduction I ² C-bus = Inter-Integrated Circuit bus Bus developed by Philips in the early 80s Simple bi-directional 2-wire bus: serial data (SDA) serial clock (SCL) Has become a worldwide industry standard and used by all major IC manufacturers Multi-master capable bus with arbitration feature Master-Slave communication; two-device only communication (generally) Each IC on the bus is identified by its own address code The slave can operate as a: receiver (slave receiver) transmitter (slave transmitter) 2

3 I 2 C-Bus Protocol Basic Start Slave Address R/W Acknowledge Stop 3

4 START and STOP Conditions Question: What is wrong with this figure? 4

5 Start and Stop Conditions Start Condition - a HIGH to LOW transition on the SDA line while SCL is HIGH Stop Condition - a LOW to HIGH transition on the SDA line while SCL is HIGH 5

6 Data Transfer Data Acknowledge During data transfer, SDA must be stable when SCL is High Each byte has to be followed by an acknowledge bit Number of bytes transmitted per transfer is unrestricted If a slave can t receive or transmit another complete byte of data, it can hold the clock line SCL LOW to force the master into a wait state 6

7 Acknowledge and Not Acknowledge The I 2 C specification says: Data transfer with acknowledge is obligatory. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. However, there are a few scenarios where there is not an acknowledge (SDA staying HIGH). Which ones? 1. A receiver with the address is not present in the I 2 C bus 2. The receiver is performing real-time tasks and it cannot process the received I 2 C information 3. The receiver is the master and wants to take control of SDA line again in order to generate a STOP command. The slave transmitter MUST then release the SDA line when it sees the NACK so the master can send the STOP command. 7

8 Key numbers to keep in mind Bit Rate (kb/s) Max Load (pf) Rise time (ns) Noise filter (ns) Standard Mode Fast Mode Fast Mode Plus High Speed Mode 0 to to to to to V DD Rise Time V IH 0.7xV DD V IL V OL GND ma Sink Current ma Sink Current (Fm+) 0.3xV DD 8

9 I 2 C Hardware architecture Pull-up resistors Typical value 2 kω to 10 kω SCL Open Drain structure (or Open Collector) Pull-down required on SDA but not on SCL 10 pf Max I/O Cap 9

10 I 2 C Pull-up Resistors How do you calculate pull up resistor values? 10

11 How to calculate I 2 C Pull-up Resistors? Minimum value There is a minimum resistor value determined by the I²C spec limit of 3 ma. R = (Vdd max Vol max )/ 0.003A Example: using a 5±0.5 V bus: R = (5.5V 0.4V)/ 0.003A = 1.7 kω Maximum value Determined by the I²C-bus rise time requirements: V(t1) = 0.3*Vdd = Vdd (1 1/e t1/rc ); then t1 = *RC V(t2) = 0.7*Vdd = Vdd (1 1/e t2/rc ); then t2 = *RC t = t2 t1 = *RC For standard-mode I²C-bus: t = rise time = 1000ns (1 μs) so RC = ns Example: at a bus load of 400 pf: R max = 2.95 kω For fast-mode: I²C-bus rise time = pf: R max = 885 Ω 11

12 μcontroller I 2 C Address, Basics I/O A/D D/A LCD RTC μcontroller II SCL SDA A 2 A 1 A 0 R/W Fixed Hardware Selectable EEPROM New devices or functions can be easily clipped on to an existing bus! Each device is addressed individually by software Unique address per device: fully fixed or with a programmable part through hardware pin(s) Programmable pins mean that several of the same devices can share the same bus Address allocation coordinated by the I 2 C-bus committee 112 different addresses max with the 7-bit format (others reserved) 10-bit format use a 2 byte message: A 9 A 8 R/W + A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 A0 A1 A2 12

13 Multi Master Mode - Clock Synchronization Master 1 Vdd Master 2 T 1 T L1 T H1 CLK 2 CLK 1 T L2, T H2 SCL T L1, T H1 T L, T H T L2 T 2 T H2 CLK1 0 CLK2 Count T L1 Counting T L1 done Wait State T L2 still counting Count T L2 Count T H1 Count T H2 Internal Counters count the Low and High times (T L1, T H1 ) and (T L2, T H2 ) 0 SCL 0 Reset Counter High T H2 Start Counting T L2 3 2 Counting TL2 done Start Counting T H2 SCL goes High 1 Counting T H1 done Start Counting T L1 SCL goes Low T L = T L2 4 Start Counting T H1 T H = T H1 2 1 Counting T H1 done Start Counting T L1 SCL goes Low 3 4 T L = longest T L = max (T L1, T L2,T Ln ) T H = shortest T H = min (T H1, T H2,T Hn ) 13

14 Multi Master Mode - Arbitration Two or more masters may generate a START condition at the same time Arbitration is done on SDA while SCL is HIGH - Slaves are not involved Master 2 loses arbitration because DATA2 SDA DATA DATA2 0 SDA 0 0 SCL 0 START SUMMARY: the master that sends a 1 while the other sends a 0 loses the arbitration 14

15 Test: I 2 C Protocol Summary START STOP DATA ACKNOWLEDGE CLOCK ARBITRATION HIGH to LOW transition on SDA while SCL is HIGH LOW to HIGH transition on SDA while SCL is HIGH 8-bit word, MSB first (Address, Control, Data) - must be stable when SCL is HIGH. - can change only when SCL is LOW. - number of bytes transmitted is unrestricted. - done on each 9 th clock pulse during the HIGH period - - the transmitter releases the bus - SDA goes HIGH. the receiver pulls DOWN the bus line - SDA goes LOW. - Generated by the master(s) - Maximum speed: ( 100, 400, 1000, 3400 khz) but NO min. - A receiver can hold SCL LOW when performing another function (transmitter in a Wait state) - A master can slow down the clock for slow devices - Master can start a transfer only if the bus is free. - Several masters can start a transfer at the same time. - Arbitration is done on SDA line - Master that lost the arbitration must stop sending data 15

16 Exercise Use switch S1 to generate an I 2 C message to the PCF

17 Exercise Objective: verify understanding of the I²C bus protocol Use switch S1 to generate an I²C message to the PCF8574 The PCF8574 address is 0x40 The PCF8574 requires one data byte The data byte should be 0xFA to turn on two of the LEDs 17

18 Exercise The following sequence should be followed: 1. Send Start condition 2. Send PCF8574 address with LSB= 0 for Write 3. Send data byte 0xFA 4. Send Stop condition 5. Don t forget the acknowledge clock pulses 18

19 Quasi Bi-directional I/O Port Structure 19

20 Quasi Bi-directional I/O Port Structure 20

21 Exercise Objective: to understand the operation of the quasi bi-directional port structure We will use the PCF8574 interface found in Win-I2CUSB Lite Checkboxes (read-only) represent state of Port pins Checked = High Unchecked = Low Press the Read button to find the state of the IO pins P6=switch connected to ground P7=switch P0-P3 control to Vcc LEDs Checked=high (LED off) Unchecked=low (LED on) Press Write button to send data to PCF8574 or use Auto Write to send automatically 21

22 Exercise 2 1. Set all the port pins high using Win-I2CUSB Lite 2. Change the state of switch 1 on S2. 3. The INT LED should illuminate 4. Change the state of the switch. The LED should turn off. 5. Turn the INT LED again by changing the switch. 6. Using Win-I2CUSB Lite. Read the PCF8574. What happened to the Interrupt? 7. Turn the INT LED again by changing the switch. Write to the PCF8574. What happened to the Interrupt? 22

23

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