CMOS VLSI Design (A3425)

Transcription

1 CMOS VLSI Design (A3425) Unit V Dynamic Logic Concept Circuits Contents Charge Leakage Charge Sharing The Dynamic RAM Cell Clocks and Synchronization Clocked-CMOS Clock Generation Circuits Communication Engineering 1

2 Introduction In the static logic circuits discussed up to this point, the output is valid so long as the inputs are well defined. A dynamic logic circuit, on the other hand, gives a result at the output that is only valid for a short period of time. If the result is not used immediately, the voltage may change in time and give an incorrect output value. Charge Sharing Another important problem that occurs in dynamic circuit is that of charge sharing. This occurs when the charge on an isolated capacitive node is used to drive another isolated capacitive node. The two capacitors C 1 and C 2 represent parasitic contributions due to the physical structure of the transistors. Suppose that initially nfet M1 is ON while M2 is in cutoff. Capacitor C 1 charges to a voltage V I =Vmax giving it a total charge of Communication Engineering 2

3 Charge Sharing Charge Sharing Suppose that the FETs are switched at time t=0, so that M1 is OFF and M2 is ON. Since there is a difference in voltage between the left and right sides of the transistor, drain current I D flows in the direction shown. This removes charge from C 1 and adds it to C 2. so that the charge is shared between the two capacitors. Since the individual charges are given by Communication Engineering 3

4 Charge Sharing We see that the current off of C 1 causes V 1 to decrease while V increases. Eventually, equilibrium is reached where the two capacitors have the same final voltage Charge Sharing The total charge in the network is now distributed according to By inspection method, V f < V max For Logic 1; C 1 > C 2 V f V max For Logic 0; C 1 < C 2 V f << V max Since the voltage difference between the two sides is zero, the current flow also goes to zero. Communication Engineering 4

5 RC Equivalent It is useful to examine the charge sharing problem by using an RC model for the MOSFET. For times t<0, the switch is open with a gate signal G=0 and the voltages are given by V 1 =V max and V 2 =0v. Closing the switch at t = 0, gives the voltage across the resistor as RC Equivalent Communication Engineering 5

6 RC Equivalent Current I through the resistor is, RC Equivalent The case where C 1 > C 2 The case where C 1 < C 2 Communication Engineering 6

7 RC Equivalent The charge sharing analysis can be extended to the case of driving multiple capacitors such as shown in fig. The Dynamic RAM cell A dynamic random-access memory (DRAM) cell is a storage circuit that consists of an access transistor MA and a storage capacitor Cs. The access FET is controlled by the Word line signal WL, and the bit line is the input/output path. The simplicity of the circuit makes it very attractive for high-density storage. there are three distinct operations for a cell: Write - A data bit is stored in the circuit; Hold - The value of the data bit is maintained in the cell; Read - The value of the data bit is transferred to an external circuit Communication Engineering 7

8 The Dynamic RAM cell The Dynamic RAM cell Write: To store a logic 1 in the cell, Vin is set to the value of V DD so that the storage cell voltage V s increases according to Storage of a logic 0 is accomplished by using an input voltage of V in = 0v so that the capacitor is discharged as described by Communication Engineering 8

9 The Dynamic RAM cell Hold: A DRAM cell holds the charge on the capacitor by turning off the access transistor using WL = 0. This creates an isolated node, and charge leakage occurs if a logic 1 high voltage is stored on C s. The maximum hold time t H for a logic 1 bit can be estimated by The Dynamic RAM cell Read: A read operation is performed When the date bit line is connected to high gain sense amplifier. Communication Engineering 9

10 The Dynamic RAM cell Read: The data voltage is given by, Voltage after charge sharing is given by, Clocks and Synchronization Data flow through a complex logic network is usually controlled by a clock signal ϕ(t). A clock voltage that has a period T in seconds that defines the time for waveform to repeat itself. The frequency f of the clock is related to the period by is the voltage associated with ϕ(t) Communication Engineering 10

11 Clocks and Synchronization Shift Registers This network is designed to move a data bit one position to the right during each half-cycle of the clock A data bit is admitted to the first stage whenϕ=1,and is transferred to stage 2 whenϕgoes to 0. Each successive bit entered into the system follows the previous bit, resulting in the movement from left to right. It is clear from the operation of the circuit that the electronic characteristics of the circuit will place some limitation on the clock frequency Communication Engineering 11

12 Shift Registers Shift Registers Communication Engineering 12

13 Shift Registers During the next portion of the clock cycle whenϕand Vϕ=0v, the pass transistor M1 is in cutoff. During this time, charge leakage will occur and the voltage V 1 across C 1 will decay from its original value of V max. The minimum value at the inverter input that will still be interpreted as a logic 1 value is V IH, so that the maximum hold time is estimated by Shift Registers We assumed a 50% duty cycle; this means that the clock has a high value for 50% of the period. As applied to the circuit This sets the maximum clock frequency as Communication Engineering 13

14 TGs as Control Elements Extension to General Clocked Systems Communication Engineering 14

15 Extension to General Clocked Systems Clocked CMOS Clocked-CMOS (C 2 MOS) is a logic family that combines static logic design with the synchronization achieved by using clock signals. The inputs A, B, and C are connected to complementary nfet/pfet pairs as in ordinary static design where they act like open or closed switches. The only modification is the insertion of two clocked FETs between the logic arrays and the output. Communication Engineering 15

16 Clocked CMOS Clocked CMOS Communication Engineering 16

17 Clocked CMOS Clocked CMOS Communication Engineering 17

18 Clocked CMOS for a logic 0 for a logic 1 Clocked CMOS Communication Engineering 18

19 Clocked CMOS Communication Engineering 19