A CMOS Multi-Gb/s 4-PAM Serial Link Transceiver*
|
|
- Carmella Higgins
- 6 years ago
- Views:
Transcription
1 A CMOS Multi-Gb/s 4-PAM Serial Link Transceiver* March 11, 1999 Ramin Farjad-Rad Center for Integrated Systems Stanford University Stanford, CA *Funding from LSI Logic, SUN Microsystems, and Powell foundation jeihgfdcbabakl
2 Goals R TERM R TERM Timing Recovery Tx Copper cable Rx Networking high-speed (5-10Gbps) systems for ranges up to 10 meters at lower cost and complexity Parallel buses are costly for long distances. Optical fibers are not beneficial for such small ranges. Serial links on copper cables are an attractive solution for this kind of application. Push bandwidth limitations of CMOS serial links CMOS technology is getting cheaper, faster, and more available. Integrate more digital functions on-chip.
3 Outline Challenges System Architecture Circuit Implementation Test Results Conclusion
4 Challenges: Interconnection Bandwidth Frequency-dependent attenuation in electrical links due to skin effect resistance and dielectric loss. The -3dB BW of 10-meter PE-142 coax is ~1.0GHz. 1 Frequency Response 0.9 Amplitude(V) Frequency(Hz)
5 Challenges: Interconnection Bandwidth Frequency-dependent attenuation causes ISI. Only channel eigen-waveforms result in no ISI. Generation and detection of true eigen-waveforms is not feasible due to circuit limitations at high frequencies. Trapezoidal pulses are instead used as basis waveforms. Higher symbol rate results in more ISI. 1 Amplitude(V) Transmitted Ideal pulse Pulse Cable pulse Pulse Response response ISI ISI Time(ns)
6 Challenges: Data Generation/Detection Hard to operate CMOS circuits at directly multi-ghz speeds Better to reduce the on-chip frequency Recovering embedded timing information from the serial data Data stream Large frequency variations of on-chip oscillators and small frequency capture range of phase detectors Data detection at high speeds Input voltage offset, cross-talk, and signal reflection (reflection ISI) limits the minimum detectable signal.
7 Outline Challenges System Architecture Circuit Implementation Test Results Conclusion
8 Reduction of On-Chip Frequency Multiplexing (N :1) and demultiplexing (1:N) the high-speed data at the transmission line* Reduces the on-chip frequency by a factor of N 5G For example: N = 5 => (for 5Gsym/s) f ck = = 1GHz 5 Max switching speed of the process is the limit CMOS provides high-speed transistor switches Transmitter Drivers (f ck ) ckt0 ckr0 (f ck ) ckt1 ckt2 ckt3 ckt4 Transmission line High-speed data (Nxf ck ) ckr1 ckr2 ckr3 ckr4 Receiver Detectors Multiplexer Demultiplexer *C-K. Yang, R. Farjad, M. Horowitz, VLSI Symp. 97
9 Proposed Modulation 4-PAM is used for data communication in the serial link Symbol rate reduces to half that of binary transmission. Lower symbol rate reduces ISI and on-chip clock frequency. Higher level PAM was not used because of: limited transmitter swing, minimum detectable signal and reflection ISI. 4Sym-->5Sym conversion guarantees clock recovery Gray code mapping of levels reduces BER by 25% vs. linear mapping 2 bits error Only 1 bit error Linear Gray 01 00
10 Proposed Architecture to Combat ISI To cancel the long tail of pulse response, a pre-emphasis symbol-spaced 2-tap FIR filter is implemented at the transmitter: Vo( n) = Vi( n) a Vi( n 1) b Vi( n 2) To sharpen the signal transition edges, a half-symbol-spaced 1-tap high-pass equalizer is implemented at the receiver 1 Veq( n) = Vi( n) α Vi n Shaped transmitted wave Received signal Equalized signal Pulse response Pre emphasized transmitted wave Received signal equalized signal Pulse response (no filtering) Amplitude(V) a b Time(ns)
11 Receiver Equalizer The half-symbol-spaced filter boosts frequency components up to f = Ts R=5Gsym/s T s =200ps f max =5GHz -f max f max Sharpening the transitions increases the eye opening width. =>Less sensitive to sampling phase errors. Slow transition Sharp transition
12 Outline Challenges System Architecture Circuit Implementation Test Results Conclusion
13 Top Level Architecture 10 Analog TX PLL 5:1 Multiplexer/Serializer 2-b DAC & Filter Serial 4-PAM Analog RX VCO 1:5 Demultiplexer Sampler & Equalizer 2-b ADC Bank 10 Ph/Fr Detector Filter V ctl
14 5:1 Multiplexing Transmitter Sym4 Sym0 Sym1 Sym2 Sym3 Ring Oscillator ck0 ck1 ck2 ck3 ck4 Sym0 R TERM R TERM CLK 0 D[0:1] (valid for Sym0) D D Out Outb CLK 1 Ts Clk 0 Clk 0 x 5 Clk 1 Each symbol is generated by the rising and falling egdes of two phases of clock
15 2-bit Output Driver Dout Dout D Dout Dout D D Clk 0 x2 Leg x1 Leg Clk 0 Clk 0 DoDo Clk0 Clk1 D1D1 tail Clk 1 Vdd Clk1 2-bit DAC module Differential drive leg
16 4-PAM Preshaping 5:1 Multiplexer clk0 clk1 clk2 data 2-b DAC Delay 2-b DAC,T1 Delay 2-b DAC,T2 clk1 clk2 clk3 data 2-b DAC Delay 2-b DAC,T1 Delay To 3 Other Drivers b DAC,T2 a b External Sources Multiplexer Drivers & 2-Tap Filters Each driver generates a filtered symbol independent of other drivers. Simple architecture to implement the filter. t
17 Symbol Generation Tap2 stream S2,T2 S3,T2 S4,T2 S0,T2 S1,T2 Tap1 stream S3,T1 S4,T1 S0,T1 S1,T1 S2,T1 Main stream Sym4 Sym0 Sym1 Sym2 Sym3 the output Main Pulse CLK 1 CLK 2 Ts D[0:1] (valid for Sym0) Delayed versions of D[0:1] D[0:1] (Ts delayed for T1) D[0:1] (2Ts delayed for T2) Tap-Drivers timing
18 Symbol-Width Problem Variations in PMOS to NMOS strength ratio result in duty cycle error in the clocks (unbalanced falling & rising times) The effective width of the final output symbol decreases.
19 Pulse-Width Control Loop To 4 other drivers D driver1 dummy T s Va Vb dummy Ck Buf D Ctl + - Ck Buf D Vdd D Ck1,2 Vdd Ck1,2 Ctl Vb Va (Wide Pulses) Vb Va (Narrow Pulses) t
20 Receiver Timing Recovery Din Pre_amplifier Clock Generator/ VCO samp_ck Phase Detector/ Receiver ctrl Filter PLL Dout Data Sample Clock Oversampling phase detection Many input samplers, Phase quantization error, Complex logic. timing margin Tracking phase detection Conventional bang-bang control: Low loop bandwidth and capture range Proportional control: Desirable
21 Top Level Architecture 10 Analog TX PLL 5:1 Multiplexer/Serializer 2-b DAC & Filter Serial 4-PAM Analog RX VCO 1:5 Demultiplexer Sampler & Equalizer 2-b ADC Bank 10 Ph/Fr Detector Filter V ctl
22 Timing Recovery: Front-end Multi-Φ Clocks 4-PAM Input (differential) Ck0 Ck1 Ck2 Ck3 S o0 S o1 S o2 S o3 2-bit ADC linear amp 2-bit ADC linear amp S e1 d0,1 d2,3 S e3 Simplified receiver front-end (x2 oversampling)
23 Proposed Proportional Phase Detection φ Clock Lags 1 1 S e = k. φ S e <0 S e >0 0 0 (1-->0) => -(S e ) > 0 (0-->1) => +(S e ) > 0 Speed clock Advantages: Larger PLL bandwidth and stability compared to bang-bang PLLs. Zero systematic phase offset (same detection mechanism for edges and data). Zero ripple on control voltage of PLL (unlike bang-bang). Disadvantage: Voltage offsets of edge samplers translate into phase error.
24 Three 4-PAM Transitions type1 type2 type2 type3 type1 Differential 4-PAM input Sampling edges (in lock) 1) Right crossing 2) Misplaced crossing 3) No crossing Only type1 transitions are used for clock recovery Transitions type2 and type3 are ignored by a decision logic
25 Data Phase Detector Data phase detector S e1 + - decision logic To input samplers S e3 + - d2,3 d4,5 Charge pump Loop filter d0,1 d2,3 Analog RX VCO S e9 + - V P d8,9 d0,1 Edge sample values, S e, of type1 are summed with correct polarity at phase detector output (V P )
26 Frequency Acquisition A frequency acquisition aid solves the small capture range problem of the data-recovery phase detector The frequency acquisition circuit sets the proper oscillation frequency before phase locking starts Data Phase Det V Q =0 ; f data -f ck > f V Q =1 ; f data -f ck < f << f capture f data -f ck LPF1 V P f CK VCO V Q Freq. Monitor LPF2 V Q CK ref Freq. Det
27 Frequency Monitor 1 V Q D Q f data -f ck Vp Edge detector C OneShot V O R Reset
28 Top Level Architecture 10 Analog TX PLL 5:1 Multiplexer/Serializer 2-b DAC & Filter Serial 4-PAM Analog RX VCO 1:5 Demultiplexer Sampler & Equalizer 2-b ADC Bank 10 Ph/Fr Detector Filter V ctl
29 1:5 Demultiplexing Samplers and Equalizers Multi-Φ Clocks 4-PAM Input differential Tap weight Ck 0 Ck 1 Ck 2 Ck 3 S 0 x S 1 x S 2 x S 3 Σ Σ Σ Σ Ck 0 Ck 1 Ck 2 Ck 3 2-bit ADC S o0 S o1 linear amp S o2 2-bit ADC linear amp S o3 1-tap Equalizer: So 1 = S 1 - α*s 0 5 Samplers for the symbol centers and 5 samplers for transitions (x2 oversampling). Each equalizer uses the present and half a symbol earlier sample (half symbol spaced)
30 Half-symbol-Spaced 1-tap Equalizer I O1 = I 1 - α I 0 α*-i 0 S O1 = S 1 - α S 0 Analog 1-tap equalizer I 1 I O1 S On1 S Op1 S n0 S p0 S p1 S n1 Tap weight (α) Equalization function should be performed very fast Subtraction is done by summing the currents, which are proportional to the sampled values with opposite polarity. Differential pairs should have a large linear range for proper operation of analog equalization.
31 Input Preamplifier I D V GS I D = k.(v GS -V t ) Vip Von Vop Vin I D Vsrc Vsrc Linear V o Linear V GS Short-channel MOS has a linear I D -V GS characteristic in saturation region Vsrc should be set such that V o -V i is linear for all values of Vi. (V i -V src )
32 Differential 4-PAM Level detection + a2 - + a1 - + a0 - V ref Vin Vip Flash detection: Three comparators to detect the 4 levels. Differential signaling: Only one reference voltage is required +Vref 0 -Vref Data levels
33 Input 2-bit ADC Vref ref + Comp ref Comp. Comp. a2 a1 a0 Gray decoder A0 A1 Preamplifier & Equalizer SR-Latch Regenerative amp V n V p a2b Vo + Vref Decode logic a0 a2 a1 A0 A1 Vin clk0 clk1 Vip Vin clk0 Vip Vsrc
34 Outline Challenges System Architecture Implementation Test Results Conclusion
35 Modeling The Cable Oscilloscope tr~40p TDR => non-ideal pulse response DSP => Ideal impulse response Convolution => Cable real symbol response * = SPICE (Xmitter) Matlab (Cable) Matlab (Equalizer) SPICE models for skin effect are not ideal, need a better model: Directly measure the cable impulse response (time domain) Convolve it with the transmitted symbols
36 Simulated Eye Diagrams Amplitude (V) a) Amplitude (V) b) τ v time (ns) time (ns) c) 1 (a) Eye diagram after cable (Without pre-emphasis) (b) Eye diagram after cable (With pre-emphasis) (c) Eye diagram after cable (With pre-emphasis/equalization) Amplitude (V) τ time (ns) v
37 0.35-µm Transmitter Die Photo 4-PAM FIR Xmitter Analog TX PLL Ck Buf Resync. PRBS Enc. SRAM Total die area: 2mm x 1.5mm 4-PAM FIR transmitter: 0.8mm x 0.3mm
38 Measured Eye Diagrams a) b) c) (a) 10Gb/s eye diagram at source (No pre-emphasis) (b) 10Gb/s eye diagram after the cable (With Pre-emphasis) (c) 8Gb/s Eye diagram after the cable (With pre-emphasis)
39 0.35-µm Transmitter Performance Transmitter Data Rate Eye Height Eye Width 10Gb/s, 10meter, W/ Pre-emphasis 200mV 90ps - 70ps 10Gb/s, 10meter, No Pre-emphasis 0 0 8Gb/s, 10meter, W/ Pre-emphasis 350mV 110ps - 90ps 8Gb/s, 10meter, No Pre-emphasis < 60mV < 50ps Transmitter Output Jitter: Peak to peak 32ps RMS 8ps 10Gb/s (5Gsym/s): Analog 0.7watts Output Driver 0.5watts Sync/Logic 0.3watts Total 1.5watts
40 0.3-µm Full Transceiver Die Photo 4-PAM FIR Xmitter Analog bypass cap TX PLL RX PLL Samplers & Phase detector Resync PRBS dec. Resync PRBS Enc. SRAM Digital bypass cap Total die area: 2mm x 2mm Total receiver data recovery section: 0.85mm x 0.43mm
41 0.3-µm Transceiver Performance Maximum link speed Transmitter output 8Gbps Receiver PLL 3V 11ps (peak-peak), 2ps (rms) 28ps (peak-peak), 4ps (rms) Receiver PLL dynamics BW > 30MHz, Ph.m. > 48 Receiver PLL capture range Min. input swing to capture lock Min. input swing to maintain lock ~ 20MHz ±400mV (diff.) ±300mV (diff.) Power 8Gb/s, 3V Analog: 750mW 4-PAM driver: 220mW Other: 130mW Total: 1.1W
42 BER Measurements PRBS Gen. Xmitter encoder on-chip Driver Ck1 Ck2 Clock Gen. At 8Gbps: BER ~ 10-7, Window = 50ps Sampler (almost no improvement with input equalizer) At 6Gbps: BER ~ 10-14, Window = 150ps (30ps improvement with input equalizer) Receiver encode frm det on-chip PRBS decode Freq. Counter Possible factors for lower BER at high speeds: - Line Reflection: Bad on-chip terminations, package/bondwire - EMI from neighboring high-speed bondwires
43 Contributions A solution for multi-gbps transmission over bandwidth-limited cables in standard CMOS technology: Transmitter: A high-speed 4-PAM DAC design to reduce the symbol rate to half (v.s. 2-PAM). A FIR preshaping filter to perform at multi-gbps rates with very low complexity. A control circuit to optimize the width of the transmitted symbols. Receiver: An analog FIR equalizer effective up to multi-ghz ranges in CMOS technology. A new proportional data-recovery phase detector for detecting 4-PAM serial data. A new frequency-acquisition technique for data-recovery PLLs. A 4-PAM transceiver capable of data transmission up to 8 Gbps over 10-m copper cable with BW~1GHz in 0.3-µm CMOS technology.
44 Acknowledgments
45 Future Work Use higher-level N-PAM modulation Challenge: Very fast ADCs and DACs with higher resolution. Explore general methods of N-PAM data recovery. Advanced communication methods for narrow-band channels: Channel eigen function as transmission symbol. Maximum likelihood detection (ML) Multi-Carrier techniques (e.g DMT in ADSL) Use coding methods to reduce BER.
46 Frequency Monitor 1 D Q V Q f data -f ck Vp Edge detector C OneShot V O R Reset W 2W W Level Converter ECL to CMOS delay in+ in- Hysteresis edge detector
47 Analog Supply Drop Vdda Vdd Gnd Gnda Analog The on-chip VCOs speed was limited to 800MHz (8Gbps) due to analog supply drop Analog supply traces has ~1.8Ω resistance in series. - Only one pin for Vdda or Gnda 250mA analog supply current at 8Gbps => ~0.45V drop on analog supply!
A 0.3-m CMOS 8-Gb/s 4-PAM Serial Link Transceiver
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 5, MAY 2000 757 A 0.3-m CMOS 8-Gb/s 4-PAM Serial Link Transceiver Ramin Farjad-Rad, Student Member, IEEE, Chih-Kong Ken Yang, Member, IEEE, Mark A. Horowitz,
More information5Gbps Serial Link Transmitter with Pre-emphasis
Gbps Serial Link Transmitter with Pre-emphasis Chih-Hsien Lin, Chung-Hong Wang and Shyh-Jye Jou Department of Electrical Engineering,National Central University,Chung-Li, Taiwan R.O.C. Abstract- High-speed
More informationAPPLICATIONS such as computer-to-computer or
580 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999 A 0.4- m CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter Ramin Farjad-Rad, Student Member, IEEE, Chih-Kong Ken Yang, Member, IEEE,
More informationECEN 720 High-Speed Links Circuits and Systems
1 ECEN 720 High-Speed Links Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by transmitters.
More informationECEN 720 High-Speed Links: Circuits and Systems
1 ECEN 720 High-Speed Links: Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by
More informationLecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1
Lecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1 LECTURE 160 CDR EXAMPLES INTRODUCTION Objective The objective of this presentation is: 1.) Show two examples of clock and data recovery
More informationECEN720: High-Speed Links Circuits and Systems Spring 2017
ECEN720: High-Speed Links Circuits and Systems Spring 2017 Lecture 12: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project Preliminary Report #2 due Apr. 20 Expand
More informationA 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a, Wang Zhengchen b, Gui Xiaoyan c,
4th International Conference on Computer, Mechatronics, Control and Electronic Engineering (ICCMCEE 2015) A 5-Gb/s 156-mW Transceiver with FFE/Analog Equalizer in 90-nm CMOS Technology Wang Xinghua a,
More informationECEN620: Network Theory Broadband Circuit Design Fall 2012
ECEN620: Network Theory Broadband Circuit Design Fall 2012 Lecture 20: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam 2 is on Friday Nov. 9 One double-sided 8.5x11
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 16: CDRs Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project descriptions are posted on the website Preliminary
More information6.976 High Speed Communication Circuits and Systems Lecture 21 MSK Modulation and Clock and Data Recovery Circuits
6.976 High Speed Communication Circuits and Systems Lecture 21 MSK Modulation and Clock and Data Recovery Circuits Michael Perrott Massachusetts Institute of Technology Copyright 2003 by Michael H. Perrott
More informationA 0.18µm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems
A 0.18µm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems M. Meghelli 1, A. Rylyakov 1, S. J. Zier 2, M. Sorna 2, D. Friedman 1 1 IBM T. J. Watson Research Center 2 IBM
More informationTo learn fundamentals of high speed I/O link equalization techniques.
1 ECEN 720 High-Speed Links: Circuits and Systems Lab5 Equalization Circuits Objective To learn fundamentals of high speed I/O link equalization techniques. Introduction An ideal cable could propagate
More informationISSCC 2006 / SESSION 13 / OPTICAL COMMUNICATION / 13.2
13.2 An MLSE Receiver for Electronic-Dispersion Compensation of OC-192 Fiber Links Hyeon-min Bae 1, Jonathan Ashbrook 1, Jinki Park 1, Naresh Shanbhag 2, Andrew Singer 2, Sanjiv Chopra 1 1 Intersymbol
More informationDesign and Implementation of High-Speed CMOS Clock and Data Recovery Circuit for Optical Interconnection Applications. Seong-Jun Song. Dec.
MS Thesis esign and Implementation of High-Speed CMOS Clock and ata Recovery Circuit for Optical Interconnection Applications Seong-Jun Song ec. 20, 2002 oratory, epartment of Electrical Engineering and
More informationThis chapter discusses the design issues related to the CDR architectures. The
Chapter 2 Clock and Data Recovery Architectures 2.1 Principle of Operation This chapter discusses the design issues related to the CDR architectures. The bang-bang CDR architectures have recently found
More informationCircuit Design for a 2.2 GByte/s Memory Interface
Circuit Design for a 2.2 GByte/s Memory Interface Stefanos Sidiropoulos Work done at Rambus Inc with A. Abhyankar, C. Chen, K. Chang, TJ Chin, N. Hays, J. Kim, Y. Li, G. Tsang, A. Wong, D. Stark Increasing
More informationHigh-Performance Electrical Signaling
High-Performance Electrical Signaling William J. Dally 1, Ming-Ju Edward Lee 1, Fu-Tai An 1, John Poulton 2, and Steve Tell 2 Abstract This paper reviews the technology of high-performance electrical signaling
More informationECEN 720 High-Speed Links: Circuits and Systems. Lab3 Transmitter Circuits. Objective. Introduction. Transmitter Automatic Termination Adjustment
1 ECEN 720 High-Speed Links: Circuits and Systems Lab3 Transmitter Circuits Objective To learn fundamentals of transmitter and receiver circuits. Introduction Transmitters are used to pass data stream
More informationHigh-Speed Circuits and Systems Laboratory B.M.Yu. High-Speed Circuits and Systems Lab.
High-Speed Circuits and Systems Laboratory B.M.Yu 1 Content 1. Introduction 2. Pre-emphasis 1. Amplitude pre-emphasis 2. Phase pre-emphasis 3. Circuit implantation 4. Result 5. Conclusion 2 Introduction
More informationChoosing Loop Bandwidth for PLLs
Choosing Loop Bandwidth for PLLs Timothy Toroni SVA Signal Path Solutions April 2012 1 Phase Noise (dbc/hz) Choosing a PLL/VCO Optimized Loop Bandwidth Starting point for setting the loop bandwidth is
More informationA 4 GSample/s 8-bit ADC in. Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California
A 4 GSample/s 8-bit ADC in 0.35 µm CMOS Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California 1 Outline Background Chip Architecture
More information10.1: A 4 GSample/s 8b ADC in 0.35-um CMOS
10.1: A 4 GSample/s 8b ADC in 0.35-um CMOS Ken Poulton, Robert Neff, Art Muto, Wei Liu*, Andy Burstein**, Mehrdad Heshami*** Agilent Technologies, Palo Alto, CA *Agilent Technologies, Colorado Springs,
More informationCS 250 VLSI System Design
CS 250 VLSI System Design Lecture 13 High-Speed I/O 2009-10-8 John Wawrzynek and Krste Asanovic with John Lazzaro TA: Yunsup Lee www-inst.eecs.berkeley.edu/~cs250/ 1 Acknowledgment: Figures and data in
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements
More informationDedication. To Mum and Dad
Dedication To Mum and Dad Acknowledgment Table of Contents List of Tables List of Figures A B A B 0 1 B A List of Abbreviations Abstract Chapter1 1 Introduction 1.1. Motivation Figure 1. 1 The relative
More informationA Phase-Locked Loop with Embedded Analog-to-Digital Converter for Digital Control
A Phase-Locked Loop with Embedded Analog-to-Digital Converter for Digital Control Sooho Cha, Chunseok Jeong, and Changsik Yoo A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2
More informationA 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit for Backplane Interface
Proceedings of the 5th WSEAS Int. Conf. on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL & SIGNAL PROCESSING, Dallas, USA, November 1-3, 2006 225 A 10Gbps Analog Adaptive Equalizer and Pulse Shaping Circuit
More informationLow-Power Pipelined ADC Design for Wireless LANs
Low-Power Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación,
More informationA 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2016.16.3.287 ISSN(Online) 2233-4866 A 10-Gb/s Multiphase Clock and Data Recovery
More informationA Serial Link Transceiver Based on 8 GSa/s A/D and D/A Converters
A Serial Link Transceiver Based on 8 GSa/s A/D and D/A Converters in 0.25µm m CMOS William Ellersick 1,3, Chih-Kong Ken Yang 2 Vladimir Stojanovic 1, Siamak Modjtahedi 2, Mark A. Horowitz 1 1 Stanford
More informationEE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces. Outline
EE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture #7 Components Termination, Transmitters & Receivers Jared Zerbe 2/10/04 Outline General issues Termination
More informationAbstract. High-Speed Transceiver Design in CMOS using Multilevel (4-PAM) Signaling.
Abstract JOSEPH, BALU High-Speed Transceiver Design in CMOS using Multilevel (4-PAM) Signaling. (Under the direction of Dr. Wentai Liu) The design of a 4 Gbps serial link transceiver in 0.35µm CMOS process
More informationThe Practical Limitations of S Parameter Measurements and the Impact on Time- Domain Simulations of High Speed Interconnects
The Practical Limitations of S Parameter Measurements and the Impact on Time- Domain Simulations of High Speed Interconnects Dennis Poulin Anritsu Company Slide 1 Outline PSU Signal Integrity Symposium
More informationA 5Gbit/s CMOS Clock and Data Recovery Circuit
A 5Gbit/s CMOS Clock and Data Recovery Circuit Author Kok-Siang, Tan, Sulainian, Mohd Shahian, Soon-Hwei, Tan, I Reaz, Mamun, Mohd-Yasin, F. Published 2005 Conference Title 2005 IEEE Conference on Electron
More informationA Serial Link Transceiver Based on 8 GSa/s A/D and D/A Converters
A Serial Link Transceiver Based on 8 GSa/s A/D and D/A Converters in 0.25µm m CMOS William Ellersick 1,3, Chih-Kong Ken Yang 2 Vladimir Stojanovic 1, Siamak Modjtahedi 2, Mark A. Horowitz 1 1 Stanford
More informationHIGH-SPEED LOW-POWER ON-CHIP GLOBAL SIGNALING DESIGN OVERVIEW. Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray
HIGH-SPEED LOW-POWER ON-CHIP GLOBAL SIGNALING DESIGN OVERVIEW Xi Chen, John Wilson, John Poulton, Rizwan Bashirullah, Tom Gray Agenda Problems of On-chip Global Signaling Channel Design Considerations
More informationMulti-gigabit signaling with CMOS
Multi-gigabit signaling with CMOS William J. Dally - Massachusetts Institute of Technology John Poulton - University of North Carolina @ Chapel Hill Steve Tell - University of North Carolina @ Chapel Hill
More informationA 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection
A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection Somnath Kundu 1, Bongjin Kim 1,2, Chris H. Kim 1 1
More informationIntroduction to CMOS RF Integrated Circuits Design
VI. Phase-Locked Loops VI-1 Outline Introduction Basic Feedback Loop Theory Circuit Implementation VI-2 What is a PLL? A PLL is a negative feedback system where an oscillatorgenerated signal is phase and
More informationBER-optimal ADC for Serial Links
BER-optimal ADC for Serial Links Speaker Name: Yingyan Lin Co-authors: Min-Sun Keel, Adam Faust, Aolin Xu, Naresh R. Shanbhag, Elyse Rosenbaum, and Andrew Singer Advisor s name: Naresh R. Shanbhag Affiliation:
More informationHigh-Speed Links. Agenda : High Speed Links
High-Speed Links Vladimir Stojanovic (with slides from M. Horowitz, J. Zerbe, K.Yang and W. Ellersick) EE371 Lecture 16 Agenda : High Speed Links High-Speed Links, What,Where? Signaling Faster - Evolution»
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 6: RX Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 4 Prelab due now Exam
More information9-Bit, 30 MSPS ADC AD9049 REV. 0. Figure 1. Typical Connections FUNCTIONAL BLOCK DIAGRAM
a FEATURES Low Power: 00 mw On-Chip T/H, Reference Single +5 V Power Supply Operation Selectable 5 V or V Logic I/O Wide Dynamic Performance APPLICATIONS Digital Communications Professional Video Medical
More information10-Bit, 40 MSPS/60 MSPS A/D Converter AD9050 REV. B. Figure 1. Typical Connections FUNCTIONAL BLOCK DIAGRAM
a FEATURES Low Power: 1 mw @ 0 MSPS, mw @ 0 MSPS On-Chip T/H, Reference Single + V Power Supply Operation Selectable V or V Logic I/O SNR: db Minimum at MHz w/0 MSPS APPLICATIONS Medical Imaging Instrumentation
More informationPhil Lehwalder ECE526 Summer 2011 Dr. Chiang
Phil Lehwalder ECE526 Summer 2011 Dr. Chiang PLL (Phase Lock Loop) Dynamic system that produces a clock in response to the frequency and phase of an input clock by varying frequency of an internal oscillator.
More informationDesign And Simulation Of First Order Sigma Delta ADC In 0.13um CMOS Technology Jaydip H. Chaudhari PG Student L. C. Institute of Technology, Bhandu
Design And Simulation Of First Order Sigma Delta ADC In 0.13um CMOS Technology Jaydip H. Chaudhari PG Student L. C. Institute of Technology, Bhandu Gireeja D. Amin Assistant Professor L. C. Institute of
More informationA Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation
WA 17.6: A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos 1, Mark Horowitz 1 Computer Systems Laboratory, Stanford
More informationFundamentals of Data Converters. DAVID KRESS Director of Technical Marketing
Fundamentals of Data Converters DAVID KRESS Director of Technical Marketing 9/14/2016 Analog to Electronic Signal Processing Sensor (INPUT) Amp Converter Digital Processor Actuator (OUTPUT) Amp Converter
More informationLecture 15: Transmitter and Receiver Design
Lecture 15: Transmitter and Receiver Design Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 2000 by Mark Horowitz EE371 Lecture 15-1 Horowitz Outline System Architectures
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 0 Lecture 8: RX FIR, CTLE, & DFE Equalization Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam is
More informationISSCC 2006 / SESSION 4 / GIGABIT TRANSCEIVERS / 4.1
SSCC 006 / SESSON 4 / GGABT TRANSCEVERS / 4. 4. A 0Gb/s 5-Tap-/4-Tap-FFE Transceiver in 90nm CMOS M. Meghelli, S. Rylov, J. Bulzacchelli, W. Rhee, A. Rylyakov, H. Ainspan, B. Parker, M. Beakes, A. Chung,
More informationA Compact, Low-Power Low- Jitter Digital PLL. Amr Fahim Qualcomm, Inc.
A Compact, Low-Power Low- Jitter Digital PLL Amr Fahim Qualcomm, Inc. 1 Outline Introduction & Motivation Digital PLL Architectures Proposed DPLL Architecture Analysis of DPLL DPLL Adaptive Algorithm DPLL
More informationTransmitter Equalization for 4Gb/s Signalling
Transmitter Equalization for 4Gb/s Signalling William J. Dally Artificial Intelligence Laboratory Massachusetts Institute of Technology billd@ai.mit.edu John Poulton Microelectronic Systems Laboratory
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2010
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 010 Lecture 7: PLL Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Project Preliminary Report
More informationDigital PWM IC Control Technology and Issues
Digital PWM IC Control Technology and Issues Prof. Seth R. Sanders (sanders@eecs.berkeley.edu) Angel V. Peterchev Jinwen Xiao Jianhui Zhang EECS Department University of California, Berkeley Digital Control
More informationECEN 620: Network Theory Broadband Circuit Design Fall 2012
ECEN 620: Network Theory Broadband Circuit Design Fall 2012 Lecture 23: High-Speed I/O Overview Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Exam 3 is postponed to Dec. 11
More informationMultiple Reference Clock Generator
A White Paper Presented by IPextreme Multiple Reference Clock Generator Digitial IP for Clock Synthesis August 2007 IPextreme, Inc. This paper explains the concept behind the Multiple Reference Clock Generator
More informationA Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage
International Journal of Engineering & Technology IJET-IJENS Vol:14 No:04 75 A Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage Mohamed A. Ahmed, Heba A. Shawkey, Hamed A. Elsemary,
More information26.8: A 1.9GHz Single-Chip CMOS PHS Cellphone
26.8: A 1.9GHz Single-Chip CMOS PHS Cellphone William W. Si, Srenik Mehta, Hirad Samavati, Manolis Terrovitis, Michael Mack, KeithOnodera, SteveJen, Susan Luschas, Justin Hwang, SuniMendis, DavidSu, BruceWooley
More information20Gb/s 0.13um CMOS Serial Link
20Gb/s 0.13um CMOS Serial Link Patrick Chiang (pchiang@stanford.edu) Bill Dally (billd@csl.stanford.edu) Ming-Ju Edward Lee (ed@velio.com) Computer Systems Laboratory Stanford University Stanford University
More informationEE290C - Spring 2004 Advanced Topics in Circuit Design High-Speed Electrical Interfaces. Announcements
EE290C - Spring 04 Advanced Topics in Circuit Design High-Speed Electrical Interfaces Lecture 11 Components Phase-Locked Loops Viterbi Decoder Borivoje Nikolic March 2, 04. Announcements Homework #2 due
More informationDecoupling Technique for Reducing Sensitivity of Differential Pairs to Power-Supply-Induced Jitter
Decoupling Technique for Reducing Sensitivity of Differential Pairs to Power-Supply-Induced Jitter John McNeill Vladimir Zlatkovic David Bowler Lawrence M. DeVito ANALOG DEVICES Application Presentation
More informationA Fully Integrated 20 Gb/s Optoelectronic Transceiver Implemented in a Standard
A Fully Integrated 20 Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13 µm CMOS SOI Technology School of Electrical and Electronic Engineering Yonsei University 이슬아 1. Introduction 2. Architecture
More informationSource Coding and Pre-emphasis for Double-Edged Pulse width Modulation Serial Communication
Source Coding and Pre-emphasis for Double-Edged Pulse width Modulation Serial Communication Abstract: Double-edged pulse width modulation (DPWM) is less sensitive to frequency-dependent losses in electrical
More informationCascaded Noise-Shaping Modulators for Oversampled Data Conversion
Cascaded Noise-Shaping Modulators for Oversampled Data Conversion Bruce A. Wooley Stanford University B. Wooley, Stanford, 2004 1 Outline Oversampling modulators for A/D conversion Cascaded noise-shaping
More informationCLOCK AND DATA RECOVERY (CDR) circuits incorporating
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 1571 Brief Papers Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits Jri Lee, Member, IEEE, Kenneth S. Kundert, and
More informationA 2-byte Parallel 1.25 Gb/s Interconnect I/O Interface with Self-configurable Link and Plesiochronous Clocking
UDC 621.3.049.771.14:681.3.01 A 2-byte Parallel 1.25 Gb/s Interconnect I/O Interface with Self-configurable Link and Plesiochronous Clocking VKohtaroh Gotoh VHideki Takauchi VHirotaka Tamura (Manuscript
More informationShort Course On Phase-Locked Loops and Their Applications Day 5, AM Lecture. Advanced PLL Examples (Part I)
Short Course On Phase-Locked Loops and Their Applications Day 5, AM Lecture Advanced PLL Examples (Part I) Michael Perrott August 15, 2008 Copyright 2008 by Michael H. Perrott All rights reserved. Outline
More information2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
19-262; Rev ; 5/1 2.5Gbps, +3.3V Clock and Data Retiming ICs General Description The are compact, low-power clock recovery and data retiming ICs for 2.488Gbps SONET/ SDH applications. The fully integrated
More informationXR FSK Modem Filter FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION FEATURES ORDERING INFORMATION APPLICATIONS SYSTEM DESCRIPTION
FSK Modem Filter GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM The XR-2103 is a Monolithic Switched-Capacitor Filter designed to perform the complete filtering function necessary for a Bell 103 Compatible
More informationA 0.18µm CMOS Gb/s Digitally Controlled Adaptive Line Equalizer with Feed-Forward Swing Control for Backplane Serial Link
1 A 0.18µm CMOS 3.125-Gb/s Digitally Controlled Adaptive Line Equalizer with Feed-Forward Swing Control for Backplane Serial Link Ki-Hyuk Lee, Jae-Wook Lee nonmembers and Woo-Young Choi regular member
More informationStatistical Link Modeling
April 26, 2018 Wendem Beyene UIUC ECE 546 Statistical Link Modeling Review of Basic Techniques What is a High-Speed Link? 1011...001 TX Channel RX 1011...001 Clock Clock Three basic building blocks: Transmitter,
More information3Gb/s CMOS Adaptive Equalizer for Backplane Serial Links
3Gb/s CMOS Adaptive Equalizer for Backplane Serial Links JaeWook Lee and WooYoung Choi Department of Electrical and Electronic Engineering, Yonsei University patima@tera.yonsei.ac.kr Abstract A new line
More informationPhase-Locked Loops and Their Applications. Advanced PLL Examples (Part II)
Short Course On Phase-Locked Loops and Their Applications Day 5, PM Lecture Advanced PLL Examples (Part II) Michael Perrott August 15, 2008 Copyright 2008 by Michael H. Perrott All rights reserved. Outline
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN620: Network Theory Broadband Circuit Design Fall 2014 Lecture 8: Charge Pump Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda HW2 is due Oct 6 Exam 1 is
More information20 GHz Low Power QVCO and De-skew Techniques in 0.13µm Digital CMOS. Masum Hossain & Tony Chan Carusone University of Toronto
20 GHz Low Power QVCO and De-skew Techniques in 0.13µm Digital CMOS Masum Hossain & Tony Chan Carusone University of Toronto masum@eecg.utoronto.ca Motivation Data Rx3 Rx2 D-FF D-FF Rx1 D-FF Clock Clock
More information+3.3V. C FIL 0.82μF SDI+ SDI- SLBI+ SLBI- +3.3V V CTRL V REF SIS LREF LOL RS1 SYSTEM LOOPBACK DATA +3.3V
19-2709; Rev 3; 2/07 EVALUATION KIT AVAILABLE Multirate Clock and Data Recovery General Description The is a compact, multirate clock and data recovery with limiting amplifier for OC-3, OC-12, OC-24, OC-48,
More informationFractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter
J. Park, F. Maloberti: "Fractional-N PLL with 90 Phase Shift Lock and Active Switched-Capacitor Loop Filter"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Josè, 21 September
More informationTHE serial advanced technology attachment (SATA) is becoming
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 54, NO. 11, NOVEMBER 2007 979 A Low-Jitter Spread Spectrum Clock Generator Using FDMP Ding-Shiuan Shen and Shen-Iuan Liu, Senior Member,
More informationISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.5
ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.5 20.5 A 2.4GHz CMOS Transceiver and Baseband Processor Chipset for 802.11b Wireless LAN Application George Chien, Weishi Feng, Yungping
More informationLow Jitter, Low Emission Timing Solutions For High Speed Digital Systems. A Design Methodology
Low Jitter, Low Emission Timing Solutions For High Speed Digital Systems A Design Methodology The Challenges of High Speed Digital Clock Design In high speed applications, the faster the signal moves through
More informationAnalog and Telecommunication Electronics
Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics C5 - Synchronous demodulation» AM and FM demodulation» Coherent demodulation» Tone decoders AY 2015-16 19/03/2016-1
More informationA 25MS/s 14b 200mW Σ Modulator in 0.18µm CMOS
UT Mixed-Signal/RF Integrated Circuits Seminar Series A 25MS/s 14b 200mW Σ Modulator in 0.18µm CMOS Pio Balmelli April 19 th, Austin TX 2 Outline VDSL specifications Σ A/D converter features Broadband
More informationA Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter
University of Pennsylvania ScholarlyCommons epartmental Papers (ESE) epartment of Electrical & Systems Engineering 7-1-2003 A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and
More informationA fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications
LETTER IEICE Electronics Express, Vol.10, No.10, 1 7 A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications June-Hee Lee 1, 2, Sang-Hoon Kim
More informationon-chip Design for LAr Front-end Readout
Silicon-on on-sapphire (SOS) Technology and the Link-on on-chip Design for LAr Front-end Readout Ping Gui, Jingbo Ye, Ryszard Stroynowski Department of Electrical Engineering Physics Department Southern
More informationWideband Sampling by Decimation in Frequency
Wideband Sampling by Decimation in Frequency Martin Snelgrove http://www.kapik.com 192 Spadina Ave. Suite 218 Toronto, Ontario, M5T2C2 Canada Copyright Kapik Integration 2011 WSG: New Architectures for
More informationAnalog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem
Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview
More informationPhase-locked loop PIN CONFIGURATIONS
NE/SE DESCRIPTION The NE/SE is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 0MHz. As shown in the Block Diagram, the NE/SE consists of a VCO, limiter, phase comparator,
More informationEuropean Conference on Nanoelectronics and Embedded Systems for Electric Mobility
European Conference on Nanoelectronics and Embedded Systems for Electric Mobility ecocity emotion 24-25 th September 2014, Erlangen, Germany Low Power Consideration in Transceiver Design for Internet of
More informationLow Phase Noise CMOS Ring Oscillator VCOs for Frequency Synthesis
Low Phase Noise CMOS Ring Oscillator VCOs for Frequency Synthesis July 27, 1998 Rafael J. Betancourt Zamora and Thomas H. Lee Stanford Microwave Integrated Circuits Laboratory jeihgfdcbabakl Paul G. Allen
More informationA 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS
A 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS Diary R. Sulaiman e-mail: diariy@gmail.com Salahaddin University, Engineering College, Electrical Engineering Department Erbil, Iraq Key
More informationOptimization of Digitally Controlled Oscillator with Low Power
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 6, Ver. I (Nov -Dec. 2015), PP 52-57 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Optimization of Digitally Controlled
More informationConfiguring the MAX3861 AGC Amp as an SFP Limiting Amplifier with RSSI
Design Note: HFDN-22. Rev.1; 4/8 Configuring the MAX3861 AGC Amp as an SFP Limiting Amplifier with RSSI AVAILABLE Configuring the MAX3861 AGC Amp as an SFP Limiting Amplifier with RSSI 1 Introduction As
More informationAccomplishment and Timing Presentation: Clock Generation of CMOS in VLSI
Accomplishment and Timing Presentation: Clock Generation of CMOS in VLSI Assistant Professor, E Mail: manoj.jvwu@gmail.com Department of Electronics and Communication Engineering Baldev Ram Mirdha Institute
More informationLow-Jitter, 8kHz Reference Clock Synthesizer Outputs MHz
19-3530; Rev 0; 1/05 Low-Jitter, 8kHz Reference General Description The low-cost, high-performance clock synthesizer with an 8kHz input reference clock provides six buffered LVTTL clock outputs at 35.328MHz.
More informationAn 8-Gb/s Inductorless Adaptive Passive Equalizer in µm CMOS Technology
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.12, NO.4, DECEMBER, 2012 http://dx.doi.org/10.5573/jsts.2012.12.4.405 An 8-Gb/s Inductorless Adaptive Passive Equalizer in 0.18- µm CMOS Technology
More informationOIF CEI 6G LR OVERVIEW
OIF CEI 6G LR OVERVIEW Graeme Boyd, Yuriy Greshishchev T10 SAS-2 WG meeting, Houston, 25-26 May 2005 www.pmc-sierra.com 1 Outline! Why CEI-6G LR is of Interest to SAS-2?! CEI-6G- LR Specification Methodology!
More information15.3 A 9.9G-10.8Gb/s Rate-Adaptive Clock and Data-Recovery with No External Reference Clock for WDM Optical Fiber Transmission.
15.3 A 9.9G-10.8Gb/s Rate-Adaptive Clock and Data-Recovery with No External Reference Clock for WDM Optical Fiber Transmission. H. Noguchi, T. Tateyama, M. Okamoto, H. Uchida, M. Kimura, K. Takahashi Fiber
More information