Circuit Design for a 2.2 GByte/s Memory Interface

Transcription

1 Circuit Design for a 2.2 GByte/s Memory Interface Stefanos Sidiropoulos Work done at Rambus Inc with A. Abhyankar, C. Chen, K. Chang, TJ Chin, N. Hays, J. Kim, Y. Li, G. Tsang, A. Wong, D. Stark

2 Increasing Chip I/O Bandwidth Computers: Main memory: SDRAM100 (100 Mbps) RDRAM ( Gbps) Peripherals: PCI (66 Mbps) Infiniband (2.5 Gbps) Networks: Physical Front End: LAN: Fast-Eth (100 Mbps) Gigabit-Eth (1Gbps) WAN: OC-12 (625 Mbps) OC-48 (2.4 Gbps) Switch Fabric: 625 Mbps 2.5 Gbps

3 Outline Overview Timing Methods Signaling Methods Timing Circuits Signaling Circuits Results

4 Main Issues Tx Channel PCB, Coax, Fiber Rx Drive and capture signals at the correct time Bit times are as small as 2-3 gate delays Send and receive signals robustly Noise is a large fraction of the signal < 400-mV < 1-ns

5 Timing Architectures Synchronous: Same frequency and phase Conventional busses Conventional Memories t t F 0 Mesochronous: Same frequency, unknown phase Fast memories/busses t A t B MP networks t A t B F 0 Interconnection networks Plesiochronous: Almost the same frequency Network front-end Router core F 1 F 2 F 1 F 2

6 Synchronous Systems CK X PLL/DLL CK C CK X D I on-chip logic D I CK C On-chip clock is a multiple of system clock: Synthesize on-chip clock frequency On-chip clock phase varies: Cancel clock buffer delay

7 Mesochronous Systems CK SRC PLL/DLL CK RCV data rcvr logic ref CK SRC data D 0 D 1 D 2 D 3 CK RCV Position on-chip sampling clock at the optimal point i.e. maximize timing margin

8 Plesiochronous Systems CK R rcvr logic D IN D 0 D 1 D IN CRC CK R Recover incoming data fundamental frequency Position sampling clock at the optimal point

9 Signaling Send and receive the data impaired by noise: Independent noise sources: Thermal and uncorrelated system noise Proportional noise sources: Reflections, cross-talk, signal-return noise Low Impedance High Impedance V S Single Ended V S /2 + - shared d ref + - Differential + - d d + -

10 Outline Background Timing Circuits Signaling Circuits Results

11 Rambus Memory Channel M 1 M 2 M 16 M 1 M 2 M Controller CTM Clk Gen CFM 1.6-GB/s (800 Mbps/pin): Current mode signaling Source synchronous clocking D0 D1 D2

12 Increasing System Performance Increase transfer rate: System Clock: MHz ( Mbps/pin) Peak Bandwidth: GB/s Challenges: Timing Margin Device Variations Channel Imperfections Voltage Errors Bus Hand-off

13 Prototype DRAM Interface Chip Technology: 0.25-µm, 2.5-V CMOS Supply: 1.8-V Active Area: 11.2 x 1.3 mm 2 Package: LGA, µbga Chip Includes: T/R DLL 2-Data bytes, 1-Address byte Packet Protocol Logic 18 KB SRAM

14 Outline Background Timing Circuits Requirements Architecture Timing Error Sources Signaling Circuits Results

15 RDRAM Timing Circuit Requirements DLL T CLK R CLK R CLK T CLK R CLK DQ A CTM CFM RQ DQ B CTM CFM DQ D 0 D 1 D 2 D 3 DQ/RQ D 0 D 1 D 2 D 3 T CLK R CLK

16 PLLs vs DLLs VCO VCDL clk clk ref clk N PD ref clk PD Filter Filter Second/third order loop: First order loop: Stability is an issue Stability guaranteed Frequency synthesis easy Frequency synthesis problematic Ref. Clk jitter gets filtered Ref. Clk jitter propagates Phase error accumulates Phase error does not accumulate

17 Supply Noise: DLL vs PLL 6-stage DLL vs 6-stage PLL 0.) g e (d r r o e e s a h p DLL-pk PLL-pk DLL PLLBW 20MHz PLLBW 5MHz time (ns) * Supply sensitivity: 0.1%-delay/%-supply/element No need for clock multiplication use a DLL

18 Conventional DLL ref clk clk PD Limited phase acquisition range Generate delay by using phase interpolation

19 Variable Phase Interpolation φ φ φ ψ Θ ψ ψ w = 0..N Θ = ( N w) φ + N w ψ φ 1 If φ, ψ selectively span 2π: ψ 1 ψ 0 Can generate any Θ φ 2 φ 0 φ, ψ can be generated by a DLL ψ 2 ψ 3 φ 3

20 RDRAM Delay Buffers [Maneatis 93] V CP V CTL Bias Circuit V CN [Hu 92] Use differential elements with replica biasing: Increased noise immunity Not easily portable Require larger supply head-room but ok for 1.8-V

21 Interpolator Design V CP V CN 5 DAC + - Interpolator bias and input/output time constant scales TDC remains linear over large frequency range

22 Dual DLL Block Diagram PD/CP/Bias Input Clock Amp CORE Amp FSM PERIPHERAL up/dn PD Ref Clock

23 Device Timing Variations 25 Receive Window Distribution 20 # parts Receive-valid Window Center (ps) 100 parts: µ 30-ps, σ 20-ps

24 Propagation Delay Mismatch φ DRAM Module Discontinuity v( t) = A [sin( ω t ) + r sin( ω t 2ϕ )] v( t) = A' sin( ω t + θ ) Clock and data channels different Clock and data spectral components different Propagation delays can differ by ~ 100-ps Regain margin: every DRAM transmit/receive timing must be offset from its lock point A θ A ra 2φ

25 Original Dual-DLL PD/CP/Bias Input Clock Amp Amp Mux+Interpolator Decoder 8 Counter FSM up/dn FB Clock PD Main Clock Ref Clock to I/O

26 DLL for in-system Calibration PD/CP/Bias Input Clock Amp Amp Decoder Mux+Interpolator Mux+Interpolator (_2) Adder Decoder 8 8 Offset[7:0] time) Counter up/dn FB Clock PD Main Clock Ref Clock to I/O

27 Outline Background Timing Circuits Signaling Circuits Bus Environment Challenges Output Subsystem Design Results

28 Back-to-Back Reads V term Contr. t 1 t 2 V term Mem 1 Mem 2 Controller t 1 + t 2 2 t 2 V term -V sw Mem 2 2 t 2 V term -1.5V sw Compliance voltage for M 2 as low as 0.5-V

29 Output Driver Subsystem Driver Bias Voltage Generator V GREF - + V GATE CC[6:0] EN V G [6:0] _7 DQ 0 7 DQ 1 7 DQ 8 Q 0 Q 1 Q 8 _7 _7 _7

30 Driver Bias Voltage Generator I C I R V GREF I R R R >V T Constant gate overdrive: Increase noise immunity Constant saturation margin over PVT

31 Driver IV Characteristics Iout (ma) TT SS FF Vpad (V)

32 Output Driver Model -A v O v G g m2 g m r o i out = gm vg + vo / ro A gm2 v o Negative resistance compensates for finite r o

33 Output Driver Schematic SL[1:0] M 7 [1:0] M 6 [1:0] D Q V G [6:0] M 2 [6:0] M 5 Q M 1 [6:0] M 3 M 4 M6-M7 control maximum feedback current M3/M4 ratio constrained to minimize time constant

34 Driver IV Characteristics Iout (ma) TT SS FF Vpad (V)

35 Outline Introduction Timing Signaling Results

36 Operating Range 2.75 T BIT (nsec) 1.8-V 1.1 Gbps/pin V DD (Volts)

37 Measured DLL Jitter < 100-ps peak-peak with interface and core active

38 Uncalibrated Output Data-valid Window 2.5 V DD (Volts) 1-V 760-ps t (ns) 1.0 T BIT = 900-ps, T OFFS = default T Q offset ~ 150-ps

39 Calibrated Output Data-valid Window 2.5 V DD (Volts) 1-V 780-ps t (ns) 1.0 T BIT = 900-ps, calibrated T OFFS T Q offset < 20-ps

40 Measured Calibration Accuracy offset (degrees) MHz 533 MHz code # DNL, INL < 2-LSB

41 RDRAM Power Modes DLL must go into low-power nap mode IVDD < 4-mA Restore clock phase within 80-ns Digital peripheral loop logic naturally holds state Hold state of core loop on 25-pF charge-pump capacitor

42 Measured Driver I-V Characteristics Iout (ma) FB off FB on Vpad (V)

43 Summary Increasing memory interface bandwidth: Minimize both voltage and timing errors: Voltage errors are systematic Compensated with new driver design Timing Errors are unpredictable Compensated with in-system calibration Expect to see more digital calibration in high speed links: Challenge is minimize overhead: Area, Power, Yield.. System bring-up and ease of use..