Design of High-Speed Serial-Links in CMOS (Task ID: )

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1 Design of High-Speed Serial-Links in CMOS (Task ID: ) SRC Research Review September 10, 2003 Won Namgoong University of Southern California SRC Review 9/10/03 W. Namgoong, USC 1

2 Design of High-Speed Serial- Links in CMOS Technical Thrust Circuit Design Students Kyongsu Lee Lei Feng SRC Review 9/10/03 W. Namgoong, USC 2

3 Accomplishments for 2003 Developed adaptive/synchronization techniques for frequency channelized receivers. Designed a serial-link prototype based on frequency channelization. Currently in fabrication. SRC Review 9/10/03 W. Namgoong, USC 3

4 Outline of Talk Adaptive frequency channelized receiver. Frequency channelized receiver implementation. Research plans for next year. SRC Review 9/10/03 W. Namgoong, USC 4

5 Background in Signaling Transistor mismatches. On-chip noise. Inter-symbol interference. Wire losses and package parasitics. Finite receiver/transmitter bandwidth. SRC Review 9/10/03 W. Namgoong, USC 5

6 Existing Architecture Time-Interleaved Receiver Sample at approx. Nyquist rate; 2-4 bit s (flash). sees the full bandwidth of the input signal. Sample/hold circuitry difficult to design. Sensitive to sampling jitter and sample-time offsets. Large input capacitance. SRC Review 9/10/03 W. Namgoong, USC 6

7 Frequency Channelized Receiver Achieves the same effective sampling frequency as timeinterleaved receiver using the same number of s. input bandwidth reduced. Sample/hold circuitry relaxed. More robust to sampling jitter even with mixer phase noise present. Reduced input bandwidth. SRC Review 9/10/03 W. Namgoong, USC 7

8 Adaptive Frequency Channelized Receiver Overview Adaptive synthesis filter bank. Equalize distortion caused by the propagation channel and reconstruct the channelized signal for detection. Analog analysis filter bank not accurately known at design time. Error signal based on the detected symbol. Digital interpolators. sampling frequency generally not an integer multiple of the symbol frequency. Interpolation must occur after synthesis filter bank. SRC Review 9/10/03 W. Namgoong, USC 8

9 Overall Receiver Structure s[l] Adaptive Filter Bank d ˆ[ n ] Timing/Detection Module Detection Interpolator Timing Controller Detector Timing Recovery aˆ [ m] Training Symbols Delay - + Backward Timing Prediction Adaptive Control Module Reference Interpolator Timing/detection module extracts timing information and detects transmitted symbol. Adaptive control module generates error signal used to update the adaptive synthesis filter bank. SRC Review 9/10/03 W. Namgoong, USC 9

10 Adaptive Filter Bank (1) x ( t) + n( t) s 0 [ l] H( jω) y [ n 0 ] γ G 0( z ) Re{ } d ˆ[ n ] H( jω) f sample s [ l 1 ] γ G ( z 1 ) exp{ j2πf sample t} H( jω) exp{ j2π ( M 1) f sample t} : : f sample s [ l M 1 ] f sample γ y [ n M 1 ] G M 1 ( z) e[n] d[n] - + Effective sampling frequency feff =γ f sample, where γ = 2M 1. Re{} applied since transmitted signal is a baseband real signal. SRC Review 9/10/03 W. Namgoong, USC 10

11 Adaptive Filter Bank (2) s 0 [ l] : : s [ l M 1 ] code channel 0 W ( 0,0 z) : W M ) ( 1,0 z W ( 0, γ 1 z : W ( M 1, γ 1 z ) ) Re{ } Re{ } code channel γ 1 z[ γl] e[ γl ] z[ γl + γ 1] e[ γl + γ 1] e[n] d ˆ[ n ] - + d[n] Synthesis filter bank is LPTV system with period γ. Each code channel estimates one of γ consecutive samples. LMS adapts each code channel independently: w [ l + 1] = w [ l ] + εs[ l ] e[ γl i] i i + SRC Review 9/10/03 W. Namgoong, USC 11

12 Timing/Detection Module d ˆ[ n ] Detection Interpolator u[m] Detector aˆ [ m] µ m Compute Fractional Interval Overflow η[n] NCO e T L[m] Loop Filter e T [m] M&M Timing Error Detector Timing Controller Timing Recovery Detection interpolator resamples to symbol rate. Timing recovery determines timing error that controls interpolator. SRC Review 9/10/03 W. Namgoong, USC 12

13 Adaptive Control Module n = n d ˆ[ n ] D r e[n'] Delay D r - + d[n'] Backward Timing Predictor Compute Past Overflow d ˆ[ n Overflow ] Reference Interpolator Compute Fractional Interval ξ n Symbols η[n] w NCO [n] NCO Backward timing predictor calculates timing information of delayed filter bank output based on current NCO state. Delayed for used in DD mode. Reference interpolator generates desired reference signal. SRC Review 9/10/03 W. Namgoong, USC 13

14 Simulation Results Convergence Performance SRC Review 9/10/03 W. Namgoong, USC 14

15 Simulation Results Effect of Filter Taps SRC Review 9/10/03 W. Namgoong, USC 15

16 Simulation Results Effect of Bits SRC Review 9/10/03 W. Namgoong, USC 16

17 Summary of Adaptive Frequency Channelized Receiver Work Based on frequency channelized signals, an adaptive synchronization/detection scheme is described. Performance of proposed receiver is similar to that of a single channel receiver. Convergence time is slightly longer. SRC Review 9/10/03 W. Namgoong, USC 17

18 Implementation of Frequency Channelized Receiver A frequency channelized receiver excluding the digital back-end has been implemented in 0.25um CMOS. Symbol rate of 10Gsymbols/sec. Three frequency subbands and 10 3-bit s each operating at 1.24Gsamples/sec. Currently in fabrication. SRC Review 9/10/03 W. Namgoong, USC 18

19 System Architecture 2 Differential input signal 50Ω f - 3dB = fo 2fo I/Q LPF LPF fs = fo 2fo fo = 1.24G 4fo freq. LPF LPF Gray decoder & Output driver 4fo I/Q LPF SRC Review 9/10/03 W. Namgoong, USC 19

20 Quad-Phase Mixing 50Ω + VSIG + ILO + I + ILO - VSIG - ILO I + QLO + Q - ILO Q - QLO + ILO Conventional passive double balanced mixer. 50 ohm matching allows wide input bandwidth: ~6.5GHz. SRC Review 9/10/03 W. Namgoong, USC 20

21 Low Pass Filtering Buffer 4-stage Feedback LPF Gain [db] Ri RF RO RS 80dB/dec 20dB/dec Freq. VB RS RF Vc Vc adjusts gm of transistor M1 to control gain without affecting bandwidth. Ma M1 CMFB Achieves 20dB gain with 1.4GHz 3-dB bandwidth. SRC Review 9/10/03 W. Namgoong, USC 21

22 Architecture 2 Time-interleaved 3-bit LPF f 3dB = 1.24G architecture f s = 1.24G Each 3-bit samples at 1.24Gsps. Effective sampling rate/channel is 2.48Gsps. No offset scheme necessary. a6 a5 a4 a3 a2 a1 a0 V N V P ref latch sampler CLK comparator SRC Review 9/10/03 W. Namgoong, USC 22

23 Local Oscillator Frequency Generation differential 2fo Quad - phase 4 - phase 2fo drive mixer Freq. Divider 2 - phase fo drive, Code converter BPF LPF VCO Quad - phase 4 - phase 4fo drive mixer 4fo Freq. Doubler SRC Review 9/10/03 W. Namgoong, USC 23

24 Chip Layout & DECODER LPF MIXER & LO SIGNAL INTERFACE Freq. Doubler SRC Review 9/10/03 W. Namgoong, USC 24

25 Plans for Next Year Fabricate and test design prototype to verify main concepts. Develop/analyze more sophisticated adaptive reception algorithms based on maximumlikelihood sequence estimation (MLSE). Faster convergence speed and higher performance. Design transmitter/receiver to support higher rates. Multi-level signaling. OFDM based communication systems. SRC Review 9/10/03 W. Namgoong, USC 25