European Conference on Nanoelectronics and Embedded Systems for Electric Mobility

Transcription

1 European Conference on Nanoelectronics and Embedded Systems for Electric Mobility ecocity emotion th September 2014, Erlangen, Germany Low Power Consideration in Transceiver Design for Internet of Things Applications Ye Zhang M.Sc. Chair of Integrated Analog Circuits & RF Systems RWTH Aachen University, Germany

2 Presentation Outline Specification of Internet of Things Transceiver architecture introduction Low-Power techniques Sliding-IF architecture Current-reuse VCO Digital clock recovery Performance comparison Conclusion & outlook

3 Specification of Internet of Things Short distance communication Low power Low cost and low complexity High efficient Sufficient data rate Energy harvesting Sleeping / wake up mode Supporting multi-standards application BT, Zigbee, SUN, ANT+, DECT 6.0, WBAN, etc Multiple frequency bands (ISM 400MHz, 900MHz, 2.4GHz) Multiple data rate (100kbps to 2Mbps) Constant envelop modulation (BPSK, GFSK,OQPSK, etc) Relaxed BER requirement

4 Transceiver Architecture Introduction TX_I D A LPF Mixer BPF Transmitter: Frequency Synthesizer :2 LO_I VGA PA LO_Q TX_Q D A Mixer LPF VGA ADC A D RX_I Receiver: LNA :2 LO_I Frequency Synthesizer LO_Q A D RX_Q Frequency synthesizer generates the highest frequency High power consumption Only valid for single frequency band

5 Low power consideration on IoT Multiple frequency band access Sliding IF architecture Sharing the unique RF frontend Saving power in transceiver Current-reuse VCO Single-ended structure Multiple data rate access Digital clock recovery Adjustable oversampling ratio Adaptive frequency offset compensation

6 Sliding-IF Architecture RF frontend 400MHz 1.6-2GHz :2 :2 WBAN low band: A D Zigbee low band: 900MHz BT, BTLE, SUN, etc: 2.4GHz A D Sharing unique RF frontend in TX & RX Same IF frequency achieved by single/dual conversion Sharing the same DSP

7 Low Power Technique in LO Generator V DD Reference clock VCO L PFD CP LPF C V out Divider M1 M2 VCO dominates out-of-band phase noise VCO consumes high power due to high frequency Current-reuse VCO reduce power to 50%, but: Unbalanced output swing Transconductances mismatch

8 VCO Fundamentals Conventional L C V out V DD dominates Current-reuse VCO L C V out M1 M2 M1 M2 V DD Output swing is unbalanced S.-J. Yun, et al. A 1mW current-reuse CMOS differential LC-VCO with low phase noise, ISSCC Introduce harmonic spurs at differential outputs

9 Current-Reuse VCO VCO with resistors Switch on Switch off V DD V DD L R on2 C C L C L M1 M2 R s1 R s2 V DD R on1 Transistors switch on and off simultaneously No common-source node Resistors limit current with enough voltage swing Equalize waveform swings in two periods

10 Proposed Current-Reuse VCO V DD V DD Cs 1 Rs 1 M1 L C var V con C var To divider M3 C var V txdata C 0 S 0 C 0 C var M5 To mixer M4 C 1 S 1 C 1... C 5 S 5 C 5 M6 Rail to rail M2 Rs 2 Cs 2 Ye Zhang, et al. A 2.4-GHz Low Power High Performance Frequency Synthesizer Based on Current-Reuse VCO and Symmetric Charge Pump, RFIC RFIC Seattle 2-4 June 2013

11 Proposed Transmitter Architecture Crystal 32 MHz V ref MUX S1 VCO 4.8 GHz PFD/CP LPF :2 Frequency divider ƩΔ modulator LPF Clk Enable To mixer I Q Data_in Data_out Div_fixed Time delay DAC Serias interface Div_modulated Digital Predistortion filter S1 6 Pre-tuning 3 Frequency comparator & FSM Preset 3 Register Readout

12 Self-Calibration for Pre-Tuning From LPF V default MUX VCO Coarse tuning From cystal Counter Reset switch Pre-tuning 6 Preset Comparator 3 3 Register Readout From div Counter VCO alignment is stored as preset value 30μs for initial calibration

13 Performance with Current-Reuse VCO LO phase noise Baseband spectrum Fourier series of output wave v( t ) = [1 + P form with non-ideal duty cycle 1 τ: T n = 1 2sinc( n ) cos( n! t ) ] T Offset amplitude in DC and harmonic frequencies Harmless to the fundamental frequency component

14 Clock Data Recovery Introduction Integer and fixed oversampling ratio for analog CDR Extra PLL needed for digital CDR Ʃ modulated frequency divider implemented in proposed CDR

15 Proposed CDR Mechanism r(kt s ) LPF r(kt s +μ n T s ) z(kt s ) z(nt+εt) Interpolator MF Decimator e jθ CFO estimator NDA DD Decision Block diagram: s IF (t) f s jω IF t e μ n m n Phase rotator NDA a k Clock data rate controller ε Timing error esimator DD Example f s /f data =4.25: Sampling clock Recovered data clock Sampling data Recovered data Ye Zhang, et al. A Low-Power Low-Complexity Multi-Standard Digital Receiver for Joint Clock Recovery and Carrier Frequency Offset Calibration, TCAS Sampling clock is irrelevant to data rate Fractional interpolator determines fractional delay

16 Clock Recovery Performance Input, output, clock data waveform 667kbps data recovery 2Mps data recovery

17 Clock Recovery Performance CDR and CFO calibration process Recovered clock spectrum CDR and CFO Error gets convergence in 80μs Recovered clock has quantization noise due to fractional frequency divider Frequency deviation depends on oversampling ratio

18 Conclusion & Outlook Conclusion Low power, low complexity and high flexibility architectures and circuits are highly required in IoT applications Sliding-IF technique allows multiband frequency access Current-reuse VCO can save half current Adaptive CDR is valid for multiple data rate Outlook Wake up transceiver systems to save more power Energy harvesting

19 Thank you Acknowledgement to German Federal Ministry of Education and Research and the Joint Undertaking eniac for supporting the project of Energy to Smart Grid (EFFORT), FKZ 13N12122