60 GHz Transmitter (Tx) Waveguide Module

Transcription

1 The is a highly integrated millimeter wave transmitter that covers the 60 GHz global unlicensed spectrum allocations packaged in a standard waveguide module. Transmitter architecture is a double conversion, sliding IF with wide bandwidth capability through the upconversion chain from baseband to carrier. The I/Q interface accepts analog baseband signals which provides for flexibility in design and applications. The baseband input optionally supports FSK/MSK modulation for noncoherent applications. The transmitter incorporates a complete waveguide interface with low-loss transition between the chip and the WR5 waveguide port. The integrated package is small and lightweight, with a simple to use multi-pin ST4 connector for power, reference clock, digital control port and baseband signals. Either of two reference clocks can be used for setting 540 MHz or 500 MHz channel spacing. Features: Complete millimeter wave transmitter WR-5, UG-85/U flange Operates in the 5 to 66 GHz unlicensed band dbm typical output power Up to.8 GHz modulation bandwidth I/Q analog baseband interface On chip synthesizer covers 5 to 64.8 GHz 500 MHz or 540 MHz step size 85.4 MHz clock for 500 MHz step size 08.5 MHz clock for 540 MHz step size Power, control, signals on ST4 connector Temperature sensor Applications 80.ad: 58., 60.48, 6.64, GHz 80.aj: 59.94, 6.0, 6.0, 6.8 GHz Any Channel (500 MHz or 540 MHz) GHz Multi-Gbps Digital Communications HD Video Transmission Millimeter Wave Radar Millimeter Wave Imaging Development for 80.ad and 80.aj ATE Equipment for 60 GHz Manufacturing Test inventory and certifications: REV

2 G G WR-5 UG-85/U Flange.05" (6.85 mm).50" (9.05 mm).9" (0. mm) Samtec ST4-0 Connector.59" (5.00 mm).94" (0.00 mm).54" (9.00 mm).5" (8.00 mm) Pin G Figure Mechanical Dimensions inventory and certifications: REV

3 G Samtec ST4-0 Pin.V.5V 4V 4V.V.V.V.V.V.V.V.5V VCC VDD VCC_PA VCC_PA VCC VCC VCC VCC VCC VCC VCC VDD CLK DATA SCANOUT BB_QM BB_QP BB_IM BB_IP FMM_Q FMP_Q FMM_I FMP_I REFCLKM REFCLKP Q_E Q_B_C RESET ENABLE Mating Connector: Samtec SS L-D-K-TR Figure Interface Connector Pinout inventory and certifications: REV

4 Table Performance Specifications* Parameter Min Typ Max Unit Comment Frequency Range GHz Channel Spacing 540 MHz 08.5 MHz Reference Channel Spacing 500 MHz 85.4 MHz Reference Modulation Bandwidth.8 GHz Max BW setting, double-sided at db Gain, Max 8 db Gain = P out - P in (I/Q differential input) Gain, Range 0 db Gain, Step Size.5 db PdB dbm Psat 5 dbm Image Rejection 4 db Sideband Suppression 0 db Carrier Suppression 0 db x LO Suppression db Phase 00 khz - dbc/hz Phase MHz -86 dbc/hz Phase 0 MHz - dbc/hz Phase 00 MHz -5 dbc/hz Phase GHz - dbc/hz PLL Loop Bandwidth 00 khz I/Q Balance Phase ± degrees I/Q Balance Amplitude ± db *Test Conditions: Reference Frequency 08.5 MHz Temperature 5 C I/Q Input Signal Level Referenced to - dbm x4 at each 50 ohm input port IF Bandwidth Max Output Referenced to WR5 output port inventory and certifications: REV 4

5 Table Recommended Operating Conditions Description Power Supplies Serial Control Port Logic High Serial Control Port Logic Low Name Vcc ST4 Pin # 8,,4,6, 8,0, Min Typ Max Unit Vdd 0, V Vcc_PA,4,6, V DATA 8 CLOCK 6 ENABLE V RESET SCANOUT 40 DATA 8 CLOCK 6 ENABLE V RESET SCANOUT 40 V Serial Control Port Speed 00 MHz REFCLKM 5 Reference Clock REFCLKP -5 0 dbm BB_QM I and Q Baseband BB_QP mvpp BB_QP BB_IM 9 FMM_Q FM/MSK Baseband FMP_Q 5 FMM_I mvpp FMP_I Q_E Temperature Sensor Q_B_C Vcc.V Supply Current Icc 9 ma Vdd.5V Supply Current Idd 8 ma Vcc_PA 4V Supply Current I PA 66 ma Operating Temperature C T A Reference clock power level specified at 00 ohms differential Baseband voltage at each of the individual baseband inputs (I +/-, Q +/-, FMI +/-, FMQ +/-) Temperature sensor is a N904 NPN transistor die connected as a diode junction inventory and certifications: REV 5

6 Table Absolute Maximum Ratings Table Absolute Maximum Ratings Description Power Supplies Serial Control Port Logic High Serial Control Port Logic Low Reference Clock I and Q Baseband FM, MSK Baseband GND Power Dissipation Storage Temperature Operating Temperature Name Vcc Vdd Vcc_PA DATA CLOCK ENABLE RESET SCANOUT DATA CLOCK ENABLE RESET SCANOUT REFCLKM REFCLKP BB_QM BB_QP BB_IM BB_QP FMM_Q FMP_Q FMM_I FMP_I P D T S T A ST4 Pin # 8,,4,6, 8,0, MAX.85 V 0,4.6 V,4,6,8 4. V V -.05 V 5 dbm 50 mvpp 50 mvpp 5,,,,9,5 ± 50 mv 00 mw -55 to 50 C -40 to 85 C Assertion of RESET, active high, asynchronously resets all registers inventory and certifications: REV 6

7 Transmitter Architecture The transmitter uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at / the RF carrier frequency, and the VCO is at / the RF carrier frequency. The LO is x the VCO frequency. The LO and IF are generated from a built-in synthesizer that has a step size at the RF carrier frequency of either 500 MHz or 540 MHz depending upon which reference clock frequency is used. The 540 MHz step size uses a 08.5 MHz reference, and the 500 MHz step uses a 85.4 MHz frequency. The IEEE channels for 80.ad and 80.aj are supported when the 540 MHz step size is used. I and Q analog baseband signals are upconverted to the IF frequency at the input mixers. The IF signal is filtered with a variable gain amplifier and filter with approximately 0 db range, which is then mixed with the LO. A notch filter attenuates the image frequency. The output of the mixer is fed to the PA stage which is coupled to the low-loss waveguide transition. There are optional FSK/MSK baseband data inputs for non-coherent modulation applications. The overall phase noise and I/Q balance specifications are sufficient for up to 6 QAM operation. Configuration and settings are controlled through a digital serial interface port. The block diagram below shows the various stages and circuits in the module. REFCLKP REFCLKM Synthesizer 5.0 to 64.8 GHz 0.5 or 0.54 GHz step Div x BB_IP BB_IM PA WR-5 Waveguide UG-85/U Flange 0 90 BB_QP BB_QM IF VGA Var IF Filter FMP_Q FMM_Q FMP_I FMM_I Serial Control Registers RESET ENABLE CLOCK DATA SCANOUT Figure Block Diagram inventory and certifications: REV

8 Synthesizer Design The transmitter uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at / the RF carrier frequency, and the VCO is at / the RF carrier frequency. The LO is x the VCO frequency. The tables below show the RF carrier, IF, VCO and LO for the frequency range from 5 GHz to GHz at 540 MHz and 500 MHz channel spacing respectively. The reference clock for the synthesizer at 540 MHz spacing is 08.5 MHz; for 500 MHz spacing it is 85.4 MHz. The loop bandwidth of the synthesizer phase lock loop is 00 khz. 540 MHz Spacing 500 MHz Spacing frf IF VCO LO frf IF VCO LO Figure 4 Synthesizer RF, IF, VCO and LO Frequencies inventory and certifications: REV 8

9 Digital Control Registers and Serial Interface Protocol - Write Operation The is configured via the serial control port which transfers data synchronously to or from (write or read operation) a register location. Register locations are organized into 6, byte-wide (8-bit) locations. The register locations are written to or read from one byte at a time as shown in Figures 5 and 6 respectively. Figure 5 shows the sequence of the digital control signals for the ENABLE, CLOCK and DATA input pins (ST4 connector, pins 9, 6 and 8 respectively) to write a single byte into the control register. After the ENABLE signal goes low, the first of 8 data bits (bit 0) is placed on the data pin, and ns or more after the DATA signal stabilizes, the CLOCK signal goes high which clocks in data bit 0. The DATA signal must remain stable for at least ns after the rising edge of the CLOCK. The signal levels are.5v CMOS, 50 kω impedance, with a maximum clock rate of 00 MHz. A write operation requires an 8 bit field associated with 8 clock pulses as shown in Figure 5. The 8 bit field contains the 8-bit data (LSB is clocked in first), followed by the byte address (BYTE 0 through BYTE 5, to 00, LSB first, only 4 of the 6 bits are used with the two MSBs set to 0), the read/write (R/W) bit (write = ), and the module address which distinguishes between a transmitter module and receiver module (for the V60RXWG receiver, RX module = ). After clock pulse (8 total pulses), the ENABLE signal is returned to a high state to load the register byte into the module. The CLOCK signal must be stable in the low state at least ns prior to the rising edge of the ENABLE signal. ENABLE CLOCK 0 DATA Data Byte Address R/W TX/RX Module LSB MSB LSB MSB LSB MSB Figure 5 Write Operation Timing Diagram inventory and certifications: REV 9

10 Digital Control Registers and Serial Interface Protocol - Read Operation Figure 6 shows the sequence of control signals at the ENABLE, CLOCK and DATA pins to read a single byte at a register location. A read operation requires a bit field: The first 8 bits are used to clock in the bits on the DATA input pin. The first 8 bits during a read operation are don t care bits as they are placeholders for the 8-bit byte data which would be present during a write operation. The following 0 bits are composed of the byte address (BYTE 0 through BYTE 5, to 00, LSB first, only 4 of the 6 bits are used with the two MSBs set to 0), the read/write (R/W) bit (read = 0), and the module address which distinguishes between a transmitter module and receiver module (for the transmitter, TX module = 0, LSB first). After clock pulse (8 total pulses), the ENABLE signal is returned to a high state while the clock signal is low, then a single clock pulse (pulse 8) is sent during the ENABLE signal high period. The ENABLE signal then returns to the low state while the CLOCK signal is low. At each of the subsequent 8 CLOCK pulses, the 8-bit data from the specified register location is available at the SCANOUT pin, LSB first. Note that the DATA signal must remain in the low state during the period from clock pulse 8 through 6. Following clock pulse 6, the ENABLE signal goes high while the CLOCK signal is low to end the read operation. ENABLE CLOCK DATA Data Byte Address R/W TX/RX Module SCAN OUT LSB MSB LSB MSB LSB MSB Read Data LSB MSB Figure 6 Read Operation Timing Diagram inventory and certifications: REV 0

11 Table 4. Register Byte Functions Table 4. Register Byte Functions Bit Name BYTE 0 pa_pwrdn 6 pa_pwrdn_fast 5 mixer_pwrdn 4 divider_pwrdn if_bgmux_pwrdn if_mixer_pwrdn driver_pwrdn 0 ifvga_pwrdn BYTE ipc_pwrdn 6 tripler_pwrdn 5 ifvga_q_cntrl_ 4 ifvga_q_cntrl_ ifvga_q_cntrl_0 not used not used 0 not used BYTE fdb_ 6 fdb_0 5 fdb_9 4 fdb_8 pa_sel_vgbs_ pa_sel_vgbs_ pa_sel_vgbs_ 0 pa_sel_vgbs_0 Function Active high to power down PA circuits not controlled by bit <6> Active high to power down PA core in < us Active high to power down IF to RF mixer Active high to power down local oscillator divider Active high to power down one of three on-chip refs (IF) and associated mux Active high to power down baseband to IF mixers Active high to power down PA predriver Active high to power down IF variable gain amplifier Active high to power down module current reference generator Active high to power down frequency tripler IF filter Q in the VGA amplifier; bits <:0> = 000 for highest Q and gain For reduced Q and wider bandwidth, bits <:0> = 00,00,0, in sequence Not used; bits <:0> = xxx Reserved; bits <:4> = for normal operation PA output transistors base voltage regulator; bits <:0> = 0000 for normal operation inventory and certifications: REV

12 Table 4. Register Byte Functions Table 4. Register Byte Functions Bit Name BYTE fdb_ 6 fdb_6 5 fdb_5 4 fdb_4 fdb_ fdb_ fdb_ 0 fdb_0 BYTE 4 pa_sel_vref_ 6 pa_sel_vref_ 5 pa_sel_vref_ 4 pa_sel_vref_0 driver_bias_ driver_bias_ driver_bias_0 0 driver_bias_ BYTE 5 not used 6 not used 5 not used 4 not used bg_monitor_set if_refsel enable_fm 0 not used Function Reserved: bits <:4> = 000 for normal operation Reserved: bits <:0> = for normal operation PA output transistors bias current; bits <:4> = 00 for normal operation PA predriver bias current; bits <:> = for normal operation PA predriver bias current; bit <0> = for normal operation Not used; bits <:4> = xxxx Reserved: bits <:> = 0 for normal operation Active high to enable FM/MSK modulator inputs; bit <> = 0 for normal I/Q Not used; bit <0> = x inventory and certifications: REV

13 Table 4. Register Byte Functions Bit Name BYTE BYTE BYTE ifvga_bias_ ifvga_bias_ ifvga_bias_ ifvga_bias_0 ifvga_tune_4 ifvga_tune_ ifvga_tune_ ifvga_tune_ ifvga_vga_adj_ ifvga_vga_adj_ ifvga_vga_adj_ ifvga_vga_adj_0 rfmix_tune_ rfmix_tune_ rfmix_tune_ rfmix_tune_0 tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_0 tripler_bias_9 tripler_bias_8 tripler_bias_ tripler_bias_6 Function IF VGA bias ; bits <:4> = 000 for normal operation IF VGA filter ; bits <:0> = for normal operation IF VGA gain control bits; bits <:4> = 0000 highest gain, lowest gain Attenuation.5 db/step, 0 db maximum IF filter alignment in the RF mixer; bits <:0> = for normal operation Frequency tripler bias (upper 8 bit portion): bits <:0> = 0 default inventory and certifications: REV

14 Table 4.4 Register Byte Functions Bit Name BYTE 9 tripler_bias_5 6 tripler_bias_4 5 tripler_bias_ 4 tripler_bias_ tripler_bias_ tripler_bias_0 driver_bias_ 0 driver_bias_0 BYTE 0 rdacin_5 6 rdacin_4 5 rdacin_ 4 rdacin_ rdacin_ rdacin_0 synreset 0 divratio_4 BYTE divratio_ 6 divratio_ 5 divratio_ 4 divratio_0 band_ band_ band_0 0 rfseldiv Function Frequency tripler bias (lower 6 bit portion): bits <:> = 00 default PA predriver bias current; bits <:0> = for normal operation VCO amplitude DAC; bits<:> = 00 for normal operation Synthesizer reset; bit <> = 0 for normal operation Synthesizer divider ratio bit 4 (see Tables 5. and 5.) Synthesizer divider ratio bits :0 (see Tables 5. and 5.) VCO band tuning bits :0 (see Tables 5. and 5.) Reserved; bit <0> = for normal operation inventory and certifications: REV 4

15 Table 4.5 Register Byte Functions Bit Name BYTE BYTE BYTE cpbias_ cpbias_ cpbias_0 vrsel_ vrsel_ vrsel_ vrsel_0 refselvco muxref div_4 en_dc ini pd_div_5 pd_div_ pd_qp pd_vco pd_cal muxout pdcalc5 pload wide_ wide_ slew_ slew_0 Function Synthesizer charge pump bias; bits <:5> = 00 for normal operation Synthesizer lock detector window width; bits <4:> = for normal operation Reserved; bit <0> = for normal operation Reserved; bit <> = for normal operation Enable synthesizer divider bit 4; bit <6> = 0 for normal operation Synthesizer reference input DC coupling; bit <5> = 0 for normal operation Reserved; bit <4> = 0 for normal operation Active high to power down.5v circuits in synthesizer divider Active high to power down.v circuits in synthesizer divider Active high to power down synthesizer charge pump Active high to power down synthesizer VCO Active high to power down VCO calibration; bit <> = 0 for normal operation Multiplexer control for ability to read byte 5; bit <6> = for normal operation Active high to power down VCO ALC; bit <5> = for normal operation Active high to load adjustment of VCO; bit <4> = for normal operation Control for VCO ALC loop; bits <:> = 0 for normal operation Slew rate control of sub-integer N divider; bits <:0> = 0 for normal operation inventory and certifications: REV 5

16 Table 4.6 Register Byte Functions Table 4.6 Register Byte Functions Bit Name BYTE 5 comp_p comp_n rdacmsb_ rdacmsb_ rdacmsb_0 rdacmux_0 rdacmux_ rdacmux_ Reserved (read only) Function Synthesizer lock indication (read only): bits <:6> = 0 locked, = above window, = 00 below window, = 0 disallowed indicating error Table MHz Channels Table MHz Channels Channel Divider Band Byte Byte Reference: 08.5 MHz Note : Band setting typical, may change from module to module and temperature. Note : Operation above 64 GHz not guaranteed over full operating temperature range. inventory and certifications: REV 6

17 Table MHz Channels Channel Divider Band Byte Byte Reference: 85.4 MHz Note : Band setting typical, may change from module to module and temperature. from Pasternack Enterprises has same day shipment for domestic and International orders. Our RF, microwave and fiber optic products maintain a 99% availability and are part of the broadest selection in the industry. inventory and certifications: URL: REV

18 CAD Drawing Millimeter Wave Transmitter Module Operating From 5 GHz To 64 GHz 0 Pasternack Enterprises All Rights Reserved REV 8