RFIC Design for Wireless Communications

Transcription

1 RFIC Design for Wireless Communications VLSI Design & Test Seminar, April 19, 2006 Foster Dai 1. An MIMO Multimode WLAN RFIC 2. A Σ Direct Digital Synthesizer IC Foster Dai, April,

2 1. Dave An MIMO Multimode WLAN RFIC 1. An Overview of MIMO Technology 2. MIMO Transceiver Design 3. Transceiver Building Block Circuits 4. Measured Results G. Rahn, Mark S. Cavin, Foster F. Dai, Neric Fong, Richard Griffith, Jose Macedo, David Moore, John W. M. Rogers, and Mike Toner, A Fully Integrated Multi-Band MIMO WLAN Transceiver RFIC, IEEE Journal on Solid State Circuits, Vol. 40, No. 8, pp , August, IEEE Symposium on VLSI Circuits, pp , Kyoto, Japan, June, Foster Dai, April,

3 Advantages of MIMO Technology MIMO can extend range and higher data rates Graph shows that for a 4X4 MIMO system 16.5dB less S/N ratio required for 54MBit/sec compared to standard technology As well vector CBF is shown which uses four orthogonal data streams to increase data rate 4X. VCBF not implemented here (not backwards compatible), but shows future of this technology. Average Data Rate (Mbps) x1 1x2 SD 4x4 CBF 4x4 VCBF 16.5dB Average SNR (db)/antenna Foster Dai, April,

4 MIMO Transceiver Design Two Radios On the same chip Slave Chip Beam Forming in the TX to get antenna gain through signal shaping Maximum ratio Combining at receive of signals in four paths at the RX Slave Chip LO Porting Trace Link LO Porting Trace Master Chip Transmitting Radio Note: Both beam forming and maximum ratio combining controlled by DSP Master Chip Receiving Radio Foster Dai, April,

5 MIMO Transceiver Design Issues MIMO transceiver RFIC design is a challenge due to the following issues: 1. Multiple radios on same die cause interference, especially PAs cause VCO injection-locking. Careful floor planning and proper isolation in layout are critical. VCOs operate at different frequencies from the PAs. 2. All LOs must be synchronized. MIMO calibration requires loop back measurement to match phase and amplitude of all paths. 3. Tx-Tx isolation must be high to maximize the gain from CBF. 30dB or higher desired. 4. Rx-Rx isolation must be maximized in order to maximize the gain from MCR. 40dB desired. Foster Dai, April,

6 MIMO Transceiver Design Block Diagram Uses walking IF architecture for only one synthesizer Includes 2 a/b/g paths on each chip. Either master or slave PLL mode. BB filters switched so same Si used in Tx and Rx. BBI1 BBQ1 BBQ2 BBI2 Legend: Matching Network Switch BBLPF IFLOQ RFMIX VGA IFMIX PPA Switch Serial to Parallel Interface Switch BBLPF Switch IFMIX IFLOQ IFMIX IFMIX IFLOQ IFLOI IFLOQ IFLOI PPA RFLO VGA RFMIX VGA 4 IFLOI IFLOQ RFMIX VGA RFMIX RFLO PPA PPA LNA RFLO VCO PA PA LNA Σ SYN LNA LNA PA RFOUT1 5GHz XTAL RCLPF RFOUT1 2.5GHz RFIN1 2.5GHz RFIN1 5GHz RFIN2 5GHz RFIN2 2.5GHz RFOUT2 2.5GHz Path1 Path2 RFOUT2 5GHz Foster Dai, April, 2006 PA 6

7 Synthesizer Design From master or to slave chip LO + Reset Signal off chip LPF VCOs n Bi-Directional LO Porting Circuit Additional Radio Paths (not shown) F Ref R PFD Charge Pump 1 : : F RF RF mixer IF mixers Baseband I-Q output Reference source Multi-modulus Divider RF mixer Baseband I-Q input Course tune frequency word C F IF 0 Multiple Input Multiple Output Transceiver Fine tune frequency word K + Σ accumulator size F Reset n th order Σ Foster Dai, April,

8 Chip Layout Designed in a 50GHz SiGe BiCMOS technology Chip measures 5.4mmX5.4mm Placed in a 72pin leadless plastic chip carrier (LPCC) package. RX1a RX1b/g TX1b/g TX1a MIMO Transceiver BB1 IF1 Synthesizer PFD/CP SPI LO Porting VCO BB2 IF2 MMD Σ TX2b/g TX2a RX2a RX2b/g Foster Dai, April,

9 EVM Measurements A: Ch1 OFDM Meas Range: -15dBm 1.5 Shows typical EVM measurement which complies with IEEE a standard. I-Q 300 m /div RBW: 312.5kHz TimeLen: 60 Sym B: Ch1 Spectrum Range: -15dBm -10 dbm 10 db /div -110 dbm Center: 5.18GHz RBW: kHz Foster Dai, April, Span: 36MHz TimeLen: uSec

10 Synthesizer Phase Noise Measurements Phase Noise (dbc/hz) Frequency Offset (khz) Shows good agreement with measured results. Foster Dai, April,

11 Chip Measurements SUMMARY OF TRANSCEIVER PERFORMANCE Parameter Performance Band b/g a Technology 0.5µm SiGe BiCMOS Voltage Supply 2.75V 2.75V TX Chain Current Supply (1path/2paths) 240/ 400mA 255/ 430mA RX Chain Current Supply (1path/2paths) Synthesizer Current supply 195/ 320mA 36mA 195/ 320mA 36mA TX output power 11dBm 13.5dBm EVM at TX output 4% (g only) 4% power TX Path to Path > 40dB > 40dB Isolation (measured at the PA outputs) RX Max Gain 4.1dB 7.5dB RX chain Max Gain 77 db 72 db RX chain Min Gain 5.5dB 25dB Rx Min Gain +8.8 dbm dbm RX I/Q Amplitude 0.3 db 0.3 db Imbalance RX I/Q Quadrature Error SUMMARY OF TRANSCEIVER PERFORMANCE Parameter Performance Band b/g a Rx Path to Path >50dB > 40dB Isolation (measured at the BB filter output) Max DC offset without 90mV 90mV correction (measured at the output of the BB filter) Synthesizer Integrated Noise 0.35~0.43 rms 0.63~0.86 rms 100Hz to 10MHz VCO Phase Noise 1MHz 1MHz In Band Phase Noise 10kHz 10kHz Synthesizer 40MHz Reference Frequency Synthesizer Step Size kHz kHz Synthesizer Spurious <-50 dbc Foster Dai, April,

12 A Multi-Band Σ Fractional-N Frequency Synthesizer John W.M. Rogers, Foster F. Dai, Mark S. Cavin, and Dave G. Rahn, A Fully Integrated Multi-Band SD Fractional-N Frequency Synthesizer for a MIMO WLAN Transceiver RFIC, IEEE Journal on Solid State Circuits, Vol. 40, No. 3, pp , March, Foster Dai, April,

13 CONFER ENCE ROOM COPY R M WORKR OOM MECHAN ICAL WORK R OOM 16 PANTRY CONFER ENCE ROOM TELECOMM. 13 CONFER ENCE RECEPTION Demo of Range Improvement Using the MIMO Transceiver RFIC 1x1 1x2sel 4CBFx2sel 4x2 CBF AP Scale: 10feet Shows improved range of MIMO radios in an office building at 2.4GHz. 4X4 link range too large to show. Foster Dai, April,

14 Conclusions Implemented an IEEE a/b/g transceiver RFIC for 2.4GHz and 5.2GHz and Japan 4.9GHz multi-band MIMO WLAN applications. Transceiver RFIC includes two complete radio paths fully integrated on the same chip. Using walking IF architecture, uses a single Σ fractional-n synthesizer for LO generation. Using two RFICs, 4X4 MIMO radio link has been tested under a typical indoor WLAN environment. The measured 4X4 MIMO radio achieves 15dB of link margin improvement over a conventional SISO radio. Foster Dai, April,

15 A CMOS Direct Digital Frequency Synthesizer with Single- Stage SD Interpolator and Current-Steering DAC DDS spurs and quantization noise due to phase truncation. Frequency domain and phase domain Σ noise shaping schemes. 12-bit current-steering DAC with Q 2 random walk switching scheme. 1.Foster F. Dai, Weining Ni, Yin Shi and Richard C. Jaeger, A Direct Digital Frequency Synthesizer with Single-Stage Σ Interpolator and Current-Steering DAC, IEEE Journal on Solid State Circuits, Vol. 41, No. 4, pp , April IEEE Symposium on VLSI Circuits, pp , Kyoto, Japan, June, Foster Dai, April,

16 Conventional ROM-Based DDS Fine step size requires a large accumulator and a large ROM. To reduce ROM size, the phase word is truncated, causing spurs at DDS output. Numerically controlled oscillator (NCO) D amplitude bits Sampled sin waveform Frequency control word (FCW) N + Phase accumulator N Phase truncation P MSB LSB N-P 2 P phase addresses SIN look up table D D-bits DAC Deglitch LPF DAC ~ f o N Z -1 Truncated phase Phase to amplitude conversion Filtered sin waveform Phase Digitized sin amplitude f o = f clk FCW N 2 Foster Dai, April,

17 DDS Pros and Cons Advantages Fine frequency tuning resolution Fast frequency switching Quadrature outputs with accurate I/Q matching Direct modulations (PSK, FSK, MSK, PM, and FM) Compatible with digital CMOS processing Disadvantages Low output frequency Quantization noise and spurious tones Foster Dai, April,

18 DDS With 4th Order Σ Modulator Implemented in 0.35µm CMOS Technology FCW Z -1 Phase word Phase word truncation 4 th order Σ noise shaper 1-(1-Z -1 ) k 8 MSBs 8 LSBs SIN ROM phase error e p (i) SIN word 12 DAC 12-bit DAC Deglitch LPF SIN output Using a 4 th order Σ modulator, ROM sized is reduced by a factor of 16 times, without compressing the ROM. ROM size can be further reduced using ROM compression algorithms. Foster Dai, April,

19 Output Spectrum Before Deglitch Filter For DDS With 4th Order Σ Modulator (a) Simulated (b) Measured Foster Dai, April,

20 Comparison of Measured Output Spectra for DDS with and without The 4th Order Σ Modulator With Σ Without Σ 72dB 58dB SFDR improved by 14 db Foster Dai, April,

21 Die Photo of The Σ DDS Prototype Implemented in 0.35µm CMOS Technology Die area = 2.2 2mm 2 DDS core = 1.11mm 2 Σ accumulator = mm 2 ROM = mm 2 ROM size is greatly reduced due to the use of Σ. DAC = mm 2 Power consumption = 200mW DAC = 82 mw Vdd = 3.3V Max clock frequency = 300MHz Foster Dai, April,

22 Questions? Contact Foster Dai Associate Professor Department of Electrical & Computer Engineering 200 Broun Hall, Auburn University, Auburn, AL Phone: (334) , Fax: (334) , Foster Dai, April,