Design and Implementation of Power Efficient RF-Frontends for Short Range Radio Systems

Transcription

1 Design and Implementation of Power Efficient RF-Frontends for Short Range Radio Systems Dr.-Ing. Lei Liao Infineon Technologies AG

2 Outline Introduction Challenges of Low Power Hardware Design The LPRF Project System Concept Hardware Demonstration Prototype of LPRF V.1 Implementation and characterization Prototype of LPRF V.2 Design and post-layout verification Investigation of Passive Sliding IF Mixer Topologies Conclusions Page 2

3 Introduction Wireless Radio System Page 3

4 Challenges of Low Power Hardware Design Compliance of most suitable standards IEEE /6 group: WPAN/Zigbee, SUN, Bluetooth etc. Ultra-low power consumption P=UI U I => P Low cost Using time, System power efficiency, Circuit robustness, PMU design effort High integration rate, Die area, External elements, Process R&D Page 4

5 The LPRF Project LPRF V.1 Fulfill the Bluetooth low energy standard Minimize RX power consumption Product orientated Investigate the circuit robustness LPRF V.2 Support multi-band multi-standard application System-level energy efficient Product orientated Highly integrated Page 5

6 System Concept of RX LPRF V.1 -f RF 0 f RF 0 Analog Digital Bandselect Filter 0 90 A D DSP LO LNA LPF VGA (a) Zero IF Receiver A D -f RF 0 f RF 0 IF Bandselect Filter LO LNA 0 90 BPF VGA (b) Low IF Receiver Analog Digital A D A D Low IF receiver: Less DC offset Less Flicker noise Power DSP Target Spec BTLE NF : ~11dB 29dB RX Gain: >40dB RX IIP3: -31dBm -35dBm f RFin GHz BW BB 1.3MHz Pdiss: <5mW Page 6

7 Hardware Implementation of LPRF V.1 PLL out 3W Bus data input Demod data output VDD PLL VDD ADC PLL 3W-Interface MODEM VDD RFFED VDD Digital A D RFin 0 :2 90 A D I bias I mess BIAS LNA Mixer PPF Low power design! LO ext BBI/Q mess & BBI/Q ext ΣΔADC out Page 7

8 Hardware Implementation of LPRF V.1 Capacitive Cross-Coupled CG-LNA under Low Power condition R u n s VDD L load µ = db σ = db N = 500 T = µ = 3. 2 db σ = db N = 500 T = 27 RF out RF outx V bias,casc M1 M3 M2 I 1 I 2 RF in C c,casc C V c,casc bias,in Gain [ db ] RF inx C c,in C c,in L s M4 I1[mA] Runs NF [ db ] Standard deviation: σ Gain 2.88 db, σ NF 1.27 db Not robust enough due to DC current variations! Page 8

9 Hardware Implementation of LPRF V.1 Improvement of Cross-Coupled CG-LNA VDD L load RF out RF outx V bias,casc M1 M2 I 1 I 2 C V bias,in c,casc C c,casc M3 M4 I bias I1[mA] µ=22.77 db σ=0.602 db N=500 T=27 Runs w/o current bias /w current bias Standard deviation: σ Gain db, σ NF 0.083dB Significantly improved! µ=2.925 db σ=83.7 mdb N=500 T=27 RF in RF inx C c,in C c,in Runs Current bias <1:32> M5 L s M6 Gain [db] LNA NF [db] Page 9

10 Hardware Implementation of LPRF V.1 Baseband Circuit BW/IF Tuning (900 khz -2 MHz) I - path Q - path V trim 4 C m C m Cross coupling resistors V CM LO + R 4 R 5 R Q C 0 C 0 R 1 R 2 R 3 C 0 LNA out LO - V CM LO + Passive mixer Baseband filter 6x Low power opamp Page 10

11 Hardware Implementation of LPRF V.1 Chip & PCB PLL out 3W Bus data input PLL & TX Digtal Demodulator & 3Wire Bus CLK ref LNA Mixer Baseband Filter BIAS Measurement driver ΣΔ ADC RFin BBI/Qmess & BBI/Qext 1200um 800um LNA Mixer Baseband Filter M e a s u r e m e n t D r i v e r LO ext 130 nm CMOS 1.2 V supply LNA 0.36x0.8 mm² BB filter 0.55x0.76 mm² QFN 48 package FR4 substrate Page 11

12 Hardware Implementation of LPRF V.1 Measurement Results -15 Simulated Measured extr. sim Measured S11 [db] -25 RX NF [db] Frequency [GHz] Frequency [MHz] 50 extr. sim Measured RX Gain [db] RX Gain [db] Pout [dbm] Frequency [MHz] st 3rd IIP3=-21.7dBm BER [%] Frequency [MHz] BER@ 2.403GHz 2.423GHz 2.443GHz 2.463GHz 2.483GHz Spec P in [dbm] Input power [dbm] Page 12

13 Hardware Implementation of LPRF V.1 Discussion Receiver frontend meets desired requirement Optimized circuit robustness P RX < 3.5 mw (w/o. LO drivers) Testchip fulfills BTLE/BT standard First time right design LO path dissipate more than 2 mw An improvement is needed! Page 13

14 Hardware Implementation of LPRF V.2 Low Band (Low IF RX) 800 MHz receiver frontend Sub-GHz FB-LNA Passive I/Q mixer Analog baseband RF 800M : RX mode selector Multi-mode PPF BBI Passive SIF mixer RF 2.4G 2.4GHz CG LNA : BBQ LO ext /LO PLL High Band (Passive SIF RX) 1.6GHz LO path 2.4GHz receiver frontend Bandgap/bias 3-wire bus interface Page 14

15 Hardware Implementation of LPRF V.2 RF 800M 800 MHz receiver frontend Sub-GHz FB-LNA Passive I/Q mixer : RX mode selector Analog baseband Multi-mode PPF BBI M1 M0 b2 b1 Multi-mode PPF b0 Passive SIF mixer RF 2.4G 2.4GHz CG LNA : BBQ Vhgain Vhgain VLLIF R2 R5 Cω R4 Cω LO ext /LO PLL VDD 1.6GHz LO path 2.4GHz receiver frontend High Band LNA Bandgap/bias Low Band LNA 3-wire bus interface VLLIF VBBI IN VBBI INX R1 R3 Cω R6 RCC1 RCC2 RCC2 VBBI outx VBBI out RFout Lload RFoutx CFB Vbias,casc AVDD CFB AVDD VBBQ IN VBBQ outx 1st stage 2nd stage VBBQ INX VBBQ out M1 M2 R1 R2 R3 R4 I1 Cc,casc Vbias,in Cc,casc I2 RX800in RX800outx RX800out Vhgain Vhgain VLLIF RX800inx Ibias M3 M4 RCM RCM M1 M2 M3 M4 RFin Ibias25u ICM25u I= 1.2 ma I= 1 ma b0 Cc,in Cc,in M5 M6 b1 RFinx Ls AVSS b2 Current bias <1:32> M5 M6 M0 M1 Page 15

16 Hardware Implementation of LPRF V.2 Top-Level Implementation DC bias block RF in 2nd stage C fb LB RX Supply ring ESD LB- LNA Passive I/Q Mixer Baseband filter PAD PAD PAD 90 µm R L,1st 1st Mixer RF in 2nd Mixer DC bias resistors DC bias resistors 1st stage 260 µm 100 µm MIM cap MIM cap BBI out BBQ out LO 1.6G input RF out LO800MHz 0 LO800MHz µm Frequency divider R L,2nd HB LNA Sliding IF Mixer PLL RF-Frontend 2.4 GHz RX Baseband filter Digital Baseband ADC Switched capacitors Filter Opamps Switched capacitors Resistors TX 560 µm I path Q path 620 µm Page 16

17 Hardware Implementation of LPRF V.2 RX Performance V.2 vs V.1 Integration of sub-gigahertz band Flexible bandwidth Reduced power consumption of LO path (V.1:2.6mW, V.2: 0.6mW) Total power consumption of RF frontend reduced (V.1: HB< 3.5mW, V.2: HB<3mW, LB<4.5mW) Improvement of all performance NF, gain, linearity Active area of RF frontend increased 5% Integration of bias and reference circuit Page 17

18 Investigation of Passive Sliding IF Mixer Topology Regular passive SIF M A2 Lower LO frequency Power efficient A1 Gain/NF sensitive to LO 0.5S 0.5A1 0.5A2 0.25S 0.25S 0.25S 0.125S * * * * -f LO1 -f LO2 f LO2 f S LO1 f RF 0.5S Extra phase control circuit Sensitive to parasitic -0.5A2 Fully quadrature SIF approach M A 2 A 1 Sensitive to Layout Lower LO frequency Power efficient 0.5S 0.5A 1 0.5A S * * * * 0.5S 0.5S -f LO1 -f -0.25S LO2 f LO2 f LO1-0.5A 1-0.5A 2 f RF 0.5S Better Gain/NF NOT sensitive to parasitic Less layout effort How should this circuit looks like? Page 18

19 Conclusion Investigation of low power receiver frontend structure Implementation of multi-mode,band receiver Investigation and improvement of RF frontend under ultra-low power condition Investigation of various passive SIF mixer topologies Development of accurate mathematical model for analyzing SIF mixer Implementation of worldwide first double quadrature passive sliding IF mixer Page 19

20 Thank you! Page 20