LTC5585 Wideband IQ Demodulator with IIP2 and DC Offset Control. Applications. Typical Application

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1 Features n 7MHz to 3GHz Operating Frequency n High IIP3: 8.7dBm at 7MHz,.7dBm at 1.9GHz n High IIP: 7dBm at 7MHz, 6dBm at 1.9GHz n User Adjustable IIP Up to 8dBm n User Adjustable DC Offset Null n High Input P1dB: 16dBm at 19MHz n I/Q Bandwidth of 3MHz or Higher n Image Rejection: 43dB at 19MHz n Noise Figure: 13.dB at 7MHz 1.7dB at 1.9GHz n Conversion Gain:.dB at 7MHz.4dB at 1.9GHz n Single-Ended RF with On-Chip Transformer n Shutdown Mode n Operating Temperature Range (T C ): 4 C to C n 4-Lead 4mm 4mm QFN Package Applications n LTE/W-CDMA/TD-SCDMA Base Station Receivers n Wideband DPD Receivers n Point-To-Point Broadband Radios n High Linearity Direct Conversion I/Q Receivers n Image Rejection Receivers Wideband IQ Demodulator with IIP and DC Offset Control Description The LTC 8 is a direct conversion quadrature demodulator optimized for high linearity receiver applications in the 7MHz to 3GHz frequency range. It is also usable in the 4MHz to 7MHz and 3GHz to 4GHz ranges with reduced performance. It is suitable for communications receivers where an RF signal is directly converted into I and Q baseband signals with bandwidth of 3MHz or higher. The incorporates balanced I and Q mixers, LO buffer amplifiers and a precision, high frequency quadrature phase shifter. The integrated on-chip broadband transformer provides a single-ended interface at the RF input with simple off-chip L-C matching. In addition, the provides four analog control voltage interface pins for IIP and DC offset correction, greatly simplifying system calibration. The high linearity of the provides excellent spurfree dynamic range for the receiver. This direct conversion demodulator can eliminate the need for intermediate frequency (IF) signal processing, as well as the corresponding requirements for image filtering and IF filtering. These I/Q outputs can interface directly to channel-select filters (LPFs) or to baseband amplifiers. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application BPF Direct Conversion Receiver with IIP and DC Offset Calibration LNA BPF LO INPUT ENABLE RF INPUT RF LO EN 9 V V CC IP AND DC OFFSET CAL IP AND DC OFFSET CAL I + I Q + Q LPF IP ADJUST DC OFFSET DC OFFSET IP ADJUST LPF VGA VGA A/D D/A D/A D/A D/A A/D IIP vs IPI, IPQ Trim Voltage I, 4 C I, C Q, 4 C Q, C f RF = 7MHz IPI, IPQ (V) 8 G9 8 TA1a 1

2 Absolute Maximum Ratings (Note 1) V CC Supply Voltage....3V to.v V CAP Voltage...V CC ±.V I, I +, Q +, Q, CMI, CMQ Voltage...V to V CC +.3V Voltage on Any Other Pin....3V to V CC +.3V LO +, LO, RF Input Power...dBm RF Input DC Voltage... ±.1V Maximum Junction Temperature (T JMAX )... 1 C Operating Temperature Range (T C )... 4 C to C Storage Temperature Range... 6 C to 1 C Pin Configuration IPQ DCOQ DCOI IPI RF REF I + I Q TOP VIEW Q CMI CMQ V CAP LO LO + EN VBIAS V CC EDC EIP UF PACKAGE 4-LEAD (4mm 4mm) PLASTIC QFN T JMAX = 1 C, θ JC = 7 C/W EXPOSED PAD (PIN ) IS, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE IUF#PBF IUF#TRPBF 8 4-Lead (4mm x 4mm) Plastic QFN 4 C to C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: For more information on tape and reel specifications, go to: Electrical Characteristics, V CC = V, EN = V, EDC = EIP = V, REF = IPI = IPQ = DCOI = DCOQ =.V, P RF = dbm ( dbm/tone for -tone IIP and IIP3 tests), P LO = 6dBm, unless otherwise noted. (Notes, 3,, 6, 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f RF(RANGE) RF Input Frequency Range (Note 1).4 to 4. GHz f LO(RANGE) LO Input Frequency Range (Note 1).4 to 4. GHz P LO(RANGE) LO Input Power Range (Note 1) to dbm f RF1 = 7MHz, f RF = 71MHz, f LO = 69MHz, L6 =.7pF, C19 = 1.pF, L = 1nH, C =.6pF f RF(MATCH) RF Input Frequency Range Return Loss > db 68 to 87 MHz f LO(MATCH) LO Input Frequency Range Return Loss > db 69 to 8 MHz G V Voltage Conversion Gain Loaded with Ω Pull-Up (Note 8). db NF Noise Figure Double-Side Band (Note 4) 13. db NF BLOCKING Noise Figure Under Blocking Conditions Double-Side Band, P RF = dbm (Note 7) 1. db IIP3 Input 3rd Order Intercept 8.7 dbm IIP Input nd Order Intercept Unadjusted, EIP = V 7 dbm IIP OPT Optimized Input nd Order Intercept EIP = V, IPI, IPQ Adjusted for Minimum IM 8 dbm P1dB Input 1dB Compression 16 dbm

3 Electrical Characteristics, V CC = V, EN = V, EDC = EIP = V, REF = IPI = IPQ = DCOI = DCOQ =.V, P RF = dbm ( dbm/tone for -tone IIP and IIP3 tests), P LO = 6dBm, unless otherwise noted. (Notes, 3,, 6, 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC OFFSET DC Offset at I/Q Outputs Unadjusted, EDC = V (Note 13) 4 mv G I/Q Gain Mismatch. db φ I/Q Phase Mismatch.3 Deg IRR Image Rejection Ratio (Note ) 4 db LO-RF LO to RF Leakage 64 dbm RF-LO RF to LO Isolation 6 db f RF1 = 19MHz, f RF = 191MHz, f LO = 194MHz, L6 = 1.pF, C19 =.1nH, L = 1.pF, C13 =.1nH f RF(MATCH) RF Input Frequency Range Return Loss > db 1.6 to.1 GHz f LO(MATCH) LO Input Frequency Range Return Loss > db 1.8 to. GHz G V Voltage Conversion Gain Loaded with Ω Pull-Up (Note 8).4 db NF Noise Figure Double-Side Band (Note 4) 1.7 db IIP3 Input 3rd Order Intercept.7 dbm IIP Input nd Order Intercept Unadjusted, EIP = V 6 dbm IIP OPT Optimized Input nd Order Intercept EIP = V, IPI, IPQ Adjusted for Minimum IM 8 dbm P1dB Input 1dB Compression 16 dbm DC OFFSET DC Offset at I/Q Outputs Unadjusted, EDC = V (Note 13) 7 mv G I/Q Gain Mismatch. db φ I/Q Phase Mismatch.7 Deg IRR Image Rejection Ratio (Note ) 43 db LO-RF LO to RF Leakage 49 dbm RF-LO RF to LO Isolation 8 db f RF1 = 1MHz, f RF = 11MHz, f LO = MHz, C17 = 1.pF, L6 = 4.7nH, C19 =.pf, L =.1nH, C =.7pF f RF(MATCH) RF Input Frequency Range Return Loss > db.3 to.36 GHz f LO(MATCH) LO Input Frequency Range Return Loss > db. to. GHz G V Voltage Conversion Gain Loaded with Ω Pull-Up (Note 8).3 db NF Noise Figure Double-Side Band (Note 4) 13. db NF BLOCKING Noise Figure Under Blocking Conditions Double-Side Band, P RF = dbm (Note 7).6 db IIP3 Input 3rd Order Intercept.9 dbm IIP Input nd Order Intercept Unadjusted, EIP = V 6 dbm IIP OPT Optimized Input nd Order Intercept EIP = V, IPI, IPQ Adjusted for Minimum IM 8 dbm P1dB Input 1dB Compression 1 dbm DC OFFSET DC Offset at I/Q Outputs Unadjusted, EDC = V (Note 13) 6 mv G I/Q Gain Mismatch. db φ I/Q Phase Mismatch 1. Deg IRR Image Rejection Ratio (Note ) 4 db LO-RF LO to RF Leakage dbm RF-LO RF to LO Isolation 6 db f RF1 = 6MHz, f RF = 61MHz, f LO = 9MHz, C17 =.pf, L6 =.7nH, L = 1.nH, C = 1pF f RF(MATCH) RF Input Frequency Range Return Loss > db.3 to 3.1 GHz f LO(MATCH) LO Input Frequency Range Return Loss > db.47 to.6 GHz G V Voltage Conversion Gain Loaded with Ω Pull-Up (Note 8).3 db 3

4 Electrical Characteristics, V CC = V, EN = V, EDC = EIP = V, REF = IPI = IPQ = DCOI = DCOQ =.V, P RF = dbm ( dbm/tone for -tone IIP and IIP3 tests), P LO = 6dBm, unless otherwise noted. (Notes, 3,, 6, 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NF Noise Figure Double-Side Band (Note 4) 13.6 db NF BLOCKING Noise Figure Under Blocking Conditions Double-Side Band, P RF = dbm (Note 7) 1. db IIP3 Input 3rd Order Intercept 7. dbm IIP Input nd Order Intercept Unadjusted, EIP = V 6 dbm IIP OPT Minimum Input nd Order Intercept EIP = V, IPI, IPQ Adjusted for Minimum IM 8 dbm P1dB Input 1dB Compression 1. dbm DC OFFSET DC Offset at I/Q Outputs Unadjusted, EDC = V (Note 13) 8 mv G I/Q Gain Mismatch. db φ I/Q Phase Mismatch 1. Deg IRR Image Rejection Ratio (Note ) 4 db LO-RF LO to RF Leakage 46 dbm RF-LO RF to LO Isolation db Power Supply and Other Parameters V CC Supply Voltage V I CC Supply Current ma I CC(LOW) Supply Current EDC = EIP = V ma I CC(OFF) Shutdown Current EN <.3V 11 9 μa t ON Turn-On Time EN Transition from Logic Low to High (Note ). µs t OFF Turn-Off Time EN Transition from Logic High to Low (Note 1).8 µs V EH EN, EDC, EIP Input High Voltage (On). V V EL EN, EDC, EIP Input Low Voltage (Off).3 V I ENH EN Pin Input Current EN =.V μa I EDCH EDC Pin Input Current EDC =.V 33 μa I EIPH EIP Pin Input Current EIP =.V μa V REF REF Pin Voltage With REF Pin Unloaded. V V REF(RANGE) REF Pin Voltage Range When Driven with External Source.4 to.7 V Z REF REF Input Impedance (Note 11) 1 kω pf DCOI, DCOQ, IPI, IPQ Pin Voltage Unloaded. V DCOI, DCOQ, IPI, IPQ Voltage Range When Driven with External Source to V REF V DCOI, DCOQ, IPI, IPQ Impedance (Note 11) 8 1 kω pf DCOI, DCOQ, IPI, IPQ Settling Time For Step Input, Output with 9% of Final Value ns DC Offset Adjustment Range DCOI, DCOQ Swept from V to 1V, EDC = V ± mv DC Offset Drift Over Temperature Unadjusted, EDC = V μv/ C V CM I +, I, Q +, Q Common Mode Voltage V CC 1. V Z OUT I +, I, Q +, Q Output Impedance Single Ended 6 Ω pf BW BB I +, I, Q +, Q Output Bandwidth Ω External Pull-Up, 3dB Corner Frequency 3 MHz 4

5 Electrical Characteristics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : Tests are performed with the test circuit of Figure 1. Note 3: The is guaranteed to be functional over the 4 C to C case temperature operating range. Note 4: DSB noise figure is measured at the baseband frequency of 1MHz with a small-signal noise source without any filtering on the RF input and no other RF signal applied. Note : Performance at the RF frequencies listed is measured with external RF and LO impedance matching, as shown in the table of Figure 1. Note 6: The complementary outputs (I +, I and Q +, Q ) are combined using a phase-shift combiner. Note 7: Noise figure under blocking conditions (NF BLOCKING ) is measured at an output frequency of 6MHz with RF input signal at f LO + 1MHz. Both RF and LO input signals are appropriately filtered, as well as the baseband output. NF BLOCKING measured at 84MHz, MHz and MHz only. Note 8: Voltage conversion gain is calculated from the average measured power conversion gain of the I and Q outputs using the test circuit shown in Figure 1. Power conversion gain is measured with a Ω differential load impedance on the I and Q outputs. Note 9: Baseband outputs have a Ω external pull-up resistor to V CC as shown in the test circuit shown in Figure 1. Note : Image rejection is calculated from the measured gain error and phase error using the method listed in the appendix. Note 11: The DCOI, DCOQ, IPI, IPQ pins have an 8k internal resistor to ground. The REF pin has a k internal resistor to ground. If unconnected, these pins will float up to mv through internal current sources. A low output resistance voltage source is recommended for driving these pins. Note 1: This is the recommended operating range, operation outside the listed range is possible with degraded performance to some parameters. Note 13: DC offset measured differentially between I + and I and between Q + and Q. The reported value is the mean of the absolute values of the characterization data distribution. Note : Baseband amplitude is within % of final value. Note 1: Baseband amplitude is at least 3dB down from its on state.

6 DC Performance Characteristics EN = V, EDC = V and EIP = V. Test circuit shown in Figure 1 SUPPLY CURRENT (ma) Supply Current vs Supply Voltage T C = 4 C T C = 8 C T C = C SUPPLY VOLTAGE (V). 8 G1 REF VOLTAGE (mv) REF Voltage vs Temperature V CC = 4.7V V CC = V V CC =.V TEMPERATURE ( C) 8 G Typical Performance Characteristics 7MHz application. V CC = V, EN = V, EDC = V, EIP = V, REF =.V,, P LO = 6dBm, f LO = 69MHz, f RF1 = 7MHz, f RF = 71MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. IIP3, P1dB (dbm) IIP3, P1dB vs Temperature (T C ) IIP3, P1dB vs Supply Voltage (V CC ) IIP3 vs LO Power I, 4 C I, C Q, 4 C Q, C IIP3 P1dB IIP3, P1dB (dbm) I, 4.7V I,.V I,.V Q, 4.7V Q,.V Q,.V IIP3 P1dB IIP3 (dbm) I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm G3 8 G4 8 G 6

7 Typical Performance Characteristics 7MHz application. V CC = V, EN = V, EDC = V, EIP = V, REF =.V,, P LO = 6dBm, f LO = 69MHz, f RF1 = 7MHz, f RF = 71MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. IIP3 (dbm) Tone IIP3 vs RF Power I, 4 C I, C Q, 4 C Q, C f RF1 = 7MHz f RF = 71MHz f LO = 69MHz RF POWER (dbm) Uncalibrated IIP vs Temperature (T C ) I, 4 C I, C Q, 4 C Q, C Uncalibrated IIP vs LO Power I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm IIP vs IPI, IPQ Trim Voltage I, 4 C I, C Q, 4 C Q, C 8 G6 f RF = 7MHz IPI, IPQ (V) 8 G IIP vs RF Tone Spacing f RF1 = 7MHz f LO = 69MHz 8 G7 I (UNCALIBRATED) I (NULLED AT 1MHz) Q (UNCALIBRATED) Q (NULLED AT 1MHz) RF TONE SPACING (MHz) 8 G x Half-IF IIP vs RF to LO Tone Spacing Q I 8 G8 f LO = 69MHz RF TO LO TONE SPACING (MHz) 8 G11 GAIN, NF (db) Noise Figure and Conversion Gain vs Temperature (T C ) I, 4 C I, C Q, 4 C Q, C NF GAIN GAIN, NF (db) Noise Figure and Conversion Gain vs LO Power I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm NF GAIN DSB NOISE FIGURE (db) Noise Figure vs RF Power and IPI, IPQ Trim Voltage I, dbm I, dbm Q, dbm Q, dbm 13 1 f RF = 89MHz f LO = 9MHz 11 f NOISE = 3.4MHz EIP = V IPI, IPQ TRIM VOLTAGE (V) 8 G1 8 G13 8 G 7

8 Typical Performance Characteristics 7MHz application. V CC = V, EN = V, EDC = V, EIP = V, REF =.V,, P LO = 6dBm, f LO = 69MHz, f RF1 = 7MHz, f RF = 71MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. DSB NOISE FIGURE (db) Noise Figure vs RF Input Power with f NOISE = 6MHz PLO = dbm PLO = 6dBm PLO = dbm f LO = 84MHz f RF = 841MHz f NOISE = 6MHz 1 RF INPUT POWER (dbm) DSB NOISE FIGURE (db) Noise Figure vs RF Input Power with f NOISE = 3.4MHz PLO = dbm PLO = 6dBm PLO = dbm f LO = 9MHz f RF = 89MHz f NOISE = 3.4MHz 1 RF INPUT POWER (dbm) DC OFFSET (mv) DC Offset vs DCOI, DCOQ Control Voltage f LO = 7MHz I, 4 C I, C Q, 4 C Q, C DCOI, DCOQ (V) 8 G1 8 G16 8 G17 DC OFFSET (mv) DC Offset vs LO Power 9 I, dbm Q, dbm I, 6dBm Q, 6dBm 8 I, dbm Q, dbm LEAKAGE (dbm), ISOLATION (dbc) LO to RF Leakage and RF to LO Isolation 3 3 L-R, 4 C R-L, 4 C L-R, C R-L, C 4 L-R, 8 C R-L, 8 C 4 L-R, C R-L, C IMAGE REJECTION (db) Image Rejection vs Temperature (Note ) T C = 4 C T C = 8 C T C = C G 8 G19 8 G 8

9 Typical Performance Characteristics 19MHz application. V CC = V, EN = V, EDC = V, REF =.V, EIP = V,, P LO = 6dBm, f LO = 194MHz, f RF1 = 19MHz, f RF = 191MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. IIP3, P1dB (dbm) IIP3, P1dB vs Temperature (T C ) IIP3, P1dB vs Supply Voltage IIP3 vs LO Power I, 4 C I, C Q, 4 C Q, C IIP3 P1dB IIP3, P1dB (dbm) I, 4.7V I,.V I,.V Q, 4.7V Q,.V Q,.V IIP3 P1dB IIP3 (dbm) I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm IIP3 (dbm) Tone IIP3 vs RF Power I, 4 C I, C f RF1 = 19MHz f RF = 191MHz f LO = 194MHz Q, 4 C Q, C 8 G RF POWER (dbm) G Uncalibrated IIP vs Temperature (T C ) Uncalibrated IIP vs LO Power I, 4 C I, C Q, 4 C Q, C I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm 8 G IIP vs IPI, IPQ Trim Voltage I, 4 C I, C f RF = 19MHz Q, 4 C Q, C 8 G IPI, IPQ (V) 8 G IIP vs RF Tone Spacing f RF1 = 19MHz f LO = 194MHz 8 G I (UNCALIBRATED) I (NULLED AT 1MHz) Q (UNCALIBRATED) Q (NULLED AT 1MHz) RF TONE SPACING (MHz) 8 G x Half-IF IIP vs RF to LO Tone Spacing Q I 8 G6 f LO = 194MHz RF TO LO TONE SPACING (MHz) 8 G9 9

10 Typical Performance Characteristics 19MHz application. V CC = V, EN = V, EDC = V, REF =.V, EIP = V,, P LO = 6dBm, f LO = 194MHz, f RF1 = 19MHz, f RF = 191MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. GAIN, NF (db) Noise Figure and Conversion Gain vs Temperature (T C ) 4 I, 4 C Q, 4 C I, C Q, C 16 NF GAIN GAIN, NF (db) Noise Figure and Conversion Gain vs LO Power 4 I, dbm Q, dbm I, 6dBm Q, 6dBm I, dbm Q, dbm 16 NF GAIN DC OFFSET (mv) DC Offset vs DCOI, DCOQ Control Voltage f LO = 19MHz I, 4 C I, C Q, 4 C Q, C DCOI, DCOQ (V) 8 G3 8 G31 8 G3 DC OFFSET (mv) DC Offset vs LO Power 1 I, dbm Q, dbm I, 6dBm Q, 6dBm 13 I, dbm Q, dbm LEAKAGE (dbm), ISOLATION (dbc) LO to RF Leakage and RF to LO Isolation L-R, 4 C R-L, 4 C L-R, C R-L, C 3 L-R, 8 C R-L, 8 C 3 L-R, C R-L, C IMAGE REJECTION (db) Image Rejection vs Temperature (Note ) T C = 4 C T C = 8 C T C = C G33 8 G34 8 G3 PERCENTAGE DISTRIBUTION (%) 4 3 Conversion Gain Distribution IIP3 Distribution, I Side IIP3 Distribution, Q Side T C = 4 C T C = 8 C T C = C CONVERSION GAIN (db) PERCENTAGE DISTRIBUTION (%) T C = 4 C T C = 8 C T C = C IIP3 (dbm) PERCENTAGE DISTRIBUTION (%) IIP3 (dbm) T C = 4 C T C = 8 C T C = C 8 G36 8 G37 8 G38

11 Typical Performance Characteristics 19MHz application. V CC = V, EN = V, EDC = V, REF =.V, EIP = V,, P LO = 6dBm, f LO = 194MHz, f RF1 = 19MHz, f RF = 191MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. PERCENTAGE DISTRIBUTION (%) DSB Noise Figure Distribution, I Side 11 T C = 4 C T C = 8 C T C = C DSB NOISE FIGURE (db) 8 G39 PERCENTAGE DISTRIBUTION (%) DSB Noise Figure Distribution, Q Side DSB NOISE FIGURE (db) T C = 4 C T C = 8 C T C = C 8 G4 PERCENTAGE DISTRIBUTION (%) IIP Distribution, I Side 7 T C = 4 C T C = 8 C T C = C G41 PERCENTAGE DISTRIBUTION (%) IIP Distribution, Q Side T C = 4 C T C = 8 C T C = C 8 G4 PERCENTAGE DISTRIBUTION (%) Gain Error Distribution.1 T C = 4 C T C = 8 C T C = C GAIN ERROR (db) 8 G43 Phase Error Distribution Image Rejection Distribution (Note ) PERCENTAGE DISTRIBUTION (%) 3 T C = 4 C T C = 8 C T C = C PERCENTAGE DISTRIBUTION (%) 4 3 T C = 4 C T C = 8 C T C = C PHASE ERROR (DEGREES) IMAGE REJECTION (dbc) 8 G44 8 G4 11

12 Typical Performance Characteristics 1MHz application. V CC = V, EN = V, EDC = V, EIP = V, REF =.V,, P LO = 6dBm, f LO = MHz, f RF1 = 1MHz, f RF = 11MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. IIP3, P1dB (dbm) IIP3, P1dB vs Temperature (T C ) I, 4 C I, C Q, 4 C Q, C IIP3 P1dB IIP3, P1dB (dbm) IIP3, P1dB vs Supply Voltage (V CC ) IIP3 vs LO Power I, 4.7V I,.V I,.V Q, 4.7V Q,.V Q,.V IIP3 P1dB IIP3 (dbm) I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm IIP3 (dbm) Tone IIP3 vs RF Power I, 4 C I, C f RF1 = 1MHz f RF = 11MHz f LO = MHz Q, 4 C Q, C 8 G RF POWER (dbm) G47 Uncalibrated IIP vs Temperature (T C ) Uncalibrated IIP vs LO Power I, 4 C I, C Q, 4 C Q, C I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm 8 G IIP vs IPI, IPQ Trim Voltage I, 4 C I, C f RF = 1MHz Q, 4 C Q, C 8 G IPI, IPQ (V) 8 G IIP vs RF Tone Spacing f RF1 = 1MHz f LO = MHz 8 G I (UNCALIBRATED) I (NULLED AT 1MHz) Q (UNCALIBRATED) Q (NULLED AT 1MHz) RF TONE SPACING (MHz) 8 G x Half-IF IIP vs RF to LO Tone Spacing Q I 8 G1 f LO = MHz RF TO LO TONE SPACING (MHz) 8 G4

13 Typical Performance Characteristics 1MHz application. V CC = V, EN = V, EDC = V, EIP = V, REF =.V,, P LO = 6dBm, f LO = MHz, f RF1 = 1MHz, f RF = 11MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. DSB NOISE FIGURE (db) Noise Figure vs RF Input Power PLO = dbm PLO = 6dBm PLO = dbm f LO = MHz f RF = 1MHz f NOISE = 6MHz 1 RF INPUT POWER (dbm) GAIN, NF (db) 4 Noise Figure and Conversion Gain vs Temperature (T C ) I, 4 C I, C Q, 4 C Q, C 16 NF GAIN GAIN, NF (db) Noise Figure and Conversion Gain vs LO Power 4 I, dbm Q, dbm I, 6dBm Q, 6dBm I, dbm Q, dbm 16 NF GAIN DC OFFSET (mv) LEAKAGE (dbm), ISOLATION (dbc) G DC Offset vs DCOI, DCOQ Control Voltage f LO = 1MHz I, 4 C I, C Q, 4 C Q, C DCOI, DCOQ (V) LO to RF Leakage and RF to LO Isolation 8 G8 L-R, 4 C R-L, 4 C L-R, C R-L, C 3 L-R, 8 C R-L, 8 C 3 L-R, C R-L, C G6 DC OFFSET (mv) IMAGE REJECTION (db) G6 DC Offset vs LO Power I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm G9 Image Rejection vs Temperature (Note ) T C = 4 C T C = 8 C T C = C G61 8 G7 13

14 Typical Performance Characteristics 6MHz application. V CC = V, EN = V, EDC = V, EIP = V, REF =.V,, P LO = 6dBm, f LO = 9MHz, f RF1 = 6MHz, f RF = 61MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. IIP3, P1dB (dbm) IIP3, P1dB vs Temperature (T C ) IIP3, P1dB vs Supply Voltage (V CC ) IIP3 vs LO Power I, 4 C I, C Q, 4 C Q, C IIP3 P1dB IIP3, P1dB (dbm) I, 4.7V I,.V I,.V Q, 4.7V Q,.V Q,.V IIP3 P1dB IIP3 (dbm) I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm IIP3 (dbm) Tone IIP3 vs RF Power I, 4 C I, C f RF1 = 6MHz f RF = 61MHz f LO = 9MHz Q, 4 C Q, C 8 G RF POWER (dbm) G63 Uncalibrated IIP vs Temperature (T C ) I, 4 C I, C Q, 4 C Q, C Uncalibrated IIP vs LO Power I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm 8 G IIP vs IPI, IPQ Trim Voltage I, 4 C I, C f RF = 6MHz Q, 4 C Q, C 8 G IPI, IPQ (V) 8 G IIP vs RF Tone Spacing f RF1 = 6MHz f LO = 9MHz 8 G66 I (UNCALIBRATED) I (NULLED AT 1MHz) Q (UNCALIBRATED) Q (NULLED AT 1MHz) RF TONE SPACING (MHz) 8 G G66 x Half-IF IIP vs RF to LO Tone Spacing f LO = 9MHz Q I RF TO LO TONE SPACING (MHz) 8 G7

15 Typical Performance Characteristics 6MHz application. V CC = V, EN = V, EDC = V, EIP = V, REF =.V,, P LO = 6dBm, f LO = 9MHz, f RF1 = 6MHz, f RF = 61MHz, f BB = MHz, P RF1 = P RF = dbm, DC Blocks and Mini-Circuits PSCJ--1 combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1. GAIN, NF (db) 4 Noise Figure and Conversion Gain vs Temperature (T C ) I, 4 C I, C Q, 4 C Q, C 16 1 NF GAIN GAIN, NF (db) 4 Noise Figure and Conversion Gain vs LO Power I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm 16 NF GAIN DSB NOISE FIGURE (db) Noise Figure vs RF Power and IPI, IPQ Trim Voltage I, dbm I, dbm Q, dbm Q, dbm 13 1 f RF = 1MHz f LO = MHz 11 f NOISE = 6MHz EIP = V IPI, IPQ TRIM VOLTAGE (V) 8 G71 8 G7 8 G73 DSB NOISE FIGURE (db) Noise Figure vs RF Input Power PLO = dbm PLO = 6dBm PLO = dbm f LO = MHz f RF = 1MHz f NOISE = 6MHz 1 RF INPUT POWER (dbm) DC OFFSET (mv) DC Offset vs DCOI, DCOQ Control Voltage f LO = 6MHz I, 4 C I, C Q, 4 C Q, C DCOI, DCOQ (V) DC OFFSET (mv) DC Offset vs LO Power I, dbm I, 6dBm I, dbm Q, dbm Q, 6dBm Q, dbm LEAKAGE (dbm), ISOLATION (dbc) 8 G74 LO to RF Leakage and RF to LO Isolation 1 L-R, 4 C R-L, 4 C L-R, C R-L, C L-R, 8 C R-L, 8 C L-R, C R-L, C G77 IMAGE REJECTION (db) G7 Image Rejection vs Temperature (Note ) T C = 4 C T C = 8 C T C = C G78 8 G76 1

16 Pin Functions IPQ, IPI (Pin 1, Pin 4): IIP Adjustment Analog Control Voltage Input for Q and I Channel. A decoupling capacitor is recommended on this pin. A low output resistance voltage source is recommended for driving these pins. These pins should be left floating if unused. DCOQ, DCOI (Pin, Pin 3): DC Offset Analog Control Voltage Input for Q and I Channel. A decoupling capacitor is recommended on this pin. A low output resistance voltage source is recommended for driving these pins. These pins should be left floating if unused. RF (Pin ): RF Input. External matching is used to obtain good return loss across the RF input frequency range. The RF pin is internally shorted to ground through internal transformer windings. The RF pin should be DC-blocked with a pf coupling capacitor. (Pins 6, 8, 13,, Exposed Pad Pin ): Ground. These pins must be soldered to the RF ground plane on the circuit board. The backside exposed pad ground connection should have a low inductance connection and good thermal contact to the printed circuit board ground plane using many through-hole vias. See Figures and 3. EN (Pin 7): Enable Pin. When the voltage on the EN pin is a logic high, the chip is completely turned on; the chip is completely turned off for a logic low. An internal k pull-down resistor ensures the chip remains disabled if there is no connection to the pin (open-circuit condition). V BIAS (Pin 9): This pin can be pulled to ground through a resistor to lower the current consumption of the chip. See Applications Information. V CC (Pin ): Positive Supply Pin. This pin should be bypassed with shunt pf and 1µF capacitors. EDC (Pin 11): DC Offset Adjustment Mode Enable Pin. When the voltage on the EDC pin is a logic high, the DC offset control circuitry is enabled. The circuitry is disabled for a logic low. An internal k pull-down resistor ensures the circuitry remains disabled if there is no connection to the pin (open-circuit condition). EIP (Pin 1): IP Offset Adjustment Mode Enable Pin. When the voltage on the EIP pin is a logic high, the IP adjustment circuitry is enabled. The circuitry is disabled for a logic low. An internal k pull-down resistor ensures the circuitry remains disabled if there is no connection to the pin (open-circuit condition). LO +,LO (Pin 1, Pin 16): LO Inputs. External matching is required to obtain good return loss across the LO input frequency range. Can be driven single ended or differentially with an external transformer. The LO pins should be DC-blocked with a pf coupling capacitor. V CAP, CMQ, CMI (Pin 17, Pin, Pin 19): Common Mode Bypass Capacitor Pins. It is recommended that CMI and CMQ be connected to V CAP through.1µf capacitors. Nothing else should be connected to V CAP since it is connected to V CC inside the chip. I +, I, Q +, Q (Pin 3, Pin, Pin 1, Pin ): Differential Baseband Output Pins for the I Channel and Q Channel. The DC bias point is V CC 1.V for each pin. These pins must have an external Ω or an inductor pull-up to V CC. REF (Pin 4): Voltage Reference Input for Analog Control Voltage Pins. A decoupling capacitor is recommended on this pin. A low output resistance voltage source is recommended for driving this pin. This pin should be left floating if unused. 16

17 Block Diagram 6 RF 17 V CC V CAP CMI 19 I + 3 I 1 16 LO + LO 9 IP AND DC OFFSET CAL DCOI 3 IPI 4 EDC 11 EIP 1 REF 4 IP AND DC OFFSET CAL IPQ 1 DCOQ 9 7 V BIAS EN BIAS 8 13 EXPOSED PAD Q + 1 Q CMQ 8 BD 17

18 Test Circuit RF.1".6" DC.1" NELCO N4-13 C9 R9 R11 C1 C R13 R C3 I OUT Q + OUT I + OUT Q OUT C REF IPQ DCOQ DCOI IPI RF EN C3 C C33 C17 L6 C34 C31 C3 C C11 IPQ CMQ DCOQ V CAP DCOI LO IUF 1 IPI LO + RF 13 REF I + I Q + Q CMI EN VBIAS V CC EDC EIP C1 C36 C37 3 T L C13 C C1 EIP EDC C16 LO V CC 4.7V TO.V 8 F1 RF MATCH LO MATCH FREQUENCY RANGE C17 L6 C19 C13 L C 7MHz.7pF 1.pF 1nH.6pF 19MHz 1.pF.1nH.1nH 1.pF 1MHz.pF 4.7nH.1nH.7pF 6MHz.pF.7nH 1.nH 1pF REF DES VALUE SIZE VENDOR REF DES VALUE SIZE VENDOR C, C11, C31-C3.1μF 4 Murata L, L6 See Table 4 Murata C1, C1, C, C36, C37 pf 4 Murata R9, R11, R13, R Ω 4 Vishay C13, C, C17, C19 See Table 4 Murata T1 4:1 8 Anaren BD86JA C16, C1, C, C9, C3 1μF 4 Murata Figure 1. Test Circuit Schematic

19 Test Circuit Figure. Component Side of Evaluation Board Figure 3. Bottom Side of Evaluation Board Applications Information The is an IQ demodulator designed for high dynamic range receiver applications. It consists of RF transconductance amplifiers, I/Q mixers, quadrature LO amplifiers, IIP and DC offset correction circuitry, and bias circuitry. Operation As shown in the Block Diagram for the, the RF signal is applied to the inputs of the RF transconductor V-to-I converters and is then demodulated into I/Q baseband signals using quadrature LO signals which are internally generated by a precision 9 phase shifter. The demodulated I/Q signals are lowpass filtered on-chip with a 3dB bandwidth of 3MHz. The differential outputs of the I-channel and Q-channel are well matched in amplitude and their phases are 9 apart. RF Input Port Figure 4 shows the demodulator s RF input which consists of an integrated transformer and high linearity transconductance amplifiers (V-I converters). The primary side of the transformer is connected to the RF input pin. The secondary side of the transformer is connected to the RF INPUT (MATCHED) C pf L6 C17 C19 BIAS RF 8 F4 Figure 4: Simplified Schematic of the RF Pin Interface 19

20 Applications Information differential inputs of the transconductance amplifiers. External DC voltage should not be applied to the RF input pin. DC current flowing into the primary side of the transformer may cause damage to the integrated transformer. A series DC blocking capacitor should be used to couple the RF input pin to the RF signal source. The RF input port can be externally matched over the operating frequency range with simple L-C matching. An input return loss better than db can be obtained over a bandwidth of better than 16% with this method. Figure shows the RF input return loss for various matching component values. Table 1 shows the impedance and input reflection coefficient for the RF input without using any external matching components. The input transmission line length is de-embedded from the measurement. Larger bandwidths can be obtained by using multiple L-C sections. For example Figure 6 shows a -section L-C match having a bandwidth of about 38% where return loss is >db. Figure 7 shows the RF input return loss for the wide bandwidth match. Broadband Performance To get an idea of the broadband performance of the, a 6dB pad can be put on the RF and LO ports, and the ports can be left unmatched. The measured RF performance for this configuration is shown in Figures 8, 9, and 11 with the 6dB pad de-embedded. The RF RETURN LOSS (db) FREQUENCY (GHz) 8 F L6 =.7pF, C19 = 1pF L6 = 1.pF, C19 =.1nH C17 = 1.pF, L6 = 4.7nH, C19 =.pf C17 =.pf, L6 =.7nH Figure. RF Input Return Loss Table 1. RF Input Impedance FREQUENCY S11 (MHz) INPUT IMPEDANCE (Ω) MAG ANGLE ( ) j j j j j j j j j j j j j j j j j j j C L7 pf RF INPUT 3.9nH MHz TO MHz RETURN LOSS (db) L6 8.nH C17 1.pF BIAS RF C19.pF Figure 6. Wide Bandwidth RF Input Match 1 L7 = 3.9nH, C17 = 1.pF L6 = 8.nH, C19 =.pf FREQUENCY (GHz) 8 F7 Figure 7. RF Input Return Loss for Wideband Match 8 F6

21 Applications Information IIP3, P1dB (dbm) I, 4 C I, C Q, 4 C Q, C IIP3 P1dB GAIN, NF (db) I, 4 C I, C Q, 4 C Q, C NF GAIN F8 8 F Figure 8. Broadband IIP3 and IP1dB Figure. Broadband NF and Gain I, 4 C I, C Q, 4 C Q, C IMAGE REJECTION (db) T C = 4 C T C = 8 C T C = C F9 8 F11 Figure 9. Broadband IIP Figure 11. Broadband Image Rejection tone spacing is 1MHz, and f LO is MHz lower than f RF. The conversion gain is lower than under the impedance matched condition, and correspondingly the P1dB, IIP3, and NF are higher. As shown, the part can be used at frequencies outside its specified operating range with reduced conversion gain and higher NF. LO Input Port The demodulator s LO input interface is shown in Figure 1. The input consists of a high precision quadrature phase shifter which generates and 9 phase shifted LO signals for the LO buffer amplifiers to drive the I/Q mixers. DC blocking capacitors are required on the LO + and LO inputs. The differential LO input impedance and S parameters with the input transmission lines and balun de-embedded are listed in Table. Figure 13 shows LO input return loss using the ANAREN BD86JA 4:1 balun with various matching component values. For optimum IIP and large-signal NF performance the LO inputs should be driven differentially with a 4:1 balun such as the ANAREN BD86JA or BD4JAHF. As shown in Figure, the LO input can also be driven single-ended from either the LO + or LO input. The unused port should be DC-blocked and terminated with a Ω load. Figure 1 compares the uncalibrated IIP performance of single ended versus differential LO drive. 1

22 Applications Information V CC LO INPUT (MATCHED) L C ANAREN BD86JA C13 C37 pf LO + LO TO IDENTICAL Q-CHANNEL C36 pf PHASE SHIFTER 8 F1 Figure 1. Simplified Schematic of LO Input Interface with External Matching Components Table. LO Input Impedance (Differential) FREQUENCY S11 (MHz) INPUT IMPEDANCE (Ω) MAG ANGLE ( ) 4 1. j j j j j j j j j j j j j j j j j j j RETURN LOSS (db) 1 L = 1nH, C =.6pF L = 1.pF, C13 =.1nH L =.1nH, C =.7pF L = 1.nH, C = 1pF FREQUENCY (GHz) 8 F13 Figure 13. LO Input Return Loss

23 Applications Information V CC LO INPUT (MATCHED) L C C13 Ω C37 pf LO + LO TO IDENTICAL Q-CHANNEL C36 pf PHASE SHIFTER 8 F Figure. Recommended Single-Ended LO Input Configuration F1 SINGLE-ENDED LO, I SIDE DIFFERENTIAL LO, I SIDE SINGLE-ENDED LO, Q SIDE DIFFERENTIAL LO, Q SIDE Figure 1. Broadband IIP with Differential and Single-Ended LO Drive I-Channel and Q-Channel Outputs The phase relationship between the I-channel output signal and the Q-channel output signal is fixed. When the LO input frequency is higher (or lower) than the RF input frequency, the Q-channel outputs (Q +, Q ) lead (or lag) the I-channel outputs (I +, I ) by 9. Each of the I-channel and Q-channel outputs is internally connected to V CC through a Ω resistor. In order to maintain an output DC bias voltage of V CC 1.V, external Ω pull-up resistors or equivalent 1mA DC current sources are required. Each single-ended output has an impedance of Ω in parallel with a 6pF internal capacitor. With an external Ω pull-up resistor this forms a lowpass filter with a 3dB corner frequency at 3MHz. The outputs can be DC coupled or AC coupled to external loads. The voltage conversion gain is reduced by the external load by: 1 Log + Ω db R PULL-UP R LOAD(SE) when the output port is terminated by R LOAD(SE). For instance, the gain is reduced by 6dB when each output pin is connected to a Ω load (or Ω differentially). The output should be taken differentially (or by using differential-tosingle-ended conversion) for best RF performance, including NF and IIP. When no external filtering or matching components are used, the output response is determined by the loading capacitance and the total resistance loading the outputs. The 3dB corner frequency, f C, is given by the following equation: f C = [π(r LOAD(SE) Ω R PULL-UP ) (6pF)] 1 Figure 16 shows the actual measured output response with various load resistances. Figure 17 shows a simplified model of the I, Q outputs with a Ω differential load and Ω pull-ups. The 1dB bandwidth in this configuration is about MHz, or about twice the 1dB bandwidth with no load. 3

24 Applications Information CONVERSION GAIN (db) R LOAD(DIFF) = Ω, BW = 8MHz 7 R LOAD(DIFF) = Ω, BW = 63MHz 8 R LOAD(DIFF) = 4Ω, BW = 3MHz 9 R LOAD(DIFF) = 1k, BW = 46MHz BASEBAND FREQUENCY (GHz) 8 G16 Figure 16. Conversion Gain Baseband Output Response with R LOAD(DIFF) = Ω, Ω, 4Ω and 1k and R PULL-UP = Ω Figure shows a simplified model of the I, Q outputs with a L-C matching network for bandwidth extension. Capacitor C S serves to filter common mode LO switching noise immediately at the demodulator outputs. Capacitor C C in combination with inductor L S is used to peak the output response to give greater bandwidth of 6MHz. In this case, capacitor C C was chosen as a common mode capacitor instead of a differential mode capacitor to increase rejection of common mode LO switching noise. When AC output coupling is used, the resulting highpass filter s 3dB roll-off frequency, f C, is defined by the R-C constant of the external AC coupling capacitance, C AC, and the differential load resistance, R LOAD(DIFF) : f C = [π R LOAD(DIFF) C AC ] 1 V CC V CC 6pF Ω Ω 6pF 1.nH PACKAGE PARASITICS I + R PULL-UP Ω R PULL-UP Ω 3mA 1k AC CURRENT SOURCE 3mA 1.nH.pF I.pF 1dB BW = MHz R LOAD(DIFF) Ω 8 F17 Figure 17. Simplified Model of the Baseband Output V CC V CC 6pF Ω Ω 6pF 1.nF PACKAGE PARASITICS I + C S pf L S nh C C 4pF R PULL-UP Ω R PULL-UP Ω 3mA DC 1k AC CURRENT SOURCE 1.nF.pF 3mA DC I.pF L S nh C S pf 6mA MAX DC C C 4pF LOWPASS 1dB BW = 6MHz R LOAD(DIFF) Ω 8 F Figure. Simplified Model of the Baseband Output Showing Bandwidth Extension with External L, C Matching 4

25 Applications Information Care should be taken when the demodulator s outputs are DC coupled to the external load to make sure that the I/Q mixers are biased properly. If the current drain from the outputs exceeds about 6mA, there can be significant degradation of the linearity performance. Keeping the common mode output voltage of the demodulator above 3.1V, with a V supply, will ensure optimum performance. Each output can sink no more than 3mA when the outputs are connected to an external load with a DC voltage higher than V CC 1.V. In order to achieve the best IIP performance, it is important to minimize high frequency coupling among the baseband outputs, RF port, and LO port. Although it may increase layout complexity, routing the baseband output traces on the backside of the PCB can improve uncalibrated IIP performance. Figure 19 shows the alternate layout having the baseband outputs on the backside of the PCB. As shown in Figure 1, the REF pin is similar to the DCOI pin, but the bias current source is µa, and the internal resistance is k. If this pin is left disconnected, it will self-bias to mv. A low impedance voltage source with a source resistance of less than Ω is recommended to drive this pin. The control voltage range of the DCOI, DCOQ, IPI and IPQ pins is set by the REF pin. This range is equal to V to twice the voltage on the REF pin, whether internally or externally applied. It is recommended to decouple any AC noise present on the signal lines that connect to the analog control-voltage inputs. A shunt capacitor to ground placed close to these pins can provide adequate filtering. For instance, a value of pf on the DCOI, DCOQ, IPI and IPQ pins will provide a corner frequency of around 6 to 7MHz. A similar corner frequency can be obtained on the REF pin with a value of 39pF. Using larger capacitance values such as.1µf is recommended on these pins unless a faster control V CC 6.µA DCOI, DCOQ, IPI, IPQ 8k 8 F Figure. Simplified Schematic of the Interface for the DCOI, DCOQ, IPI and IPQ Pins V CC Figure 19. Alternate Layout of PCB with Baseband Outputs on the Backside Analog Control Voltage Pins Figure shows the equivalent circuit for the DCOI, DCOQ, IPI, and IPQ pins. Internal temperature compensated 6.μA current sources keep these pins biased at a nominal mv through 8k resistors. A low impedance voltage source with a source resistance of less than Ω is recommended to drive these pins. REF µa k 8 F1 Figure 1. Simplified Schematic of the REF Pin Interface

26 Applications Information response is needed. Figure shows the input response 3dB bandwidth for the pins versus shunt capacitance when driven from a Ω source. RESPONSE (db) DCOI, DCOQ; C = 47pF DCOI, DCOQ; C = pf IPI, IPQ; C = pf FREQUENCY (MHz) F Figure. Input Response Bandwidth for the DCOI, DCOQ, IPI and IPQ Pins DC Offset Adjustment Circuitry Any sources of LO leakage to the RF input of a direct conversion receiver will contribute to the DC offsets of its baseband outputs. The features DC offset adjustment circuitry to reduce such effects. When the EDC pin is a logic high the circuitry is enabled and the resulting DC offset adjustment range is typically ±mv. In a typical direct conversion receiver application, DC offset calibration will be done periodically at a time when no receive data is present and when the receiver DC levels have sufficiently settled. DC Offset Adjustment Example Figure 3 shows a typical direct conversion receive path having a DSP feedback path for DC offset adjustment. Any sources of LO leakage to the RF input of the demodulator will contribute to the DC offset of the receiver. This includes both static and dynamic DC offsets. If the coupling is static in nature due to fixed board-level leakage paths, the resulting DC offset does not typically need to be adjusted at a high repetition rate. Dynamic DC offsets due to transmitter transient leakage or antenna reflection can be much harder to correct for and will require a faster update rate from the DSP. LO leakage into the RF port of the demodulator causes a DC offset at the baseband outputs which is then multiplied by the gain in the baseband path. The usable ADC voltage window will be reduced by the amplified DC offset, resulting in lower dynamic range. Using DSP, this DC offset value can be averaged and sampled at a given update rate and then a 1D minimization algorithm can be applied before a new DCOI or DCOQ control signal is generated to minimize the offset. The 1-D minimization algorithm can be implemented in many ways such as golden-section search, backtracking, or Newton s method. IM Adjustment Circuitry The also contains circuitry for the independent adjustment of IM levels on the I and Q channels. When the EIP pin is a logic high, this circuitry is enabled and the IPI and IPQ analog control voltage inputs are able DSP BPF DCOI DAC DC AVERAGING LOWPASS FILTER 1-D MINIMIZATION ALGORITHM LNA ADC SAMPLE AND HOLD f LO = 19MHz 8 F3 Figure 3. Block Diagram of a Receiver with a DSP Feedback Loop for DC Offset Adjustment 6

27 Applications Information to adjust the IM level. The IM level can be effectively minimized over a large range of the baseband bandwidth. The circuitry has an effective baseband frequency upper limit of about MHz. Any IM component that falls in this frequency range can be minimized. Beyond this frequency, the gain of the IM correction amplifier falls off appreciably and the circuit no longer improves IP performance. The lower baseband frequency limit of the IM adjustment circuitry is set by the common mode reference decoupling capacitor at the CMI and CMQ pins. Below this frequency the circuit can not minimize the IM component. Figure 4 shows the CMI (and identical CMQ) pin interface. These pins have an internal 4pF decoupling capacitance to V CC, to provide a reference for the IP adjustment circuitry. The lower 3dB frequency limit, f C, of the circuitry is set by the following equation: f C = [π (4pF + C CM(EXT) )] 1 Without any external capacitor on the CMI or CMQ pin the lower limit is 8MHz. By adding a.1μf capacitor, C CM(EXT), between the CMI and CMQ pins to V CAP, the lower 3dB frequency corner can be reduced to 3kHz. Figure shows IIP as a function of RF frequency spacing versus common mode decoupling capacitance values of.1µf and pf. There is effectively no limit on the size of this capacitor, other than the impact it has on enable time for the IM circuitry to be operational. When the chip is disabled, there is no current in the I or Q mixers, so the common mode V CAP CMI OR CMQ 4pF V CC output voltage will be equal to V CC (if no DC common mode current is being drawn by external baseband circuitry such as a baseband amplifier). When the chip is enabled, the off-chip common mode decoupling capacitor must charge up through a Ω resistor. The time constant for this is essentially Ω times the common mode decoupling capacitance value. For example, with a.1µf capacitor this wait time is approximately 3μs. Figure 6 shows the pulsed enable response of the common-mode output voltage with.1µf on the CMI and CMQ pins f RF1 = 1MHz f LO = MHz.1 1 RF FREQUENCY SPACING (MHz) 8 F Figure. IIP vs Common Mode Decoupling Capacitance V CM (V) µF (UNCALIBRATED).1µF (NULLED IPI =.1V) pf (UNCALIBRATED) pf (NULLED IPI =.1V) C CMI,Q =.1µF EN PULSE OFF EN PULSE ON CMI, CMQ ENABLE VOLTAGE (V) 8 F4 3 BASEBAND OUTPUTS TIME (µs) 8 F6 Figure 4. Equivalent Circuit of the CMI and CMQ Pin Interfaces Figure 6. Common Mode Output Voltage with a Pulsed Enable 7

28 Applications Information IM Suppression Example IM adjustment circuitry can be used in a typical transceiver loop-back application as shown in Figure 7. In this example a -tone SSB training source of f1 = MHz and f = 1MHz is generated in DSP and upconverted by the LTC88-1 quadrature modulator to RF tones at 197MHz and 1971MHz using an LO source at 19MHz. A narrowband RF filter is required to remove the IM component generated by the LTC88-1. During the loopback test these RF tones are routed through high isolation switches and an attenuation pad to the demodulator input. The tones are then downconverted by the same LO source at 19MHz to produce two tones at the baseband outputs of MHz and 1MHz plus an IM impairment signal at 1MHz. After baseband channel filtering and amplification the output of the ADC is filtered by a 1MHz bandpass filter in DSP to isolate the IM tone. The power in this tone is calculated in DSP and then a 1-D minimization algorithm is applied to calculate the correction signal for the IPI control voltage pin. The 1-D minimization algorithm can be implemented in many ways such as golden-section search, backtracking or Newton s method. Enable Interface A simplified schematic of the EN pin is shown in Figure 8. The enable voltage necessary to turn on the is V. To disable or turn off the chip, this voltage should be below.3v. If the EN pin is not connected, the chip is disabled. Figures 9 and 3 show the simplified schematics for the EDC and EIP pins Figure 8. Simplified Schematic of the EN Pin Interface EDC EN V CC k k EN V CC k k 8 F8 8 F9 Figure 9. Simplified Schematic of the EDC Pin Interface DAC DSP 1-D MINIMIZATION ALGORITHM LNA IPI ADC 1MHz BPF RMS DETECTION LOOPBACK f LO = 19MHz f1 = MHz PA LTC88-1 DAC + f = 1MHz 8 F7 Figure 7. Block Diagram for a Direct Conversion Transceiver with IM Adjustment. Only the I-Channel Is Shown 8

29 Applications Information V CC V CC EIP k k k OPTIONAL R TO REDUCE CURRENT C OPT V BIAS Ω EN 8 F3 Figure 3. Simplified Schematic of the EIP Pin Interface 8 F31 It is important that the voltage applied to the EN, EDC and EIP pins should never exceed V CC by more than.3v. Otherwise, the supply current may be sourced through the upper ESD protection diode connected at the pin. Under no circumstances should voltage be applied to the enable pins before the supply voltage is applied to the V CC pin. If this occurs, damage to the IC may result. Reducing Power Consumption Figure 31 shows the simplified schematic of the V BIAS interface. The V BIAS pin can be used to lower the mixer core bias current and total power consumption for the chip. For example, adding 94Ω from the V BIAS pin to will lower the DC current to 1mA, at the expense of reduced IIP3 performance. Figure 3 shows IIP3 and P1dB performance versus DC current and resistor value. An optional capacitor, C OPT in Figure 31, has minimal effect on improving PSRR and IIP. 19MHz Receiver Application Figure 33 shows a typical receiver application consisting of the chain of LNA, demodulator, lowpass filter, ADC driver, and ADC. Total DC power consumption is about.1w. Full-scale power at the RF input is -6dBm. The Chebychev lowpass filter with unequal terminations is designed using the method shown in the appendix. Filter component values are then adjusted for the best overall response Figure 31. Simplified Schematic of the V BIAS Pin Interface IIP3, P1dB (dbm) I, 19mA I, 17mA, 487Ω I, 1mA, 94Ω f RF = 19MHz IIP3 P1dB Q, 19mA Q, 17mA, 487Ω Q, 1mA, 94Ω G1 Figure 3. IIP3 and P1dB vs DC Current and V BIAS Resistor Value and available component values. A positive voltage gain slope with frequency is necessary to compensate for the roll-off contributed by the ADC Driver and Anti-Alias Filter. From the chain analysis shown in Figure 34, the IIP3-NF dynamic range figure of merit (FOM) is 4.3dB at the LNA input, 7.dB at the demodulator input, and.8db at the ADC driver amp input. The measured 6th order lowpass baseband response is shown in Figure 3. 9

30 Applications Information C3 4.7µF C pf RF INPUT 19MHz TO 199MHz L 8.nH C1 pf R1 49.9Ω R.6k AVAGO MGA-634P8 BIAS LNA V 48mA R3 Ω L 8.nH C pf L3 4.7nH LO INPUT 19MHz 6dBm C6 4.7µF C4 pf C7.pF C11 pf RF LO + V ma V CC L7 nh L8 nh R4 1Ω R 1Ω R6 3Ω R7 3Ω C.1µF C19.4pF 4MHz LOWPASS FILTER 4MHz ANTI-ALIAS FILTER L 47nH L6 47nH L4 4.7nH T1 ANAREN BD4JAHF C8.pF I + I LO C pf C9 47pF C1 47pF C17 1µF C 1pF C13 1pF C16 1pF C1 1pF + V ma + C.4pF R8 44Ω V OCN LTC649 R9 44Ω R1 Ω R11 Ω R 138Ω R1 3Ω C1 6pF 1.8V 6mA V DD + D13 L9 nh AIN + L11 nh LTC L nh L1 nh VCM ADC A IN D R13 138Ω R Ω R16 3Ω C 6pF R17 83Ω R 83Ω R19 Ω 8 F33 R Ω C3 1µF CONTROL Figure 33. Simplified Schematic of 19MHz Receiver, (Only I-Channel Is Shown) 3

31 Applications Information 19MHz Receiver Chain Analysis G = 3.6dB NF = 3.7dB IIP3 = 8dBm FOM = 4.3dB G = 1.dB NF =.3dB IIP3 =.8dBm FOM = 7.dB G = 1.dB NF =.8dB IIP3 =.7dBm FOM =.8dB G = 1.8dB NF =.db IIP3 =.4dBm FOM =.8dB G = 1.dB NF = 4.3dB IIP3 = 48.7dBm FOM = 4.4dB G = db NF = 3.1dB IIP3 = 47.dBm FOM = 4.4dB MGA-634P8 4MHz LPF LTC649 4MHz AAF LTC G = 17.4dB NF =.44dB OIP3 = 36dBm G = 6.3dB NF = 13dB IIP3 = 7dBm G =.3dB NF =.3dB G = 3dB NF = db OIP3 = dbm G = 1.dB NF = 1.dB G = db NF = 3.1dB IP3 = 47.dBm 8 F34 Figure MHz Receiver Chain Analysis GAIN (db) FREQUENCY (MHz) For this example, receiver noise floor is approximated by a measurement at 84MHz, where adequate filtering for RF and LO signals was possible. Using the test data from Figure 37, the receiver noise figure for the I-channel (Ch 1) is calculated using the 6dBm input power, 7Hz bin width, 4MHz bandwidth, and 116.3dBFS measured in-band noise floor: SNR IN = P IN P SNR IN = 6 ( ) = 9dB SNR OUT = Log (BinW/BW) Floor Figure 3. Baseband Gain Response without LNA The receiver spurious free dynamic range (SFDR) in terms of FOM can be calculated using the following equations: FOM = IIP3 NF SFDR = /3(FOM P ) P = 174dBm + Log (BW Hz ) where P is the input noise power and 174dBm is the input thermal noise power in a 1Hz bandwidth. A measured -tone output spectrum at 19MHz is shown in Figure 36. IIP3 is calculated from the -tone IM3 levels: IIP3 = ( 7.67 ( 76.63))/ 13 IIP3 = 1.78dBm 8 F3 SNR OUT = = 73dB NF = SNR IN SNR OUT NF = 9 73 = 19dB Finally, an approximate receiver spurious free dynamic range can be calculated using the measured data at 84MHz and 19MHz: SFDR = (IIP3 NF P )/3 SFDR = ( ( ))/3 SFDR = 67.dB (I-channel) Measured IIP3 is.3db higher for the Q-channel, so the resulting SFDR is: SFDR = 68.7dB (Q-channel) 31

32 Applications Information Figure 36. f RF = 199MHz and 19MHz -Tone Receiver Test, f LO = 193MHz. Ch.1 Is the I-Channel and Ch. Is the Q-Channel. Tested without LNA 3

33 Applications Information Figure 37. f RF = 84MHz Receiver Noise Floor Test, f LO = 846MHz. Ch.1 Is the I-Channel and Ch. Is the Q-Channel. Tested without LNA 33