High IP3, 10 MHz to 6 GHz, Active Mixer ADL5801

Transcription

1 FEATURES Broadband upconverter/downconverter Power conversion gain of 1.8 db Broadband RF, LO, and IF ports SSB noise figure (NF) of 9.7 db Input IP3: 8. dbm Input P1dB: 13.3 dbm Typical LO drive: dbm Single-supply operation: V at 13 ma Adjustable bias for low power operation Exposed paddle, mm mm, -lead LFCSP package APPLICATIONS Cellular base station receivers Radio link downconverters Broadband block conversion Instrumentation GENERAL DESCRIPTION The ADL81 uses a high linearity, doubly balanced, active mixer core with integrated LO buffer amplifier to provide high dynamic range frequency conversion from 1 MHz to GHz. The mixer benefits from a proprietary linearization architecture that provides enhanced input IP3 performance when subject to high input levels. A bias adjust feature allows the input linearity, SSB noise figure, and dc current to be optimized using a single control pin. An optional input power detector is provided for adaptive bias control. The high input linearity allows the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in degradation in dynamic performance. The adaptive bias feature allows the part to provide high input IP3 performance when presented with large blocking signals. When blockers are removed, the ADL81 can automatically bias down to provide low noise figure and low power consumption. High IP3, 1 MHz to GHz, Active Mixer ADL81 LOIP LOIN FUNCTIONAL BLOCK DIAGRAM 1 3 VPLO NC 3 ADL VPLO IFON IFOP 1 DET 19 VI ENBL VSET DETO Figure VPRF 17 1 RFIP 1 RFIN 1 13 VPDT The balanced active mixer arrangement provides superb LO-to- RF and LO-to-IF leakage, typically better than dbm. The IF outputs are designed to provide a typical voltage conversion gain of 7.8 db when loaded into a Ω load. The broad frequency range of the open-collector IF outputs allows the ADL81 to be applied as an upconverter for various transmit applications. The ADL81 is fabricated using a SiGe high performance IC process. The device is available in a compact mm mm, -lead LFCSP package and operates over a C to temperature range. An evaluation board is also available Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 91, Norwood, MA -91, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADL81 TABLE OF CONTENTS Features... 1 Applications... 1 Functional Block Diagram... 1 General Description... 1 Revision History... Specifications... 3 Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... 7 Typical Performance Characteristics... 8 Downcoverter Mode with a Broadband Balun... 8 Downconverter Mode with a Mini-Circuits TC1-1-3M+ Input Balun... 1 Downconverter Mode with a Johanson 3. GHz Input Balun... 1 Downconverter Mode with a Johanson.7 GHz Input Balun... 1 Upconverter Mode with a 9 MHz Output Match Upconverter Mode with a.1 GHz Output Match... Spur Performance... 3 Circuit Description... 7 LO Amplifier and Splitter... 7 RF Voltage-to-Current (V-to-I) Converter... 7 Mixer Core... 8 Mixer Output Load... 8 RF Detector... 8 Bias Circuit... 9 Applications Information... 3 Basic Connections... 3 RF and LO Ports... 3 IF Port Downconverting to Low Frequencies... 3 Broadband Operation Single-Ended Drive of RF and LO Inputs... 3 Evaluation Board Outline Dimensions Ordering Guide REVISION HISTORY 3/1 Rev. C to Rev. D Changes to Pin 9, Table /13 Rev. B to Rev. C Changes to Table /13 Rev. A to Rev. B Added Disable Voltage and Enable Voltage; Table Changes to Table and Figure Added Downconverting to Low Frequencies Section and Figure 97; Renumbered Sequentially... 3 Added Broadband Operation Section and Figure 98 to Figure Added Single-Ended Drive of RF and LO Inputs Section and Figure 1 to Figure Updated Outline Dimensions /11 Rev. to Rev. A Changes to Specifications Section... 3 Changes to Typical Performance Characteristics Section... 8 Changes to Spur Performance Section... 3 Changes to RF Voltage-to-Current (V-to-I) Converter Section... 7 Changes to RF Detector Section... 8 Changes to RF and LO Ports Section... 3 /1 Revision : Initial Version Rev. D Page of

3 ADL81 SPECIFICATIONS VS = V, T A = C, frf = 9 MHz, flo = (frf 13 MHz), LO power = dbm, Z 1 = Ω, VSET = 3. V, unless otherwise noted. Table 1. Parameter Test Conditions Min Typ Max Unit RF INPUT INTERFACE Return Loss Tunable to > db over a limited bandwidth 1 db Input Impedance Ω RF Frequency Range 1 MHz OUTPUT INTERFACE Output Impedance Differential impedance, f = MHz 3 Ω IF Frequency Range Can be matched externally to 3 MHz LF MHz DC Bias Voltage Externally generated.7 VS. V LO INTERFACE LO Power 1 +1 dbm Return Loss 1 db Input Impedance Ω LO Frequency Range 1 MHz POWER INTERFACE Supply Voltage.7. V Quiescent Current Resistor programmable 13 ma Disable Current ENBL pin high to disable the device ma Disable Voltage ENBL pin high to disable the device. V Enable Voltage ENBL pin low to enable the device 1.8 V Enable Time Time from ENBL pin low to enable 18 ns Disable Time Time from ENBL pin high to disable 8 ns DYNAMIC PERFORMANCE at frf = 9 MHz/19 MHz 3 Power Conversion Gain frf = 9 MHz 1.8 db frf = 19 MHz 1.8 db Voltage Conversion Gain frf = 9 MHz 7.8 db frf = 19 MHz 7.8 db SSB Noise Figure fcent = 9 MHz, VSET =. V 9.7 db fcent = 19 MHz, VSET =. V 11. db SSB Noise Figure Under Blocking fcent = 9 MHz 19. db fcent = 19 MHz db Input Third-Order Intercept 7 fcent = 9 MHz 8. dbm fcent = 19 MHz. dbm Input Second-Order Intercept 8 fcent = 9 MHz 3 dbm fcent = 19 MHz 9.7 dbm Input 1 db Compression Point frf = 9 MHz 13.3 dbm frf = 19 MHz 1.7 dbm LO-to-IF Output Leakage Unfiltered IF output 7 dbm LO-to-RF Input Leakage 3 dbm RF-to-IF Output Isolation 3 dbc IF/ Spurious 9 dbm input power, frf = 9 MHz 7. dbc dbm input power, frf = 19 MHz 3 dbc IF/3 Spurious 9 dbm input power, frf = 9 MHz. dbc dbm input power, frf = 19 MHz 7. dbc Rev. D Page 3 of

4 ADL81 Parameter Test Conditions Min Typ Max Unit DYNAMIC PERFORMANCE at frf = MHz 1 Power Conversion Gain 11.1 db Voltage Conversion Gain.1 db SSB Noise Figure fcent = MHz, VSET =. V 1. db Input Third-Order Intercept 1 fcent = MHz. dbm Input Second-Order Intercept 13 fcent = MHz.3 dbm Input 1 db Compression Point fcent = MHz 13.8 dbm LO-to-IF Output Leakage Unfiltered IF output 31. dbm LO-to-RF Input Leakage 31. dbm RF-to-IF Output Isolation. dbc IF/ Spurious 9 dbm input power, frf = MHz. dbc IF/3 Spurious 9 dbm input power, frf = MHz 9.8 dbc DYNAMIC PERFORMANCE at frf = 3 MHz 1 Power Conversion Gain 1. db Voltage Conversion Gain. db SSB Noise Figure fcent = 3 MHz, VSET = 3. V 1.8 db Input Third-Order Intercept 7 fcent = 3 MHz, VSET = 3. V. dbm Input Second-Order Intercept 8 fcent = 3 MHz, VSET = 3. V.3 dbm Input 1 db Compression Point 1. dbm LO-to-IF Output Leakage Unfiltered IF output 3. dbm LO-to-RF Input Leakage 9. dbm RF-to-IF Output Isolation 9.7 dbc IF/ Spurious 9 dbm input power, frf = 38 MHz 7.1 dbc IF/3 Spurious 9 dbm input power, frf = 38 MHz 7.8 dbc DYNAMIC PERFORMANCE at frf = MHz 1 Power Conversion Gain 17.8 db Voltage Conversion Gain. db SSB Noise Figure fcent = MHz, VSET = 3. V 1. db Input Third-Order Intercept 7 fcent = MHz, VSET = 3. V.7 dbm Input Second-Order Intercept 8 fcent = MHz, VSET = 3. V 3. dbm Input 1 db Compression Point 11.3 dbm LO-to-IF Output Leakage Unfiltered IF output. dbm LO-to-RF Input Leakage 8.9 dbm RF-to-IF Output Isolation.7 dbc IF/ Spurious 9 dbm input power, frf = 8 MHz dbc IF/3 Spurious 9 dbm input power, frf = 8 MHz 7 dbc DYNAMIC PERFORMANCE at fif = 9 MHz 18 Power Conversion Gain 19 db Voltage Conversion Gain db SSB Noise Figure fif = 9 MHz, frf = MHz, VSET =. V 1. db Output Third-Order Intercept fcent = 13 MHz, VSET = 3. V 3. dbm Output Second-Order Intercept 1 fcent = 13 MHz, VSET = 3. V 8.7 dbm Output 1 db Compression Point 11.1 dbm LO-to-IF Output Leakage Unfiltered IF output 33.8 dbm LO-to-RF Input Leakage 33. dbm IF/ Spurious 9 dbm input power, frf = 1 MHz,. dbc fif = 8 MHz IF/3 Spurious 9 dbm input power, frf = 1 MHz, fif = 8 MHz 8.9 dbc Rev. D Page of

5 ADL81 Parameter Test Conditions Min Typ Max Unit DYNAMIC PERFORMANCE at fif = 1 MHz Power Conversion Gain 3 1. db Voltage Conversion Gain 7. db SSB Noise Figure fif = 1 MHz, frf = 19 MHz, VSET =. V 13. db Output Third-Order Intercept fcent = 17 MHz, VSET = 3. V dbm Output Second-Order Intercept fcent = 17 MHz, VSET = 3. V 7 dbm Output 1 db Compression Point 9.9 dbm LO-to-IF Output Leakage Unfiltered IF output 3.8 dbm LO-to-RF Input Leakage 33. dbm IF/ Spurious 9 dbm input power, frf = 1 MHz, fif = 1 MHz 1. dbc 1 Z is the characteristic impedance assumed for all measurements and the PCB. Supply voltage must be applied from an external circuit through choke inductors 3 VS = V, TA = C, frf = 9 MHz/19 MHz, flo = (frf 13 MHz), LO power = dbm, Z 1 = Ω, VSET = 3.8 V, unless otherwise noted. Excluding :1 IF port transformer (TC-1W+), RF and LO port transformers (TC1-1-13M+), and PCB loss. ZSOURCE = Ω, differential; ZLOAD = Ω differential; ZSOURCE is the impedance of the source instrument; ZLOAD is the load impedance at the output. frf = fcent, fblocker = (fcent ) MHz, flo = (fcent 13) MHz, blocker level = dbm. 7 frf1 = (fcent 1) MHz, frf = (fcent) MHz, flo = (fcent 13) MHz, each RF tone at 1 dbm. 8 frf1 = (fcent ) MHz, frf = (fcent + 1) MHz, flo = (fcent 13) MHz, each RF tone at 1 dbm. 9 For details, see the Spur Performance section. 1 VS = V, TA = C, frf = MHz, flo = (frf 11 MHz), LO power = dbm, Z 1 = Ω, VSET = 3.8 V, unless otherwise noted. 11 Including :1 IF port transformer (TC-1W+), RF and LO port transformers (TC1-1-3M+ and TC1-1-13M+ respectively), and PCB loss. 1 frf1 = (fcent 1) MHz, frf = (fcent) MHz, flo = (fcent 11) MHz, each RF tone at 1 dbm. 13 frf1 = (fcent ) MHz, frf = (fcent + 1) MHz, flo = (fcent 11) MHz, each RF tone at 1 dbm 1 VS = V, TA = C, frf = 3 MHz, flo = (frf 13 MHz), LO power = dbm, Z 1 = Ω, VSET = 3. V, unless otherwise noted. 1 Including :1 IF port transformer (TC-1W+), RF and LO port transformers (3BL1M), and PCB loss. 1 VS = V, TA = C, frf = MHz, flo = (frf 13 MHz), LO power = dbm, Z 1 = Ω, VSET = 3. V, unless otherwise noted. 17 Including :1 IF port transformer (TC-1W+), RF and LO port transformers (BL1B), and PCB loss. 18 VS = V, TA = C, frf = 13 MHz, flo = (frf + 9 MHz), LO power = dbm, Z 1 = Ω, VSET = 3. V, unless otherwise noted. 19 Including :1 IF port transformer (TC-1+), RF and LO transformers (TC1-1-13M+), and PCB loss. frf1 = (fcent 1) MHz, frf = (fcent) MHz, flo = (fcent + 9 MHz), each RF tone at 1 dbm. 1 frf1 = (fcent ) MHz, frf = (fcent + 1) MHz, flo = (fcent + 9) MHz, each RF tone at 1 dbm. VS = V, TA = C, frf = 13MHz, flo = (frf + 1 MHz), LO power = dbm, Z 1 = Ω, VSET = V, unless otherwise noted. 3 Including :1 IF port transformer (18BL1B), RF and LO port transformers (TC1-1-13M+), and PCB loss. frf1 = (fcent 1) MHz, frf = (fcent) MHz, flo = (fcent + 1 MHz), each RF tone at 1 dbm. frf1 = (fcent ) MHz, frf = (fcent + 1) MHz, flo = (fcent + 1) MHz, each RF tone at 1 dbm. Rev. D Page of

6 ADL81 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage,. V VSET, ENBL. V IFOP, IFON. V RFIN Power dbm Internal Power Dissipation 1. W θja (Exposed Paddle Soldered Down) 1. C/W θjc (at Exposed Paddle) 8.7 C/W Maximum Junction Temperature 1 C Operating Temperature Range C to Storage Temperature Range C to +1 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 As measured on the evaluation board. For details, see the Evaluation Board section. Rev. D Page of

7 VPLO ENBL ADL81 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 LOIP 3 LOIN PIN 1 INDICATOR 18 VPRF 17 1 RFIP 1 RFIN 1 13 VPDT DETO 11 VPLO VSET 1 1 IFON 1 NC 3 IFOP 19 ADL81 TOP VIEW (Not to Scale) NOTES 1. THERE IS AN EXPOSED PADDLE THAT MUST BE SOLDERED TO GROUND.. NC = NO CONNECT. Figure. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1,,,, 8, 1, Device Common (DC Ground). 1, 17, 19, 3 3, LOIP, LOIN Differential LO Input Terminal. Internally matched to Ω. Must be ac-coupled. 7, VPLO Positive Supply Voltage for LO System. 9 ENBL Detector and Mixer Bias Enable. Pull the pin high to disable the internal detector and mixer bias circuit. The device can be operated in this mode by setting the bias level using an external supply or connecting a resistor from the VSET pin to the positive supply. See the Circuit Description section for more details. Pull the pin low to enable the internal detector and mixer bias circuit. 1 VSET Input IP3 Bias Adjustment. The voltage presented to the VSET pin sets the internal bias of the mixer core and allows for adaptive control of the input IP3 and NF characteristics of the mixer core. 11 DETO Detector Output. The DETO pin should be loaded with a capacitor to ground. The developed voltage is proportional to the rms input level. When the DETO output voltage is connected to the VSET input pin, the part auto biases and increases input IP3 performance when presented with large signal input levels. 13 VPDT Positive Supply Voltage for Detector. 1, 1 RFIN, RFIP Differential RF Input Terminal. Internally matched to Ω differential input impedance. Must be ac-coupled. 18 VPRF Positive Supply Voltage for RF Input System., 1 IFOP, IFON Differential IF Output Terminal. Bias must be applied through pull-up choke inductors or the center tap of the IF transformer. NC Not Connected. EPAD The exposed paddle must be soldered to ground Rev. D Page 7 of

8 ADL81 TYPICAL PERFORMANCE CHARACTERISTICS DOWNCOVERTER MODE WITH A BROADBAND BALUN VS = V, T A = C, VSET = 3.8 V, IF = 13 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC-1W+) is extracted from the gain measurement. 3 T A = C 3 GAIN (db) T A = T A = GAIN (db) 3 GAIN = 9MHz GAIN = 19MHz INPUT IP3 = 9MHz INPUT IP3 = 19MHz 1 INPUT IP3 (dbm) Figure 3. Power Conversion Gain vs. RF Frequency LO LEVEL (dbm) Figure. Power Conversion Gain and Input IP3 vs. LO Power MEAN = 1.87 SD =.3 GAIN (db) MHz 19MHz FREQUENCY (%) IF FREQUENCY (MHz) POWER CONVERSION GAIN (db) Figure. Power Conversion Gain vs. IF Frequency Figure 7. Power Conversion Gain Distribution 3... GAIN = 9MHz GAIN = 19MHz I POS = 9MHz I POS = 19MHz T A = C T A = GAIN (db) SUPPLY CURRENT (A) GAIN (db) T A = VSET (V) Figure. Power Conversion Gain and Supply Current vs. VSET SUPPLY (V) Figure 8. Power Conversion Gain vs. Supply Voltage Rev. D Page 8 of

9 ADL T A = C T A = INPUT IP3 (dbm) 1 T A = INPUT IP (dbm) 3 T A = C T A = T A = Figure 9. Input IP3 vs. RF Frequency Figure 1. Input IP vs. RF Frequency MHz INPUT IP3 (dbm) 3 9MHz 19MHz INPUT IP (dbm) 3 19MHz IF FREQUENCY (MHz) Figure 1. Input IP3 vs. IF Frequency IF FREQUENCY (MHz) 8 Figure 13. Input IP vs. IF Frequency MHz INPUT IP3 (dbm) NOISE FIGURE (db) INPUT IP (dbm) 3 19MHz INPUT IP3 = 9MHz INPUT IP3 = 19MHz 1 NF = 9MHz NF = 19MHz VSET (V) VSET (V) Figure 11. Input IP3 and Noise Figure vs. VSET Figure 1. Input IP vs. VSET Rev. D Page 9 of

10 ADL T A = T A = INPUT P1dB (dbm) T A = C SSB NOISE FIGURE (db) MHz 9MHz Figure 1. Input P1dB vs. RF Frequency IF FREQUENCY (MHz) 3 Figure 18. SSB Noise Figure vs. IF Frequency (VSET =. V) INPUT P1dB (dbm) MHz 19MHz SSB NOISE FIGURE (db) 1 1 RF = 18MHz, IF = 13 MHz BLOCKER = 181MHz RF = 91MHz, IF = 13 MHz BLOCKER = 9MHz 1 1 IF FREQUENCY (MHz) Figure 1. Input P1dB vs. IF Frequency BLOCKER LEVEL (dbm) Figure 19. SSB Noise Figure vs. Blocker Level (VSET =. V) T A = 18 SSB NOISE FIGURE (db) T A = T A = C SSB NOISE FIGURE (db) MHz 9MHz Figure 17. SSB Noise Figure vs. RF Frequency (VSET =. V) LO LEVEL (dbm) Figure. SSB Noise Figure vs. LO Power (VSET =. V) 879- Rev. D Page 1 of

11 ADL81 RF RETURN LOSS (db) LO-TO-IF LEAKAGE (dbm) T A = C T A = T A = Figure 1. RF Return Loss vs. RF Frequency LO FREQUENCY (MHz) 1 Figure. LO-to-IF Leakage vs. LO Frequency 879- LO RETURN LOSS (db) LO-TO-RF LEAKAGE (dbm) T A = C T A = T A = LO FREQUENCY (MHz) Figure. LO Return Loss vs. LO Frequency LO FREQUENCY (MHz) Figure. LO-to-RF Leakage vs. LO Frequency 879- RESISTANCE (Ω) 3 1 CAPACITANCE (pf) RF-TO-IF OUTPUT ISOLATION (dbc) 1 3 T A = T A = C T A = IF FREQUENCY (MHz) Figure 3. IF Differential Output Impedance (R Parallel C Equivalent) Figure. RF-to-IF Leakage vs. RF Frequency Rev. D Page 11 of

12 ADL81 DOWNCONVERTER MODE WITH A MINI-CIRCUITS TC1-1-3M+ INPUT BALUN VS = V, T A = C, VSET = 3.8 V, IF = 11 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (TC1-1-3M+, TC-1W+) is included in the gain measurement GAIN (db) INPUT IP3 (dbm) 1 1 IIP3 MHz NOISE FIGURE (db) 3 NF MHz Figure 7. Power Conversion Gain vs. RF Frequency V SET (V) Figure 3. Input IP3 and Noise Figure vs. VSET GAIN M.1.1 GAIN (db) IPOS M SUPPLY CURRENT (A) INPUT IP (dbm) V SET (V) 3 Figure 8. Power Conversion Gain and IPOS vs. VSET Figure 31. Input IP vs. RF Frequency INPUT IP3 (dbm) 8 7 INPUT IP (dbm) V SET (V) Figure 9. Input IP3 vs. RF Frequency Figure 3. Input IP vs. VSET Rev. D Page 1 of

13 ADL81 INPUT P1dB (dbm) Figure 33. Input P1dB vs. RF Frequency LO TO RF LEAKAGE (dbm) LO FREQUENCY (MHz) Figure 3. LO to RF Leakage vs. LO Frequency NOISE FIGURE (db) 1 1 V SET 3.V V SET 3.V C V SET 3.V V SET V V SET V C V SET V RF TO IF OUTPUT ISOLATION (dbc) Figure 3. Noise Figure vs. RF Frequency Figure 37. RF to IF Output Isolation vs. RF Frequency LO TO IF LEAKAGE (dbm) LO FREQUENCY (MHz) Figure 3. LO to IF Leakage vs. LO Frequency Rev. D Page 13 of

14 ADL81 DOWNCONVERTER MODE WITH A JOHANSON 3. GHZ INPUT BALUN VS = V, T A = C, VSET = 3. V, IF = 13 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (3BL1M, TC-1W+) is included in the gain measurement. 3 8 GAIN (db) C Figure 38. Power Conversion Gain vs. RF Frequency INPUT IP3 (dbm) 1 1 IIP3, C IIP3, IIP3, NF, C NF, NF, V SET (V) Figure 1. Input IP3 and Noise Figure vs. VSET NOISE FIGURE (db) GAIN (db) 8 1 GAIN C GAIN GAIN IPOS C IPOS IPOS SUPPLY CURRENT (A) INPUT IP (dbm) 3 3 C V SET (V) Figure 39. Power Conversion Gain and IPOS vs. VSET Figure. Input IP vs. RF Frequency C 7 C INPUT IP3 (dbm) 1 1 INPUT IP (dbm) Figure. Input IP3 vs. RF Frequency V SET (V) Figure 3. Input IP vs. VSET Rev. D Page 1 of

15 ADL C 1 1 C INPUT P1dB (dbm) LO TO RF LEAKAGE (dbm) Figure. Input P1dB vs. RF Frequency LO FREQUENCY (MHz) Figure 7. LO to RF Leakage vs. LO Frequency 879-7, 3.V, 3.V C, 3.V NOISE FIGURE (db) 1 1,.V,.V C,.V RF TO IF OUTPUT ISOLATION (dbc) 3 7 C Figure. Noise Figure vs. RF Frequency Figure 8. RF to IF Output Isolation vs. RF Frequency LO TO IF LEAKAGE (dbm) C LO FREQUENCY (MHz) Figure. LO to IF Leakage vs. LO Frequency 879- Rev. D Page 1 of

16 ADL81 DOWNCONVERTER MODE WITH A JOHANSON.7 GHZ INPUT BALUN VS = V, T A = C, VSET = 3. V, IF = 13 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (BL1B, TC-1W+) is included in the gain measurement. 3 C 3 GAIN (db) INPUT IP3 (dbm) 1 1 IIP3, C IIP3, IIP3, 1 NF, C NF, NF, V SET (V) 1 NOISE FIGURE (db) 879- Figure 9. Power Conversion Gain vs. RF Frequency Figure. Input IP3 and Noise Figure vs. VSET. 7 GAIN (db) GAIN C GAIN GAIN IPOS C IPOS IPOS V SET (V) Figure. Power Conversion Gain and IPOS vs VSET SUPPLY CURRENT (A) 879- INPUT IP (dbm) 3 3 C Figure 3. Input IP vs. RF Frequency C 8 7 C INPUT IP3 (dbm) 1 1 INPUT IP (dbm) V SET (V) 879- Figure 1. Input IP3 vs. RF Frequency Figure. Input IP vs. VSET Rev. D Page 1 of

17 ADL C 1 1 C INPUT P1dB (dbm) LO TO RF LEAKAGE (dbm) Figure. Input P1dB vs. RF Frequency LO FREQUENCY (MHz) Figure 8. LO to RF Leakage vs. LO Frequency NOISE FIGURE (db) 1 1, 3.V,.V, 3.V,.V C, 3.V C,.V RF TO IF OUTPUT ISOLATION (dbc) 3 7 C Figure. Noise Figure vs. RF Frequency, VSET = 3. V Figure 9. RF to IF Output Isolation vs. RF Frequency LO TO IF LEAKAGE (dbm) C LO FREQUENCY (MHz) Figure 7. LO to IF Leakage vs. LO Frequency Rev. D Page 17 of

18 ADL81 UPCONVERTER MODE WITH A 9 MHZ OUTPUT MATCH VS = V, T A = C, VSET = 3. V, RF = 13 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC-1) is included in the gain measurement. 3 1 C 3 GAIN (db) OUTPUT IP3 (dbm) 1 1 OUTPUT IP3, C OUTPUT IP3, OUTPUT IP3, IF FREQUENCY (MHz) Figure. Power Conversion Gain vs. IF Frequency V SET (V) Figure 3. Output IP3 vs. VSET GAIN (db) GAIN C GAIN GAIN IPOS C IPOS IPOS SUPPLY CURRENT (A) OUTPUT IP (dbm) 7 7 C V SET (V) 3 3 Figure 1. Power Conversion Gain and IPOS vs. VSET IF FREQUENCY (MHz) 8 7 Figure. Output IP vs. IF Frequency OUTPUT IP3 (dbm) 1 1 C OUTPUT IP (dbm) 7 C IF FREQUENCY (MHz) Figure. Output IP3 vs. IF Frequency V SET (V) Figure. Output IP vs. VSET Rev. D Page 18 of

19 ADL OUTPUT P1dB (dbm) 1 8 C LO TO IF LEAKAGE (dbm) 3 3 C IF FREQUENCY (MHz) 1 Figure. Output P1dB vs. IF Frequency LO FREQUENCY (MHz) 1 Figure 8. LO to IF Leakage vs. LO Frequency NOISE FIGURE (db) NF V SET = 3.V, C NF V SET = 3.V, NF V SET = 3.V, NF V SET =.V, C NF V SET =.V, NF V SET =.V, LO TO RF LEAKAGE (dbm) C IF FREQUENCY (MHz) Figure 7. Noise Figure vs. IF Frequency, FLO = MHz LO FREQUENCY (MHz) Figure 9. LO to RF Leakage vs. LO Frequency Rev. D Page 19 of

20 ADL81 UPCONVERTER MODE WITH A.1 GHZ OUTPUT MATCH VS = V, T A = C, VSET = V, RF = 17 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, 18BL1B) is included in the gain measurement GAIN (db) C OUTPUT IP3 (dbm) 1 1 C Figure 7. Power Conversion Gain vs. RF Frequency Figure 73. Output IP3 vs. RF Frequency C GAIN (db) GAIN C GAIN GAIN IPOS C IPOS IPOS SUPPLY CURRENT (A) OUTPUT IP (dbm) V SET (V) Figure 71. Power Conversion Gain and IPOS vs. VSET IF FREQUENCY (MHz) Figure 7. Output IP vs. IF Frequency C OUTPUT IP3 (dbm) 1 1 OUTPUT IP (dbm) 7 OUTPUT IP3 C OUTPUT IP3 OUTPUT IP V SET (V) Figure 7. Output IP3 vs. VSET V SET (V) Figure 7. Output IP vs. VSET Rev. D Page of

21 ADL OUTPUT P1DB (dbm) 1 8 C LO TO RF LEAKAGE (dbm) 3 3 C IF FREQUENCY (MHz) Figure 7. Output P1dB vs. IF Frequency LO FREQUENCY (MHz) Figure 79. LO to RF Leakage vs. LO Frequency NOISE FIGURE (db) 1 1 NF V SET = 3.V, C NF V SET = 3.V, NF V SET = 3.V, NF V SET =.V, C NF V SET =.V, NF V SET =.V, RF TO IF OUTPUT ISOLATION (dbc) C IF FREQUENCY (MHz) Figure 77. Noise Figure vs. IF Frequency, FLO = 19 MHz Figure 8. RF to IF Output Isolation vs. RF Frequency C LO TO IF LEAKAGE (dbm) 3 3 C GAIN (db) LO FREQUENCY (MHz) Figure 78. LO to IF Leakage vs. LO Frequency IF FREQUENCY (MHz) Figure 81. Power Conversion Gain vs. IF Frequency Rev. D Page 1 of

22 ADL GAIN (db) GAIN C GAIN GAIN OUTPUT IP3 C OUTPUT IP3 OUTPUT IP OUTPUT IP3 (dbm) OUTPUT IP (dbm) C LO POWER (dbm) Figure 8. Power Conversion Gain and Output IP3 vs. LO Power Figure 8. Output IP vs. RF Frequency GAIN (db) C OUTPUT P1dB (dbm) C SUPPLY (V) Figure 83. Power Conversion Gain vs. Supply Figure 8. Output P1dB vs. RF Frequency C OUTPUT IP3 (dbm) IF FREQUENCY (MHz) Figure 8. Output IP3 vs. IF Frequency 879- Rev. D Page of

23 ADL81 SPUR PERFORMANCE All spur tables are (N frf) (M flo) and were measured using the standard evaluation board (see the Evaluation Board section). Mixer spurious products are measured in decibels relative to the carrier (dbc) from the IF output power level. Data was measured for frequencies less than GHz only. The typical noise floor of the measurement system is 1 dbm. 9 MHz Downconvert Performance VS = V, VSET = 3.8 V, TA = C, RF power = dbm, LO power = dbm, frf = 9 MHz, flo = 73 MHz, Z = Ω. M N MHz Downconvert Performance VS = V, VSET = 3.8 V, TA = C, RF power = dbm, LO power = dbm, frf = 19 MHz, flo = 173 MHz, Z = Ω N M Rev. D Page 3 of

24 ADL81 MHz Downconvert Performance VS = V, VSET = 3.8 V, TA = C, RF power = dbm, LO power = dbm, frf = MHz, flo = 3 MHz, Z = Ω. N < <1 7 <1 91. <1 <1 <1 8 <1 9. < <1 9 < <1 98. <1 1 <1 93. < <1 11 <1 <1 <1 <1 <1 1 <1 <1 <1 <1 <1 13 <1 <1 <1 <1 1 <1 <1 <1 1 <1 M 38 MHz Downconvert Performance VS = V, VSET = 3.8 V, TA = C, RF power = dbm, LO power = dbm, frf = 38 MHz, flo = 3 MHz, Z = Ω. N < <1 < <1 7 < <1 <1 8 <1 8. <1 <1 9 <1 <1 <1 1 <1 9.9 <1 11 <1 <1 <1 1 <1 <1 <1 13 <1 <1 <1 1 <1 <1 1 <1 M Rev. D Page of

25 ADL81 8 MHz Downconvert Performance VS = V, VSET = 3.8 V, TA = C, RF power = dbm, LO power = dbm, frf = 8 MHz, flo = MHz, Z = Ω. N <1 9 <1 <1 1 <1 <1 11 <1 <1 1 <1 < < <1 M 8 MHz Upconvert Performance VS = V, VSET = 3.8 V, TA = C, RF power = dbm, LO power = dbm, frf = 1 MHz, flo = 9 MHz, Z = Ω. N < <1 < < <1 <1 8.1 < <1 < <1 <1 8. <1 88. <1 < < <1 < < <1 <1 1. <1 <1 < <1 < <1 9.9 <1 <1 <1 < <1 < <1 <1 <1 < <1 < <1 < < <1 <1 <1 < <1 9. v <1 <1 M Rev. D Page of

26 ADL81 1 MHz Upconvert Performance VS = V, VSET =. V, TA = C, RF power = dbm, LO power = dbm, frf = 1 MHz, flo = 3 MHz, Z = Ω. N < < < <1 1. <1 97. < <1 1.8 < < <1 <1 <1 1. <1 91. < <1 <1 9. M Rev. D Page of

27 CIRCUIT DESCRIPTION The ADL81 includes a double-balanced active mixer with a Ω input impedance and Ω output impedance. In addition, the ADL81 integrates a local oscillator (LO) amplifier and an RF power detector that can be used to optimize the mixer dynamic range. The RF and LO are differential, providing maximum usable bandwidth at the input and output ports. The LO also operates with a Ω input impedance and can, optionally, be operated differentially or single ended. The input, output, and LO ports can be operated over an exceptionally wide frequency range. The ADL81 can be configured as a downconvert mixer or as an upconvert mixer. The ADL81 can be divided into the following sections: the LO amplifier and splitter, the RF voltage-to-current (V-to-I) converter, the mixer core, the output loads, the RF detector, and the bias circuit. A simplified block diagram of the device is shown in Figure 87. The LO block generates a pair of differential LO signals to drive two mixer cores. The RF input power is converted into RF currents by the V-to-I converter that then feed into the two-mixer core. The internal differential load of the mixer provides a wideband Ω output impedance from the mixer. Reference currents to each section are generated by the bias circuit, which can be enabled or disabled using the ENBL pin. A detailed description of each section of the ADL81 follows. LOIP LOIN 1 3 VPLO NC IFON IFOP ADL81 DET VI VPLO ENBL VSET DETO Figure 87. Block Diagram 18 VPRF 17 1 RFIP 1 RFIN 1 13 VPDT LO AMPLIFIER AND SPLITTER The LO input is conditioned by a series of amplifiers to provide a well controlled and limited LO swing to the mixer core, resulting in excellent input IP3. The LO input is amplified using a broadband low noise amplifier (LNA) and is then followed by LO limiting amplifiers. The LNA input impedance is nominally Ω. The LO circuit exhibits low additive noise, resulting in an excellent mixer noise figure and output noise under RF blocking. For optimal performance, the LO inputs should be driven differentially but at lower frequencies; single-ended drive is acceptable ADL81 RF VOLTAGE-TO-CURRENT (V-TO-I) CONVERTER The differential RF input signal is applied to a V-to-I converter that converts the differential input voltage to output currents. The V-to-I converter provides a Ω input impedance. The V-to- I section bias current can be adjusted up or down using the VSET pin. Adjusting the current up improves IP3 and P1dB input but degrades the SSB noise figure. Adjusting the current down improves the SSB noise figure but degrades IP3 and P1dB input. Conversion gain remains nearly constant over a wide range of VSET pin settings, allowing the part to be adjusted dynamically without affecting conversion gain. Internally, the VSET pin features a series resistance and diode to ground; hence a simple voltage divider driving the pin is not sufficient. Current adjustment can be made by connecting a resistor from the VSET pin to the positive supply, however. Table lists some typical values for this resistor and the resulting VSET value and supply current. Use Table to select the appropriate value of R1 (see Figure 1) to achieve the desired mixer bias level. In this mode of operation, R7 and R9 should remain open. Table. Suggested Values of R1 to Achieve the Desired Mixer Bias Level R1 (Ω) VSET (V) IPOS (ma) Open IPOS is the mixer supply current. Rev. D Page 7 of

28 ADL81 Optionally, the VSET pin can be connected to the DETO pin to provide automatic setting of the mixer core current. MIXER CORE The ADL81 has a double-balanced mixer that uses high performance SiGe NPN transistors. This mixer is based on the Gilbert cell design of four cross-connected transistors. MIXER OUTPUT LOAD The mixer load uses a pair of 1 Ω resistors connected to the positive supply. This provides a Ω differential output resistance. The mixer output should be pulled to the positive supply externally using a pair of RF chokes or using an output transformer with the center tap connected to the positive supply. It is possible to exclude these components when the mixer core current is low, but both P1dB input and IP3 input are then reduced. The mixer load output can operate from direct current (dc) up to approximately MHz into a Ω load. For upconversion applications, the mixer load can be matched using off-chip matching components. Transmit operation up to 3 GHz is possible. See the Applications Information section for matching circuit details. RF DETECTOR An RF power detector is buffered from the V-to-I converter section. This detector has a power response range from approximately dbm up to dbm and provides a current output. The output current is designed to be connected to the VSET pin to boost the mixer core current when large RF signals are present at the mixer input. An external capacitor can be used to adjust the response time of this function. If not used, the DETO pin can be left open or connected to ground. The detector was characterized under the conditions specified in the Downcoverter Mode with a Broadband Balun section. Pin 11 (DETO) was connected to Pin 1 (VSET), and the voltage on these pins was plotted vs. the RF input power level over temperature and a number of devices. DETECTOR OUTPUT VOLTAGE (V) C The input IP3, gain and supply current were also recorded under these conditions. The result can be seen in Figure 89 through Figure 91. INPUT IP3 (dbm) GAIN (db) SUPPLY CURRENT (ma) C RF INPUT (dbm) Figure 89. Input IP3 vs. RF Input C RF INPUT (dbm) Figure 9. Power Conversion Gain vs. RF Input C RF INPUT (dbm) Figure 91. Supply Current vs. RF Input RF INPUT (dbm) Figure 88. Detector Output Voltage vs. RF Input Rev. D Page 8 of

29 BIAS CIRCUIT A band gap reference circuit generates the reference currents used by mixers. The bias circuit can be enabled and disabled using the ENBL pin. If the ENBL pin is grounded or left open, the part is enabled. Pulling the ENBL pin high shuts off the bias circuit and disables the part. However, the ENBL pin does not ADL81 alter the current in the LO section and, therefore, does not provide a true power-down feature. In addition, if the VSET pin is connected to the positive supply through a resistor to increase the mixer core current, this continues to provide bias current to the mixer core unless the resistor supply is also removed. Rev. D Page 9 of

30 ADL81 APPLICATIONS INFORMATION BASIC CONNECTIONS The ADL81 is designed to translate between radio frequencies (RF) and intermediate frequencies (IF). For both upconversion and downconversion applications, RFIP (Pin 1) and RFIN (Pin 1) must be configured as the input interfaces. IFOP (Pin ) and IFON (Pin 1) must be configured as the output interfaces. Individual bypass capacitors are needed in close proximity to each supply pin (Pin 7, Pin 13, Pin 18, and Pin ), the VSET control pin (Pin 1), and the DETO detector output pin (Pin 11). When the on-chip detector is chosen to form a closed loop, automatically controlling the VSET pin, R7 can be populated with a Ω resistor. Alternatively, simply use a jumper between the VSET and DETO test points for evaluation. Figure 9 illustrates the basic connections for ADL81 operation. RF AND LO PORTS The RF and LO input ports are designed for a differential input impedance of approximately Ω. Figure 93 and Figure 9 illustrate the RF and LO interfaces, respectively. It is recommended that each of the RF and LO differential ports be driven through a balun for optimum performance. It is also necessary to ac couple both RF and LO ports. Using proper value capacitors may help improve the input return loss over desired frequencies. Table and Table 8 list the recommended components for various RF and LO frequency bands in upconvert and downconvert modes. The characterization data is available in the Typical Performance Characteristics section. IFOP IFON R11 T1 T T8 R13 C R R3 R C C L1 L3 L C19 C3 C VPLO NC IFON IFOP C1 1 VPRF 18 LOIN LOIP R1 R1 T T T7 C C 3 LOIP LOIN ADL81 RFIP RFIN C8 C9 L L T3 T T9 R8 R1 R RFIP RFIN VPDT 13 VPLO ENBL VSET DETO R1 C C7 ENBL DETO R7 C18 C17 R9 VSET C1 C Figure 9. Basic Connections Schematic Rev. D Page 3 of

31 ADL81 ADL81 LOIP 17 C8 RFIP 1 RFIN 1 C9 T3 1 Figure 93. RF Interface 1 C 3 LOIP LOIN T C RFIP ADL81 shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the IF frequency of operation not to load down the output current before it reaches the intended load. Additionally, the dc current handling capability of the selected choke inductors must be at least ma. The self-resonant frequency of the selected choke inductors must be higher than the intended IF frequency. A variety of suitable choke inductors is commercially available from manufacturers such as Coilcraft and Murata. An impedance transforming network may be required to transform the final load impedance to Ω at the IF outputs. Table 7 lists suggested components for the IF port in the upconvert and downconvert modes. IFOP T1 T T C R3 L3 R Figure 9. LO Interface C13 Table. Suggested Components for the RF and LO Interfaces in Downconvert Mode RF and LO Frequency T, T3 C8, C9 C, C 1 MHz Mini-Circuits TC1-1-13M+ 1 nf 1 nf 9 MHz Mini-Circuits TC1-1-13M+. pf 1 pf 19 MHz Mini-Circuits TC1-1-13M+. pf 1 pf MHz Mini-Circuits TC1-1-3M+ pf 8 pf 3 MHz 3BL1M 1. pf 1. pf MHz BL1B 3 pf 3 pf 1 MHz to MHz Mini-Circuits TCM1-3AX+ 1 nf 1 nf Table. Suggested Components for the RF Interface in Upconvert Mode RF Frequency T3 C8, C9 13 MHz TC1-1-13M+ 7 pf IF PORT The IF port features an open-collector, differential output interface. It is necessary to bias the open collector outputs using one of the schemes presented in Figure 9 and Figure 9. Figure 9 shows the use of center-tapped impedance transformers. The turns ratio of the transformer should be selected to provide the desired impedance transformation. In the case of a Ω load impedance, a :1 impedance ratio transformer should be used to transform the Ω load into a Ω differential load at the IF output pins. Figure 9 shows a differential IF interface where pull-up choke inductors are used to bias the open-collector outputs. The NC IFON IFOP ADL81 Figure 9. Biasing the IF Port Open-Collector Outputs Using a Center-Tapped Impedance Transformer C L1 C3 Z L IMPEDANCE TRANSFORMING NETWORK L3 C13 C L T1 T T NC IFON IFOP ADL81 C Figure 9. Biasing the IF Port Open-Collector Outputs Using Pull-Up Choke Inductors Table 7. Suggested Components for the IF Port in Upconvert and Downconvert Modes Mode of IF Frequency Operation T1 L3 MHz to MHz Downconvert TC-1W+ Open 9 MHz Upconvert TC-1+ 7 nh 1 MHz Upconvert 18BL1B 3.3 nh Rev. D Page 31 of

32 ADL81 DOWNCONVERTING TO LOW FREQUENCIES For downconversion to lower frequencies, the device should be biased at the output with a resistor. The common-mode voltage at the IF output of the device should be 3.7 V to ensure optimal performance. Figure 97 provides a sample setup to downconvert a 9 MHz input signal down to 1 khz. In the setup depicted in Figure 97, the output of the device is biased with Ω resistors. In this mode of operation, the device exhibits. db of conversion gain when a signal at MHz was downcoverted to a 1 khz, 1 khz or 1 khz. C.1µF 1µF 1µF NC Z L IMPEDANCE TRANSFORMING NETWORK Ω T1 T T8 IFON IFOP ADL81 Ω C19.1µF Figure 97. Resistive Bias Network to Downconvert Signals to Low Frequencies Rev. D Page 3 of

33 ADL81 BROADBAND OPERATION The ADL81 can support input frequencies from 1 MHz to GHz. The device can be operated with a broadband balun such as the MiniCircuits TCM1-3AX+ for applications that need wideband frequency coverage. Figure 98 illustrates a sample setup configuration with the MiniCircuits TCM1-3AX+ balun populated on the RF and LO ports. This single setup solution provides the option to utilize the complete input frequency range of the device. IFOP IFON R Ω C.1µF Mini-Circuits TC-1W+ C.1µF C3 1pF C 1pF VPLO NC IFON IFOP C1.1µF 1 VPRF 18 LOIN LOIP Mini-Circuits C TCM1-3AX+ 1nF R1 Ω C 1nF 3 LOIP LOIN ADL81 RFIP RFIN C8 1nF C9 1nF Mini-Circuits TCM1-3AX+ R8 Ω RFIP RFIN VPDT VPLO ENBL VSET DETO R1 C11.1µF C.1µF C7 1pF ENBL C18.1µF C17 1pF VSET DETO R9 C1.1µF C1 1pF Figure 98. Sample Setup Configuration with the MiniCircuits TCM1-3AX+ Broadband Balun Rev. D Page 33 of

34 ADL81 Figure 99 to Figure 11 demonstrate the performance of the mixer with the MiniCircuits TCM1-3AX+ populated on the RF and LO ports. GAIN, IIP3, IIP (db, dbm) CONVERSION GAIN (db) IIP3 (dbm) IIP (dbm) f IF = 13MHz, f LO : 13MHz TO 13MHz (HIGH SIDE LO) P RF = 1dBm, P LO = dbm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP: 1MHz TONE SPACING BETWEEN CHANNELS Figure 99. Gain, IIP3, IIP vs. RF Frequency INPUT RETURN LOSS (db) Figure 11. Input Return Loss vs. RF Frequency The device maintains an Input IP3 of dbm or better and conversion gain of db or better across the 1 MHz to GHz frequency band V SET =.V V SET = 3.V NOISE FIGURE (db) f IF = 13MHz, f LO : 13MHz TO 13MHz (HIGH SIDE LO) P RF = 1dBm, P LO = dbm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP: 1MHz TONE SPACING BETWEEN CHANNELS 1 3 Figure 1. Noise Figure vs. RF Frequency Rev. D Page 3 of

35 ADL81 SINGLE-ENDED DRIVE OF RF AND LO INPUTS The RF and LO ports of the active mixer can be driven single-ended without baluns for single-ended operation. In this configuration, the unused RF and LO ports should be ac grounded using a 1 nf capacitor. Figure 1 depicts setup configuration suggested to operate the device in the single-ended mode. IFOP IFON C.1µF Mini-Circuits TC-1W+ R Ω C.1µF C3 1pF C 1pF VPLO NC IFON IFOP C1.1µF 1 VPRF 18 LOIN R1 Ω C 1nF 3 LOIP ADL81 RFIP 17 1 C8 1nF RFIP LOIP C 1nF LOIN RFIN 1 1 C9 1nF R1 Ω RFIN VPDT VPLO ENBL VSET DETO R1 C11.1µF C.1µF C7 1pF ENBL C18.1µF C17 1pF VSET DETO R9 C1.1µF C1 1pF Figure 1. Single-Ended Configuration to Operate the ADL81 Rev. D Page 3 of

36 ADL81 Figure 13 to Figure 1 demonstrate the performance of the mixer in the single ended mode. GAIN, IIP3, IIP (db, dbm) CONVERSION GAIN (db) IIP3 (dbm) IIP (dbm) f IF = 13MHz, f LO : 13MHz TO 13MHz (HIGH SIDE LO) P RF = 1dBm, P LO = dbm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP: 1MHz TONE SPACING BETWEEN CHANNELS Figure 13. Gain, IIP3, IIP vs. RF Frequency INPUT RETURN LOSS (db) 1 1 f IF = 13MHz f LO : 13MHz TO 13MHz (HIGH SIDE LO) 3 P RF = 1dBm, P LO = dbm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP: 1MHz TONE SPACING BETWEEN CHANNELS Figure 1. Input Return Loss vs. RF Frequency V SET =.V V SET = 3.V 1 NOISE FIGURE (db) 1 f IF = 13MHz, f LO : 13MHz TO 13MHz (HIGH SIDE LO) P RF = 1dBm, P LO = dbm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP: 1MHz TONE SPACING BETWEEN CHANNELS 1 3 Figure 1. Noise Figure vs. RF Frequency Rev. D Page 3 of

37 ADL81 EVALUATION BOARD An evaluation board is available for the ADL81. The standard evaluation board is fabricated using Rogers RO33 material. Each RF, LO, and IF port is configured for single-ended signaling via a balun transformer. The schematic for the evaluation board is shown in Figure 1. Table 8 describes the various configuration options for the evaluation board. Layout for the board is shown in Figure 17 and Figure 18. IFOP IFON R11 T1 T T8 R13 C R R3 R C C L1 L3 L C19 C3 C VPLO NC IFON IFOP C1 1 VPRF 18 LOIN R1 C 3 LOIP ADL81 RFIP 17 1 C8 L R8 RFIP LOIP R1 T T T7 C LOIN RFIN 1 1 C9 L T3 T T9 R1 RFIN VPLO VPDT ENBL VSET DETO 13 C R1 C C7 ENBL DETO R7 C18 C17 R9 VSET C1 C Figure 1. Evaluation Board Schematic Rev. D Page 37 of

38 ADL81 Table 8. Evaluation Board Configuration Components Function Default Conditions C, C3, C, C7, C1, C11 Power supply decoupling. Nominal supply decoupling consists of a.1 µf capacitor to ground in parallel with 1 pf capacitors to ground, positioned as close to the device as possible. Series resistors are provided for enhanced supply decoupling using optional ferrite chip inductors. C8, C9, L, L, R, R8, R1, T3, T, T9, RFIN, RFIP C13, C19, C, C, L1, L, L3, R, R3, R11, R13, R, T1, T, T8, IFON, IFOP C, C, R1, R1, T, T, T7, LOIN, LOIP RF input interfaces. (Use RFIN for operation). Input channels are ac-coupled through C8 and C9. R8 and R1 provide options when additional matching is needed. T3 is a 1:1 balun used to interface to the Ω differential inputs. T and T9 provide options when high frequency baluns are used and require smaller balun footprints. IF output interfaces. The Ω open collector IF output interfaces are biased through the center tap of a :1 impedance transformer at T1. C provides local bypassing with R available for additional supply bypassing. L1 and L provide options when pull-up choke inductors are used to bias the open-collector outputs. C13, L3, R, and R3 are provided for IF filtering and matching options. T and T8 provide options when high frequency baluns are used and require smaller balun footprints. LO interface. (Use LOIN for operation). C and C provide ac coupling for the local oscillator input. T is a 1:1 balun that allows single-ended interfacing to the differential Ω local oscillator input. T and T7 provide options when high frequency baluns are used and require smaller balun footprints. C1, C1, R7, DETO DETO interface. C1 and C1 provide decoupling for the DETO pin. R7 provides access to the VSET pin when automatic input IP3 control is needed. C17, C18, R9, R1, VSET VSET bias control. C17 and C18 provide decoupling for the VSET pin. R9 and R1 form an optional resistor divider network between and, allowing for a fixed bias setting. Supply 3.8 V at the VSET pin when the DETO pin is not connected for automatic input IP3 control. C, C, C1, C11 =.1 µf (size ) C3, C7 = 1 pf (size ) C8, C9 = 1 nf (size ) L, L = Ω (size ) R1 = open (size ) R, R8 = Ω (size ) T3 = TCM1-3AX+ (Mini-Circuits) C13 = open (size ) C19, C = 1 pf (size ) C =.1 µf (size ) L1, L = open (size 8) L3 = open (size ) R, R3, R13, R = Ω (size ) R11 = open (size ) T1 = TC-1W+ (Mini-Circuits) C, C = 1 nf (size ) R1 = open (size ) R1 = Ω (size ) T = TCM1-3AX+ C1 =.1 µf (size 3) C1 = 1 pf (size ) R7 = open (size ) C17 = 1 pf (size ) C18 =.1 µf (size 3) R9, R1 = open (size ) Figure 17. Evaluation Board Top Layer Figure 18. Evaluation Board Bottom Layer Rev. D Page 38 of

39 ADL81 OUTLINE DIMENSIONS PIN 1 INDICATOR.1. SQ BSC SQ. MAX. BSC. MAX. REF EXPOSED PAD 1 PIN 1 INDICATOR.. SQ.3 ORDERING GUIDE SEATING PLANE TOP VIEW 1 MAX.8 MAX. TYP MAX. NOM COPLANARITY.8. REF 13 1 COMPLIANT TOJEDEC STANDARDS MO--VGGD-8 7 BOTTOM VIEW. MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 19. -Lead Lead Frame Chip Scale Package [LFCSP_VQ] mm mm Body, Very Thin Quad (CP--3) Dimensions shown in millimeters Model 1 Temperature Range Package Description A Package Option Ordering Quantity ADL81ACPZ-R7 C to -Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP--3 1, per Reel ADL81-EVALZ Evaluation Board 1 1 Z = RoHS Compliant Part. Rev. D Page 39 of

40 ADL81 NOTES 1 1 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D879--3/1(D) Rev. D Page of