GaAs, phemt, MMIC, Low Noise Amplifier, 0.3 GHz to 20 GHz HMC1049LP5E

Transcription

1 ACG ACG ACG FEATURES Low noise figure:. db PdB output power:. dbm PSAT output power: 7. dbm High gain: db Output IP: 9 dbm Supply voltage: VDD = 7 V at 7 ma Ω matched input/output (I/O) -lead, mm mm LFCSP package: mm APPLICATIONS Test instrumentation High linearity microwave radios VSAT and SATCOM Military and space GENERAL DESCRIPTION The is a GaAs MMIC low noise amplifier (LNA) that operates between. GHz and GHz. This LNA provides db of small signal gain,. db noise figure, and an IP output of 9 dbm, yet requires only 7 ma from a 7 V supply. The PdB output power of. dbm enables the LNA to function as a local oscillator (LO) driver for balanced, I/Q, or GaAs, phemt, MMIC, Low Noise Amplifier,. GHz to GHz V DD GND RFIN FUTIONAL BLOCK DIAGRAM V GG Figure. GND RFOUT/V DD 9 7 image rejection mixers. VDD can also be applied to Pin, although Pin requires a bias tee with VDD = V. The amplifier I/Os are internally matched to Ω, and the device is supplied in a compact, leadless mm mm LFCSP package. 79- Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... Interface Schematics... Typical Performance Characteristics...7 Evaluation Printed Circuit Board... Packaging and Ordering Information... Outline Dimensions... Ordering Guide... REVISION HISTORY / Rev. A to Rev. B Changed HMC9 to... Throughout Changes to Features Section and General Description Section. Change to Figure 7 Caption and Figure Caption... Updated Outline Dimensions... Changes to Ordering Guide... / Rev.. to Rev. A This Hittite Microwave Products data sheet has been reformatted to meet the styles and standards of Analog Devices, Inc. Updated Format... Universal Changes to General Description... Change to Table, Thermal Resistance Parameter Column... Added Figure... Changes to Table... Moved Figure to Figure 9 to Interface Schematics Section... Change to Figure and Figure 9... Changes to Figure... Added Ordering Guide Section... Rev. B Page of

3 SPECIFICATIONS TA = C, VDD = 7 V, IDD = 7 ma. Table. Parameter Min Typ Max Min Typ Max Min Typ Max Unit FREQUEY RANGE. GHz GAIN.. db Gain Variation Over Temperature..9.7 db/ C NOISE FIGURE db RETURN LOSS Input db Output db OUTPUT Output Power for db Compression (PdB). dbm Saturated (PSAT) 7. dbm Output Third-Order Intercept (IP) 9 dbm TOTAL SUPPLY CURRENT ma Adjust VGG between V to V to achieve IDD = 7 ma typical. Measurement taken at POUT/tone = dbm. Rev. B Page of

4 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Drain Bias Voltage (VDD) V Drain Bias Voltage (RF Out/VDD) 7 V RF Input Power dbm Gate Bias Voltage, VGG V to +. V Channel Temperature 7 C Continuous PDISS (T = C). W (Derate 7. mw/ C Above C) Thermal Resistance (Channel to Ground.9 C/W Paddle) Temperature Storage Temperature C to + C Operating Temperature C to + C ESD Sensitivity (HBM) Class A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table. Typical Supply Current vs. VDD VDD (V) IDD (ma) Adjust VGG to achieve IDD = 7 ma. ESD CAUTION Rev. B Page of

5 PIN CONFIGURATION AND FUTION DESCRIPTIONS GND RFIN V GG ACG ACG ACG V DD 7 GND RFOUT/V DD TOP VIEW (Not to Scale) NOTES. = NO CONNECT. THESE PINS ARE NOT CONNECTED INTERNALLY; HOWEVER, ALL DATA WAS MEASURED WITH THESE PINS CONNECTED TO RF/DC GROUND EXTERNALLY.. EXPOSED PAD. THE EXPOSED GROUND PADDLE MUST BE CONNECTED TO RF/DC GROUND. Figure. Pin Configuration Diagram 79- Table. Pin Function Descriptions Pin No. Mnemonic Description,, to,, 7 to, to 9,, No Connect. These pins are not connected internally; however, all data was measured with these pins connected to RF/dc ground externally (see the Typical Performance Characteristics section for data plots). RFIN RF Input. This pin is dc-coupled and matched to Ω. VDD Power Supply Voltage for the Amplifier. External bypass capacitors ( pf and. μf) are required. ACG Low Frequency Termination. An external bypass capacitor of pf is required. RFOUT/VDD RF Output/Alternate Power Supply Voltage for the Amplifier. An external bias tee is required when used as alternative VDD. This pin is dc-coupled and matched to Ω., ACG, Low Frequency Termination. External bypass capacitors of pf are required. ACG VGG Gate Control for Amplifier. Adjust the voltage to achieve IDD = 7 ma. External bypass capacitors of pf,. μf, and.7μf are required., GND Ground. Connect Pin and Pin to RF/dc ground. EP Exposed Pad. The exposed ground paddle must be connected to RF/dc ground. See the Interface Schematics section for pin interfaces. Rev. B Page of

6 INTERFACE SCHEMATICS V DD RFIN ACG 79- Figure. VDD Interface ACG Figure 7. ACG and ACG Interface 79-9 GND RFOUT/V DD Figure. RFOUT/VDD Interface Figure. GND Interface ACG RFOUT/V DD RFIN ACG Figure 9. ACG Interface Figure. RFIN Interface V GG 79- Figure. VGG Interface Rev. B Page of

7 TYPICAL PERFORMAE CHARACTERISTICS Data taken with VDD applied to Pin, VDD = 7 V. S S S T A = + C T A = + C T A = C RESPONSE (db) RETURN LOSS (db) FREQUEY (GHz) 79- FREQUEY (GHz) 79-9 Figure. Broadband Gain and Return Loss Figure. Output Return Loss vs. Temperature T A = + C T A = + C T A = C T A = + C T A = + C T A = C GAIN (db) NOISE FIGURE (db) FREQUEY (GHz) Figure. Gain vs. Temperature 79-7 FREQUEY (GHz) Figure. Noise Figure vs. Temperature 79- T A = + C T A = + C T A = C T A = + C T A = + C T A = C RETURN LOSS (db) NOISE FIGURE (db) FREQUEY (GHz) FREQUEY (GHz) 79- Figure. Input Return Loss vs. Temperature Figure. Noise Figure vs. Temperature, Low Frequency Rev. B Page 7 of

8 V DD = V V DD = 7V V DD = V 7 T A = + C T A = + C T A = C NOISE FIGURE (db) PdB (dbm) FREQUEY (GHz) Figure. Noise Figure vs. VDD 79- FREQUEY (GHz) Figure 9. PdB vs. Temperature 79- I DD = ma I DD = 7mA I DD = ma T A = + C T A = + C T A = C NOISE FIGURE (db) P SAT (dbm) 7 FREQUEY (GHz) Figure 7. Noise Figure vs. IDD 79- FREQUEY (GHz) Figure. PSAT vs. Temperature 79- T A = + C T A = + C T A = C V DD = V V DD = V V DD = 7V IP (dbm) PdB (dbm) FREQUEY (GHz) 79- FREQUEY (GHz) 79-7 Figure. Output IP vs. Temperature Figure. PdB vs. VDD Rev. B Page of

9 P SAT (dbm) FREQUEY (GHz) V DD = V V DD = V V DD = 7V 79- P OUT (dbm), GAIN (db), PAE (%) GAIN P OUT PAE INPUT POWER (dbm) 79- Figure. PSAT vs. VDD Figure. Power Compression at GHz ISOLATION (db) FREQUEY (GHz) T A = + C T A = + C T A = C 79-9 P OUT (dbm), GAIN (db), PAE (%) GAIN P OUT PAE INPUT POWER (dbm) 79- Figure. Reverse Isolation vs. Temperature Figure. Power Compression at GHz Rev. B Page 9 of

10 P OUT (dbm), GAIN (db), PAE (%) GAIN P OUT PAE 9 9 INPUT POWER (dbm) 79- GAIN (db), P SAT (dbm) GAIN P SAT NOISE FIGURE 7 I DD (ma) NOISE FIGURE (db) 79- Figure. Power Compression at GHz Figure. Gain, PSAT, and Noise Figure vs. IDD at GHz GAIN (db), P SAT (dbm) NOISE FIGURE (db) GAIN P SAT NOISE FIGURE V DD (V) Figure 7. Gain, PSAT, and Noise Figure vs. VDD at GHz 79- Rev. B Page of

11 Data taken with VDD applied to the bias tee at Pin. S S S T A = + C T A = + C T A = C RESPONSE (db) IP (dbm) FREQUEY (GHz) Figure 9. Broadband Gain and Return Loss, VDD = V, Supply to Bias Tee 79- FREQUEY (GHz) Figure. Output IP vs. Temperature, VDD = V, Supply to Bias Tee 79- T A = + C T A = + C T A = C 7 T A = + C T A = + C T A = C GAIN (db) PdB (dbm) FREQUEY (GHz) Figure. Gain vs. Temperature, VDD = V, Supply to Bias Tee 79- FREQUEY (GHz) Figure. PdB vs. Temperature, VDD = V, Supply to Bias Tee 79-9 T A = + C T A = + C T A = C T A = + C T A = + C T A = C NOISE FIGURE (db) P SAT (dbm) FREQUEY (GHz) Figure. Noise Figure vs. Temperature, VDD = V, Supply to Bias Tee 79-7 FREQUEY (GHz) Figure. PSAT vs. Temperature, VDD = V, Supply to Bias Tee 79- Rev. B Page of

12 EVALUATION PRINTED CIRCUIT BOARD J J J IN C V DD C C --- OUT U J C U C C H9 XXXX C C7 V GG J J 79- C9 Figure. Evaluation Board Layout C pf 9 7 J C.7µF + V DD C nf C pf V DD GND ACG RFOUT/V DD OUT J J IN RFIN 9 7 V GG ACG ACG 7 9 J C9.7µF + C nf C pf PACKAGE BASE GND C pf C7 nf 79- Figure. Evaluation Board Schematic Rev. B Page of

13 Table. List of Materials for Evaluation PCB Item Description J, J, J, J PCB mount SMA RF connector J, J DC pins C to C pf capacitor, package C to C7 pf capacitor, package C, C9.7 μf capacitor, tantalum U PCB --- evaluation PCB The circuit board used in the application should use RF circuit design techniques. Signal lines should have Ω impedance; connect the package ground leads and exposed paddle directly to the ground plane. Use a sufficient number of via holes to connect the top and bottom ground planes. The evaluation circuit board shown is available from Analog Devices, Inc., upon request. Circuit board material: Rogers or Arlon FR. Rev. B Page of

14 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS DETAIL A (JEDEC 9) PIN INDICATOR.. SQ.9. BSC... EXPOSED PAD PIN INDIC ATOR AREA OPTIONS (SEE DETAIL A)..7 SQ..9.. SEATING PLANE TOP VIEW MAX. NOM COPLANARITY.. REF BOTTOM VIEW. REF 9. MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUTION DESCRIPTIONS SECTION OF THIS DATA SHEET. PKG-9 COMPLIANT TO JEDEC STANDARDS MO--VHHD-. Figure 7. -Lead Lead Frame Chip Scale Package [LFCSP] mm mm and. mm Package Height (HCP--) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Lead Finish Moisture Sensitivity Level (MSL) Rating Package Description Ordering Quantity Package Option C to + C % matte Sn MSL -Lead LFCSP HCP-- TR C to + C % matte Sn MSL -Lead LFCSP, HCP-- 7 Tape and Reel EVAL-HMC9LP Evaluation Board -9-7-B All models are RoHS Compliant Parts. MSL rating indicates a maximum peak reflow temperature of C. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D79--/(B) Rev. B Page of