RDA1845 SINGLE CHIP TRANSCEIVER FOR WALKIE TALKIE. 1. General Description. Rev.1.0 Feb.2008

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1 RDA1845 SINGLE CHIP TRANSCEIVER FOR WALKIE TALKIE Rev.1.0 Feb General Description The RDA1845 is a single-chip transceiver for Walkie Talkie with fully integrated synthesizer, IF selectivity and base-band signal processing. The transceiver uses the CMOS process, support digital volume control and require the least external component. The package size is 6X6mm and is completely adjustment-free. The RDA1845 has a powerful low-if digital audio processor, this make it have optimum sound quality with varying reception conditions. The RDA1845 can be tuned to the worldwide frequency band for Walkie Talkie. 1.1 Features CMOS single-chip fully-integrated transceiver Support worldwide frequency band 300Mhz-500 MHz 12.5Khz,25Khz channels Digital low-if tuner Image-reject down-converter High performance A/D converter IF selectivity performed internally Fully integrated digital frequency synthesizer fully integrated on-chip RF and IF VCO fully integrated on-chip loop filter Auto DC offset calibration Digital auto frequency control (AFC) Digital auto gain control (AGC) Support multi-reference clocks 12.8/25.6Mhz 13/26Mhz Selectable pre/de-emphasis Figure 1. RDA1845 Top View Support CTCSS and CDCSS Receive signal strength indicator (RSSI) Provide programmable VOX and Squelch indicator Analog and digital volume control Reference clock drift compensation 3-wire serial control bus interface Directly support 32Ω resistance loading Integrated LDO regulator 2.7 to 3.3 V operation voltage 6X6mm 40 pin QFN package 1.2 Applications Cellular handsets Family radio services Walkie Talkies Page 1 of 11

2 2. Table of Contents 1. General Description Features Applications Table of Contents Functional Description Synthesizer Reference Clock Serial Control Interface Electrical Characteristics Transmit/Receiver Characteristics Control Interface Characteristics...6 Three-wire Interface Timing Pins Description Application Diagram Package Physical Dimension Change List Contact Information...11 Page 2 of 11

3 3. Functional Description Antana Switch PA RFIN LNA + - 0/90 I PGA Q PGA I ADC Q ADC DSP Core Audio filter Sub CH filter FM modem AFC loop DAC ADC AFOUT MIC DVDD V RFOUT LDO PA_drvier Synthesizer VCO XTAL RSSI GPIO Interface Bus INT/GPIO1 SQ/GPO2 VOX/GPO3 PDN SEN SCLK SDIO CTSIN CTSOUT MCU Figure 2. RDA1845 Block Diagram The RDA1845 transceiver uses a digital low-if architecture that avoids the difficulties associated with direct conversion while delivering lower solution cost and reduces complexity, and integrates a low noise amplifier (LNA) and PLL supporting the worldwide Walkie-Talkie band, a quadrature image-reject mixer, an analog band pass filter to rejection out band noise, a programmable gain control (PGA), high resolution analog-to-digital converters (ADCs), DSP core and high-fidelity digital-to-analog converters (DACs). The DSP core includes IF down-converter, FM modem, RSSI calculation, AFC control loop, audio/subaudio filter banks and CTCSS/CDCSS matched filter etc. 3.1 Synthesizer The frequency synthesizer generates the local oscillator signal which divide to quadrature, then be used to down convert the RF input to a constant low intermediate frequency (IF). The ADCs and DACs clocks are also come from the synthesizer. The VCO frequency is calibrated by reference clock. 3.2 Reference Clock The RDA1845 Support multi-reference clocks such as 12.8 MHz, 13 MHz, 25.6 MHz and 26 MHz 3.3 Serial Control Interface A three-wire serial interface is provided for host IC to read and write RDA1845 control registers. The serial control word is 24bits in length, comprised of a 18-bit data filed and 6-bit address field. Page 3 of 11

4 4. Electrical Characteristics Table 4-1 DC Electrical Specification (Recommended Operation Conditions): SYMBOL DESCRIPTION MIN TYP MAX UNIT DVDD Supply Voltage from LDO V T amb A mbient Temperature V IL CMOS Low Level Input Voltage (2) 0 0.3*DVDD V V IH CMOS High Level Input Voltage (2) 0.7*VDD DVDD V V TH CMOS Threshold Voltage (2) 0.5*VDD V Table 4-2 DC Electrical Specification (Absolute Maximum Ratings): SYMBOL DESCRIPTION MIN TYP MAX UNIT T amb Ambient Temperature I IN Input Current (1) ma V IN Input Voltage (1) -0.3 VIO+0.3 V V lna LNA Input Level C dbm Table 4-3 Power consumption specification (VCC = 3.0 to 3.3 V, T A = -25 to 85, unless otherwise specified) STATE DESCRIPTION Condition TYP UNIT I Rx I Tx I sleep Continue Receive RXON=1,PDN=1 60 ma Continue Transmit TXON=1,PDN=1 56 ma D eep sleep PDN=0 10 µa Page 4 of 11

5 5. Transmit/Receiver Characteristics Table 5-1 Receiver Characteristics (VCC = 3.0 to 3.3 V, TA = -25 to 85 C, unless otherwise specified) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT General specifications F in Input Frequency Range MHz NF Noise Figure Max RX Gain 3 db IP3 in Input IP3 Max RX Gain dbm Sensitivity 12.5Khz channel, 12dB SINAD -120 dbm ACS Adjacent Channel Selectivity ±12.5KHz db IR Image rejection db B loker 85 dbc Voice distortion 1.8% % Table 5-2 Transmit Characteristics (VCC = 3.0 to 3.3 V, TA = -25 to 85 C, unless otherwise specified) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT General specifications F out Output Frequency Range MHz P OUT Output Power dbm SINAD/SNR 49/49 ACP Adjacent channel power -62 dbc Modulation sensitivity 1.5kHz modulation offset 10 mv Voice distortion 0.3% % Modulation limitation khz db Notes: 1. Fin,Fout: for wide range from 300Mhz to 500Mhz, RDA1845 should tune bonding wire length; a given chip can cover 80Mhz or so. Page 5 of 11

6 6. Control Interface Characteristics Table 6-1 Three-wire Interface timing characteristics (VCC = 2.7 to 3.0 V, TA = -25 to 85 C, unless otherwise specified) PARAMETER SYMBOL Test Condition MIN TYP MAX UNIT SCLK Cycle Time t CLK 35 SCLK Rise Time t R ns SCLK Fall Time t F ns SCLK High Time t HI SCLK Low Time t LO SDIO Setup Time to SCLK t SU SDIO Hold Time from SCLK t HOLD SEN to SCLK Delay Time t EN1 SCLK to SEN Delay Time t EN2 SEN to SCLK Delay Time t EN3 SEN Pulse Width t W SCLK to SDO Time t CA ns Three-wire Interface Timing SDI D17 D16 D0 A5 A0 t HOLD SCLK SEN t SU t EN1 tlo t CLK thi t F t R t EN2 t EN3 t W Figure 3. Three-wire Interface Write Timing Diagram SDI A1 A0 SDO OD17 OD16 OD15 OD0 SCLK t CA t EN3 SEN t EN2 Figure 4. Three-wire Interface Read Timing Diagram Page 6 of 11

7 7. Pins Description Figure 5. RDA1845 Top View Table 7-1 RDA1845 Pins Description SYMBOL PIN DESCRIPTION 1 No connect. CTS_IN 2 CTCSS/CDCSS signal input SQ/GPO3 3 Squelch indicator output 4 Power supply for digital section IN1 5 MIC input pin IN2 6 MIC input pin AVSS 7 Ground for digital section XTAL2 8 Oscillator pin 2 XTAL1 9 Oscillator pin 1 10 No connect. 11 No connect. 12 Power supply for analog section AFOUT 13 Audio signal output to speaker 14 Power supply for analog section 15 Power supply for analog section AVSS 16 Ground Page 7 of 11

8 AVSS 17 Ground 18 Power supply for analog section 19 No connect. 20 No connect. 21 No connect. 22 No connect. RFIN 23 RF signal input 24 No connect 25 Power supply for analog section RFOUT 26 RF signal output 27 No connect 28 Power supply for analog section PABIAS 29 Power supply for PA 30 No connect 31 No connect AVSS 32 Ground for digital section CTS_OUT 33 CTCSS/CDCSS signal output VOX/GPO2 34 Voice activity indicator output PDN 35 Chip enable, low active INT/GPO1 36 Interrupt output SEN 37 Latch enable (active low) input for serial control bus. SCLK 38 Clock input for serial control bus. SDIO 39 Data input/output for serial control bus. 40 No connect Page 8 of 11

9 8. Application Diagram Notes: 1. All VDDS can connected together 2. U1: RDA1845 Chip Figure 6. RDA1845 Application Diagram Page 9 of 11

10 9. Package Physical Dimension Figure 7 illustrates the package details for the RDA1845. The package is lead-free and RoHS-compliant. Figure Pin 6x6 Quad Flat No-Lead (QFN) Page 10 of 11

11 10. Change List REV DATE AUTHER CHANGE DESCRIPTION v1.0e Original draft. v1.1e GSKUANG Page 11 of 11