Technology Trend of Ultra-High Data Rate Wireless CMOS Transceivers
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1 Technology Trend of Ultra-High Data Rate Wireless CMOS Transceivers Akira Matsuzawa and Kenichi Okada Tokyo Institute of Technology
2 Contents 1 Demand for high speed data transfer Developed high data-rate mm Wave transceivers ISSCC 2012: 10Gb/s 16QAM ISSCC 2014: 28Gb/s 4ch 16QAM, 64 QAM ISSCC 2016: 56Gb/s GHz, 16QAM High data-rate circuit design Widely flat frequency characteristics Low phase noise QVCO Conquer the f max limit of CMOS: 300 GHz Tx Future prospect of high data-rate wireless systems Summary AWAD A. Matsuzawa, Tokyo Tech.
3 AWAD A. Matsuzawa, Tokyo Tech. 2 Demand for high speed data transfer
4 AWAD A. Matsuzawa, Tokyo Tech. Progress of data rate in 60 GHz TRX 3 Data rate [G b/s] Career frequency is L. T. 100 GHz Developed by our group 10 Other groups Published year
5 AWAD A. Matsuzawa, Tokyo Tech. Transfer time vs. Data capacity 4 Transfer time of big contents can be reduced by increasing the data-rate. Millimeter wave can realize several second transfer of movie film in DVD. 10,000 Transfer time (sec) 1, Book Magazine Audio CD Visual DVD 200 Mbps 7 Gbps Millimeter wave Data capacity [M Byte] 1Byte=8bit 20 Mbps Current wireless
6 AWAD A. Matsuzawa, Tokyo Tech. 5 Our developed high data-rate mm Wave transceivers
7 AWAD A. Matsuzawa, Tokyo Tech. High freq. operation of semiconductor devices 6 f T and f max of CMOS are increased by technology scaling G f c max NF min gm Rg Rs max f c f f T f max GaAs CMOS InP f T CMOS InP GaAs Bulk CMOS Ultra-Thin-Body Fully-Depleted (UTB FD) SOI Multi-Gate MOSFETs
8 AWAD A. Matsuzawa, Tokyo Tech. Ultra-high speed data transfer in 60GHz band 7 Wider BW and high # of bits are required 16QAM Q BPSK: 1.7 Gbps QPSK: 3.5 Gbps 16QAM: 7 Gbps 64QAM:10.5Gbps D rate N BW I BW: 1.8GHz, 4ch
9 60GHz CMOS transceiver attained 28Gbps Direct conversion 60GHz CMOS transceiver *K. Okada,, A. Matsuzawa., ISSCC 2014 I Q 8 TX Output RX Input PA LNA RF amp. RF amp. I Mixer I Mixer Q Mixer Q Mixer LO buf. 60GHz QILO LO buf. BB amp. 20GHz PLL control logic 60GHz QILO I Q AWAD A. Matsuzawa, Tokyo Tech.
10 AWAD A. Matsuzawa, Tokyo Tech. FUJITSU 65nm CMOS Chip photo 4.2mm TX BB in 9 I MIXER LO BUF. TX out RX in PA LNA Q MIXER IMIXER & RF amp LO BUF. LO BUF. Q.OSC. Q.OSC. Logic PLL RX BB out QMIXER & RF amp TX: 186m WRX: 155mW PLL: 64mW CMOS 65nm, 1Al+11Cu TX: 186mW RX: 155mW PLL: 64mW LO BUF. Area TX 1.03mm 2 RX 1.25mm 2 PLL 0.90mm 2 Logic 0.67mm 2
11 AWAD A. Matsuzawa, Tokyo Tech. Measured characteristics 10 World's first 64QAM World s fastest 28Gbps Channel/ Carrier freq. Modulation ch GHz ch GHz 64QAM ch GHz ch GHz ch.1-ch.4 Channel bond 16QAM Data rate* 10.56Gb/s 10.56Gb/s 10.56Gb/s 10.56Gb/s 28.16Gb/s Constellation** Spectrum** TX EVM** -27.1dB -27.5dB -28.0dB -28.8dB -20.0dB TX-to-RX EVM*** -24.6dB -23.9dB -24.4dB -26.3dB -17.2dB
12 AWAD A. Matsuzawa, Tokyo Tech. Chip with antenna in package 11 The 60GHz RF chip are mounted on the antenna in package
13 AWAD A. Matsuzawa, Tokyo Tech. Recent developed 60GHz transceiver set 12 Small size 60GHz transceiver set has been developed. It attains 6Gbps data transfer. Smart phone Gate
14 Challenge for Frequency Interleave (FI) 13 Conventional f LO 3GHz 28GHz f LO This work ISSCC 2016, K. K. Tokgoz, K. Okada, A, Matsuzawa f LO1 3GHz 3GHz 16GHz 16GHz f LO2 f LO1 f LO2 Relaxed BB design Higher SNR Many challenges
15 AWAD A. Matsuzawa, Tokyo Tech. Die Photo of W-Band TRX 14 TX HB In TX Out TX LB In 3mm Doubler In 34GHz Tripler In 34GHz 2mm RX HB Out RX In RX LB Out 65nm CMOS
16 Comparison Table Our group 15 Reference [5, 6] [7] [4] [8] This work Integration TX, RX TX, RX TX, RX TX, RX TX, RX Frequency [GHz] Data Rate TRX Architecture Technology Power Cons. [mw] 16Gb/s (QPSK) TX: Heterodyne RX: Direct Conversion 65nm CMOS TX: 220 RX: Gb/s (QPSK) Heterodyne 45nm SOI TRX: Gb/s (16QAM) Direct Conversion 65nm CMOS TX: 251 RX: Gb/s (64QAM) Direct Conversion +Frequency Interleave 65nm CMOS TX: 544 RX: Gb/s (16QAM) Heterodyne+ Frequency Interleave 65nm CMOS TX: 260 RX: 300 [4] K. Okada, et al., ISSCC2014 [5] S. Kang, et al., RFIC2014 [6] S.V. Thyagarajan, et al., RFIC2014 [7] Y. Yang, et al., RFIC2014 [8] R. Wu, et al., ISSCC AWAD A. Matsuzawa, Tokyo Tech.
17 AWAD A. Matsuzawa, Tokyo Tech. 16 High data-rate circuit design
18 AWAD A. Matsuzawa, Tokyo Tech. High data rate techniques 17 Wider bandwidth and higher SNR are required to attain higher data rate Shannon s theory D BW log 1 rate 2 S N Multi-cascaded amplifier Wider bandwidth Higher SNR Passive mixer circuit Frequency interleaving Injection locked I/Q oscillator 7 bit ADC
19 AWAD A. Matsuzawa, Tokyo Tech. Effect of the gain flatness 18 Poor gain flatness makes ISI (Inter Symbol Interference) due to different gain for plus frequency and minus frequency.
20 AWAD A. Matsuzawa, Tokyo Tech. Multi-cascaded RF amplifiers 19 Multi-cascaded RF amplifier can increase the gain flatness due to the distributed resonant frequencies. 4-stage PA MIM TL TL MIM TL to antenna 4-stage CS-CS LNA ESD protection from antenna W=1m x40 1m x40 2m x20 2m x20
21 AWAD A. Matsuzawa, Tokyo Tech. Mixer circuit in TX 20 Passive mixer with resistive feedback RF amplifier can realize Widely flat impedance, rather than LC impedance matching method. Z 200// R 8 in( ) SW 2 Re Z RF LO Rf LO+ RSW 50 To PA Matching network ZRF LO- RSW RSW 200 Zin BB input Rf ZRF LO+ RSW 200 Zin
22 AWAD A. Matsuzawa, Tokyo Tech. Measured gain of TX circuit 21 The gain flatness of 2 db is attained for the band width of 4 GHz. Gain [db] Frequency [GHz]
23 AWAD A. Matsuzawa, Tokyo Tech. Required phase noise of IQ-VCO for 16QAM 22 A phase noise of LT. -90dBc/Hz@1MHz is required for 16QAM systems A reported phase noise of 60GHz IQ VCO is at most Required CNR [db] K. Scheir, et al., ISSCC, pp ,Feb QAM 8PSK AM-AM of PA QPSK Phase noise 1MHz offset
24 AWAD A. Matsuzawa, Tokyo Tech. Q of inductors and capacitor 23 Q of capacitor is rapidly degraded with frequency. Q of Less than 10 at 60 GHz at most. Low phase noise 60 GHz VCO is hard to be realized. Q switched capacitor 2nH inductor 8nH inductor Qc < 60GHz 0.2nH inductor Frequency [GHz]
25 Injection locking technique 24 Injection locking technique is a very important circuit technique for high frequency signal generation and frequency divider. Phase noise of the oscillator is mandated by the injection. t INJ N Output INJ P Injection signal t parallel injection Phase noise PN ILO Locking frequency range PN f L INJ f o 2 Q 20 log( N I inj I OSC AWAD A. Matsuzawa, Tokyo Tech. ) N: Multiple number N=3
26 AWAD A. Matsuzawa, Tokyo Tech. Injection locked 60GHz I/Q VCO 25 Developed the injection locked 60 GHz quadrature VCO The 60 GHz quadrature VCO is injected by 20 GHz PLL PN OSC ( db) PN ( db) INJ 20log M Xtal PLL 20GHz VCO Injection pulse 60GHz IVCO 60GHz I 60GHz Q 60GHz QVCO A. Musa, K. Okada, A. Matsuzawa., in A-SSCC Dig. Tech. Papers, pp , Nov
27 Low phase noise can be realized 26 Quadrature injection locked 60GHz oscillator with 20GHz PLL Low phase noise of Previous one is Best phase noise is achieved GHz, -96dBc/Hz-1MHz offset A. Musa, K. Okada, A. Matsuzawa., in A-SSCC Dig. Tech. Papers, pp , Nov AWAD A. Matsuzawa, Tokyo Tech.
28 AWAD A. Matsuzawa, Tokyo Tech. 27 Conquer the f max limit of CMOS 300 GHz Tx Prof. Fujishima s group s work of Hiroshima Univ.
29 CMOS 300GHzTransmitter 28 It is almost impossible to amplify the 300 GHz signal by CMOS technology. The 2 nd step-up mixer is used and combine the signal in the balun. To increase the RF power. The image suppression is needed. 10 GHz 48 GHz IF Tripler GHz LO 145 GHz IF LO 2 Square Mixer 300 GHz RF Balun 10 GHz IF Quasi-SSB Mixer IF LO 2 K. Takano, et al., Hiroshima Univ., ISSCC 2017, S AWAD A. Matsuzawa, Tokyo Tech.
30 Performance comparison 29 Comparable frequency with compound semiconductor devices. Over 100 Gbps has been attained. K. Takano, et al., Hiroshima Univ., ISSCC 2017, S AWAD A. Matsuzawa, Tokyo Tech.
31 AWAD A. Matsuzawa, Tokyo Tech. 30 Future prospect of high data-rate wireless systems
32 AWAD A. Matsuzawa, Tokyo Tech. Calculations for data rate of TRX 31 Calculate the data rate as function of career frequency and Tx power Shannon s theory D rate BW log 2 1 SNR D rate BW log 10 SNR 0.3 BW SNR( db) 3 Received signal P RX ( db) P TX B OFF G AT G AR I L S LOSS Spatial loss Noise S LOSS P n c 4 20log 20log 20log df 4d 4dfc c ( dbm) log BW d: distance f c : career frequency NF c
33 AWAD A. Matsuzawa, Tokyo Tech. 60GHz Link budget (QPSK) 32 6dBm(P out )-4dB(back-off)=2dBm Tx Antenna gain:6dbi -71.5dB(1.5m loss)+6dbi(tx)+6dbi(rx) Required CNR: 9.8dB Suppress Phase noise PA nonlinearity I/Q mismatch ISI -3dB(loss) -60.5dBm Rx +6dB(NF) -80.6dBm =-174dBm(kT)+93.4dB(2.2GHz-BW) CNR +14.0dB -74.6dBm
34 Estimated data rate 33 Higher data rate can be expected up to the certain frequency, however it is reduced after that frequency. Higher power is required to increase the data rate. Data rate (Gbps) Dashed line: consider the SNR Solid line: neglect the SNR 64QAM Pt=20dBm 16QAM QPSK BPSK Pt=10dBm Pt=0dBm Carrier frequency (GHz) AWAD A. Matsuzawa, Tokyo Tech. Distance:1m Antenna gain:6dbi NF: 6dB Back off: 4dB Power loss: 3dB
35 AWAD A. Matsuzawa, Tokyo Tech. Future direction 34 Future direction should be chosen by the usage model High frequency and high power Best, but very difficult!! High frequency but low power High gain antenna Sharp beam Fixed point only! Medium frequency but high power Low gain antenna Short distance only! Reasonable high data rate Reasonable long distance
36 AWAD A. Matsuzawa, Tokyo Tech. Summary 35
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