A 1.7-to-2.2GHz Full-Duplex Transceiver System with >50dB Self-Interference Cancellation over 42MHz Bandwidth

Transcription

1 A 1.7-to-2.2GHz Full-Duplex Transceiver System with >50dB Self-Interference Cancellation Tong Zhang, Ali Najafi, Chenxin Su, Jacques C. Rudell University of Washington, Seattle Feb. 8, 2017 International Solid-State Circuits Conference 1 of 34

2 Very Crowded RF Spectrum RFID Broadcast TV ZigBee GPS Cellular Phones Wi-Fi/ Bluetooth 300 MHz 6GHz Weather Radar Satellite Com. Police Radar RF spectrum has become saturated w/ standards. International Solid-State Circuits Conference 2 of 34

3 Full-Duplex (FD) Communication Frequency Division Duplex FDD) +30dBm TX Guard Band -80dBm RX Freq Higher Spectral In-band Full-Duplex (FD) TX RX Required SNR 120dB Freq FD communication potentially improves spectral efficiency up to 2X. International Solid-State Circuits Conference 3 of 34

4 Assumed SI Cancellation Distribution Air Interface Circulator RX Input Analog Front End LNA Digital Front End ADC RX Digital BB Two-Antennas Analog RF SI Canceler LO TX Output DAC TX Digital BB ~30dB ~50dB ~40dB This analog front-end chip targets 50dB SI Cancellation over a 42MHz BW International Solid-State Circuits Conference 4 of 34

5 Outline Wideband SI Cancellation Challenges Proposed Dual-path Canceler A Prototype 40nm CMOS FD Radio Measurement Results Conclusion International Solid-State Circuits Conference 5 of 34

6 Self-Interference Cancellation (SIC) in FD Radio RX Ideal SI Canceler Circulator Two-Antennas Feedforward Canceler RX input Wide cancellation BW Minimal noise, power, area High linearity TX Large In/Out impedance International Solid-State Circuits Conference 6 of 34

7 Leakage Path Channel Response Time Delay Versions of Leakage Signal Environmental Reflection Antenna Reflection Direct Coupling LNA Circulator Impulse Response Direct Coupling Antenna Reflection Environmental Reflection Circulator Phase Response > 10 Degree Phase Change in 40MHz BW Leakage Path Channel Response Mag BW Freq International Solid-State Circuits Conference 7 of 34

8 Wideband SIC Prior-Art RF Frequency Domain Equalization High Speed Current DAC Synthesizes Inverse TX LO-0A Two-Antennas N-Path Filter Circulator LO-0B BB DAC BB DAC + Mixer LNA LO-1A Gm LO-1B LO-2A Gm Gm LO-2B LNA LO-3A Gm LO-3B J. Zhou et al, ISSCC 2015 S. Ramakrishnan et al, VLSI 2016 Challenging to design a single path broadband, high SI canceler International Solid-State Circuits Conference 8 of 34

9 Dual-Path Self-Interference Architecture Circulator Two-Antennas RX_IN Coarse Canceler Analog FIR Filter LNA LO Fine Canceler Analog FIR Filter RX_BB error Discrete TX_OUT On Chip LO TX_BB Two cancellation paths, at RF and Baseband Enhance the SI cancellation depth and BW International Solid-State Circuits Conference 9 of 34

10 RF Canceler Top Level Diagram TX TX-to-RX Interface Isolation ~ 30dB RX Two-Antennas Circulator + W0 W1 W2 WN Discrete Form Published in: D. Bharadia et al, SigComm 2013 LNA International Solid-State Circuits Conference 10 of 34

11 Canceler Noise - BW Tradeoffs Proposed 5-taps Adaptive Filter RX Baseline NF International Solid-State Circuits Conference 11 of 34

12 Linearity of the RF Canceler TX TX-to-RX Interface Isolation ~ 30dB RX Two-Antennas Circulator Attenuator + W0 W1 W2 WN LNA International Solid-State Circuits Conference 12 of 34

13 RF Canceler Linearity vs C1 TX 3:1 Two-Antennas Circulator C 1 C 1 SI Canceler RX + Canceler Linearity, RX NF versus C 1 Proposed C 1 = 130fF RX NF = 4.7dB IIP 3 = 36dBm LNA RX Baseline NF C 1 provides attenuation to improve canceler IIP 3 International Solid-State Circuits Conference 13 of 34

14 RF Canceler Linearity vs Ztx TX RX 3:1 Two-Antennas Circulator SI Canceler Z tx ~9 Z in >7k Z out >500 LNA Low Z tx reduces input voltage swing of the SI canceler Large Z in / Z out relax loading for /LNA matching network International Solid-State Circuits Conference 14 of 34

15 BB Canceller Top Level Diagram I/Q MX Output RX BB Output Canceller path includes down-conversion mixer Design methodology similar to RF canceller International Solid-State Circuits Conference 15 of 34

16 Baseband Path Delay Compensation LNA 1 BB Circuits 2 A 1 f TX Leakage RX Path Receiver Path PLL BB Can Path A 1 A 2 RX BB Output f SIC TX Signal f Adaptive Filter Delay Match between RX & BB Cancellation Path for TX Carrier International Solid-State Circuits Conference 16 of 34 3 A 1 f TX Leakage BB Can Path

17 TX SI Phase Noise Cancellation LNA 1 BB Circuits 2 A 1 f TX Leakage RX Path PN LO RX Path A 1 A 2 SIC f f PLL LO BB Can Path RX BB Output TX Signal f 3 Adaptive Filter A 1 TX Leakage BB Can Path f Cancellation of TX leakage reciprocal mixing with LO PN in RX International Solid-State Circuits Conference 17 of 34

18 Outline Wideband SI Cancellation Challenges Proposed Dual-path Canceller A 40nm CMOS Prototype Chip Measurement Results Conclusion International Solid-State Circuits Conference 18 of 34

19 A 40nm CMOS Implementation of Proposed FD System RF_IN+ BB_Q+ BB_Q- RF_IN- TD2 BB G LNA G m m Comb. TD2 BB_I+ BB_I- RF SIC RF Adaptive Filter Integer-N Synthesizer CP/PFD /N VCO /2 _OUT K=0.8 3:1 XFMR C 1 C 1 C 2 BB / PN SIC Main C 2 K=0.8 1:1 0 / I/Q MX Mid BB G m Comb. Baseband Adaptive Filter _IN+ 1 st _IN- International Solid-State Circuits Conference 19 of 34

20 RF Analog FIR-Based Canceller Output C 1 C 1 W0 W1 W2 W3 W4 RX Input Tap Delay Line Buffer Vin+ 160fF fF Vin- RF Time Delay = 65ps V DD =1.2V V DD =1.2V To Next 6-bit VGA V DD =1.2V V DD =1.2V 1-bit for Signal Polarity RF Canceler P-1dB = 27dBm, IIP3 = 36dBm International Solid-State Circuits Conference 20 of 34 I out+ I out-

21 BB Analog FIR-Based Canceller Output C2 C2 Passive Mixer K0 K1 KN RX BB Signal Path V DD =1.8V Gm-C All-Pass Filter BB Time Delay = 10ns M4 C M5 Vout Vin M1 M2 M3 BB Canceler P-1dB = 26.5dBm, IIP3 = 34.5dBm S. K. Garakoui et al., JSSC 2015 International Solid-State Circuits Conference 21 of 34

22 Power Amplifier Topology First Stage V DD =2.5V Mid Stage Main Stage _IN+ _IN- V DD =2.5V K=0.8 1:1 C b C b V DD =2.5V K=0.8 1:3 _OUT V DD =2.5V F. Bruccoleri et al., ISSCC 2002 A. Afsahi et al., ISSCC 2010 First Stage uses noise-cancelling topology to reduce output noise floor Main Stage uses G m linearization technique to improve linearity International Solid-State Circuits Conference 22 of 34

23 TSMC 40nm Prototype Chip Die Photo Integer-N Synthesizer Shift Register TX Canceler Input Path Process Details TSMC 40nm 1.75mm RF Canceler Receiver (RX) LNA Phase Tuning Passive Mixer Baseband Canceler Main Stage Middle Stage 6 Metal Stack 1 UTM Layer Total Area: 1.75mm 2mm Bandgap Circuitry BB TIA True Time Delay BB Comb. Circuitry 1 st Stage 2mm International Solid-State Circuits Conference 23 of 34

24 Outline Wideband SI Cancellation Challenges Proposed Dual-path Canceller A 40nm CMOS Prototype Chip Measurement Results Conclusion International Solid-State Circuits Conference 24 of 34

25 Measurement Setup Full-duplex Chip Circulator Meca CS Rx Input Tektronix Probe P6246 Ant Rx Circulator Two-Antennas RF Balun Anaren BD1631J50100AHF RF Adaptive Filter LNA PLL MX BB Adaptive Filter BB Output Agilent E4440A PSA Spectrum Analyzer Tunable Delay MX Tx Tx Output K=0.8 Tx Input Three-Stage RF Balun Anaren BD1631J50100AHF Agilent E4438C ESG Vector Signal Generator Agilent E4446A PSA Spectrum Analyzer Filter Coefficients Altera Cyclone III Development Board with ADC/DAC Card International Solid-State Circuits Conference 25 of 34

26 Measured Power, EFF and EVM Output Power & 1.96GHz 40Mbp/s 20dBm 16QAM 1.96GHz P -1dB = 25.1dBm P sat = 26.5dBm P out E EVM =5.2% P -1dB = 25.1dBm, P sat = 26.5dBm, Max E = 32% International Solid-State Circuits Conference 26 of 34

27 Measured TX Suppression vs. Bandwidth 42MHz RF SIC Only RF & BB SIC BB SIC Only International Solid-State Circuits Conference 27 of 34

28 Measured Suppression w/ 40MHz 16 QAM Signal w/ RF Canceler w/o Cancellation w/ RF & BB Canceler Cancellation = (-79.28) = 50.85dB Cancellation = (-79.28) = 50.85dB International Solid-State Circuits Conference 28 of 34

29 RX NF w/ and w/o Cancellation RX NF, Canceler Off, TX on ~6dB RX NF, Canceler On, TX on ~1.5dB RX NF, Canceler off, TX off International Solid-State Circuits Conference 29 of 34

30 TX SI PN Cancellation Measurement Setup Measured Results LNA PLL >10dB Adaptive Filter Signal International Solid-State Circuits Conference 30 of 34

31 System Power Breakdown Canceler Misc. Blocks (11.5mW) 23% (5mW) 11% (10.4mW) 21% (22mW) 45% Receiver Synthesizer Power consumption of the is not included. International Solid-State Circuits Conference 31 of 34

32 Comparison Table Architecture J. Zhou ISSCC 2015 FD Equalization Van Dan Broek ISSCC 2015 VM- Downmixer D. Yang JSSC 2015 Duplexing LNA J. Zhou ISSCC 2016 Circulator+ BB SIC This Work Dual-path + Adaptive Filter Technology 65nm 65nm 65nm 65nm 40nm RX Frequency (GHz) TX out -to-rx in Iso. (db) N/A N/A N/A Integrated No Yes Yes No Yes Integrated PLL No No No No Yes SI Max Suppress. (db) N/A N/A 55 Cancel. BW Cancel. (db) BW (MHz) 15 / Canceller Power (mw) N/A N/A (RF) +8 (BB) SIC NF Degradation (db) N/A (RF)+0.5(BB) RF Canceller Area (µm 2 ) N/A N/A N/A N/A BB Canceller Area (µm 2 ) N/A N/A N/A N/A Canceller IIP3 (dbm) N/A N/A N/A N/A 36 (RF) / 34.5 (BB) Canceller P-1dB (dbm) N/A N/A N/A N/A 27 (RF) / 26.5 (BB) TX SI PN Suppress. (db) N/A N/A N/A N/A 10 Active Area (mm 2 ) International Solid-State Circuits Conference 32 of 34

33 Conclusion Dual-path SI cancelling architecture is proposed for full-duplex radios. This SI canceller performance achieves: Wideband SIC (50dB >42MHz BW) Low power (11.5mW) Modest noise figure degradation (1.55dB) High Linearity (36dBm/34.5dBm IIP 3 ) Feasibility of a highly integrated CMOS fullduplex transceiver operating at GHz has been demonstrated. International Solid-State Circuits Conference 33 of 34

34 Acknowledgements National Science Foundation ( ) CDADIC Google Incorporated Marvell for chip fabrication Advice of Visvesh Sathe and Li Lin International Solid-State Circuits Conference 34 of 34