T. Taris, H. Kraïmia, JB. Begueret, Y. Deval. Bordeaux, France. 12/15-16, 2011 Lauzanne, Switzerland

Transcription

1 1 MOSFET Modeling for Ultra Low-Power RF Design T. Taris, H. Kraïmia, JB. Begueret, Y. Deval Bordeaux, France

2 2 Context More services in Environment survey Energy management Process optimisation Aging follow up Human to machine interaction Wireless Sensor Networks Item tracking Localisation service Health monitoring 2

3 3 Challenges Energy management Context Environment survey More services in Process optimisation Aging follow up Wireless Sensor Networks Localisation service Human to machine interaction Low cost Item tracking Small form factor Health monitoring Low power Price/node <1$ 1 cm 3 Run 10 years! 3

4 4 Challenges Energy management Context Environment survey More services in Process optimisation Aging follow up Wireless Sensor Networks Localisation service Human to machine interaction Low cost Item tracking Small form factor Health monitoring Low power Price/node <1$ 1 cm 3 Run 10 years! 4

5 5 Context WSN Node Basics Large Power Consumption Data processing Computation Memory writing/reading Radio module Data broadcasting Communications Radio Data processing Power Unit Sensor/ Actuator Sensor/Actuator Environment Interface Power Unit Supply Energy Management/Storage

6 6 Context Low Duty Cycle WSN Node Basics Large Power Consumption Rx Tx WSN node in Rx mode most of the time Radio module Data Sensor/ Radio Sensor/Actuator processing Power Unit Actuator Data broadcasting Environment Interface Communications Power Unit Supply Energy Management/Storage

7 7 Context Radio Circuit/System Considerations Various approaches to improve the power saving in Radio LNC LNA Transistor & System Level RF Compact RF Demodulator BB Data SOM Mixer LO Compact RFFE Demodulators LNA Transistor Level Building Block Combination RF rmances Perfor Mixer LO Targeted Area Demod Concept Standalone Building Blocks Optimum biasing Circuit technique Compact RFFE LNC, SOM. ULP LNA, Mixer, System Level Power Consumption 7

8 8 Context Radio Circuit/System Considerations Various approaches to improve the power saving in Radio LNC LNA Transistor & System Level RF Compact RF Demodulator BB Data SOM Mixer LO Compact RFFE Demodulators LNA Transistor Level Building Block Combination RF rmances Perfor Mixer LO Targeted Area Demod Concept Standalone Building Blocks Optimum biasing Circuit technique Compact RFFE LNC, SOM. ULP LNA, Mixer, System Level Power Consumption 8

9 9 OUTLINE Context From analog to RF Metric Low Noise Amplifier Implementation Conclusions & Perspectives 9

10 1 0 From analog to RF Metric Low Power Analog Amplifiers Voltage Amplifier v in A v BW v out GBW A v. BW Figure Of Merit for Low Power amplifier FOM LPamplifier GBW I D 10

11 1 1 Voltage Amplifier From analog to RF Metric Low Power Analog Amplifiers Configurations v in v out v out or A v BW vin + - I d C L vin + - R s C gs I d v out GBW A v. BW GBW gm 2. C L g 2. C m GBW. gs r R ds S Figure Of Merit for Low Power amplifier FOM LPamplifier GBW I D g C. I m D g I m D 11

12 1 2 From analog to RF Metric Low Power Analog Metric Figure Of Merit for Low Power Analog Maximum in WI region Transductor gain of the device FOMLP ana Current log g I m D 1 ) gm/id(v ,00 0,20 0,40 0,60 0,80 1,00 consumption Weak Inversion Strong Inversion Vgs(V) Moderate Inversion FOM LPanalog is maximum in WI region 12

13 1 3 From analog to RF Metric Low Power RF Circuits RF Building Blocks LNA G V IP3 NF CP1 Mixer IP3 LO>IF G V LO>RF Oscillator BW PN P out FOM LNA FOM mixer FOM osc System Level FOM RFBlock 13

14 1 4 From analog to RF Metric Low Power RF Circuits RF Building Blocks Topologies / Architectures LNA G V IP3 NF CP1 Mixer IP3 LO>IF G V LO>RF Oscillator BW PN P out Single or diff. Active or Passive Harmonic or Relax Cascode Common gate Common source Single device Fully or Single balanced Cross Coupled LC RC oscillator Ring oscillator FOM LNA FOM mixer FOM osc System Level FOM RFBlock gm? I D Transistor Level 14

15 1 5 From analog to RF Metric Low Power RF LNA Low Noise Amplifier Topologies / Architectures input G V P cons NF IP3 RF output Most important characteristics A large voltage gain G v at f RF A low noise figure NF at f RF Figure Of Merit for Low Power LNA G. f FOM V RF LPLNA ( F 1 ). Pcons System Level Transistor Level 15

16 1 6 From analog to RF Metric Low Power RF LNA Low Noise Amplifier Topologies / Architectures input G V P cons NF IP3 RF output Most important characteristics v in I D v out v out I D v in v in I D v out A large voltage gain G v at f RF Common Source Common Gate Cascode A low noise figure NF at f RF Figure Of Merit for Low Power LNA G. f FOM V RF LPLNA ( F 1 ). Pcons System Level Transistor Level 16

17 1 7 From analog to RF Metric Low Power RF LNA Low Noise Amplifier Common Source Analysis I D v out input G V P cons NF IP3 RF output vin + - R s Cgs i ² ( f ) 4kT. d g m Most important characteristics A large voltage gain G v at f RF A low noise figure NF at f RF Figure Of Merit for Low Power LNA G V MOS 1 g jc m gs Pcons I D 1 Fmin 1 MOS g. R m gm R C R s s gs RF with f T gm 2. C gs G. f FOM V RF LPLNA ( F 1 ). Pcons System Level gm. ft FOM LPLNA MOS ID Transistor Level 17

18 1 8 From analog to RF Metric Low Power RF LNA Figure Of Merit for low power LNA Maximum in MI region Transductor gain of the device gm. f FOMLP LNA I D Cutoff frequency of the device T (S.THz/A) 0,60 0,50 0,40 0,30 0, ,10 Current 0,00 0,20 0,40 0,60 0,80 1,00 consumption Weak Inversion Strong Inversion Moderate Inversion FOM LPLNA is maximum in MI region 18

19 1 9 OUTLINE Context From analog to RF Metric Low Noise Amplifier Implementation Conclusions & Perspectives 19

20 2 0 Ultra Low Power LNA Forward Body Biased Cascode LNA 2.4 GHz LNA - CMOS 0.13µm 440µW@0.5V L pk C m2 M V C m3 out I d =880µA 10dB gain S21(dB) S22(dB) S11(dB) -25 1,50 2,00 2,50 3,00 3,50 L g M1 0.3V Freq(GHz) in R pol 8 NF(dB) Nfmin(dB) V pol L s 3.4dB NF MOS device in MI region to maximise FOM LPLNA 0 Bulk forward biasing to reduce V th 1,00 1,50 2,00 2,50 3,00 3,50 4,00 Freq(GHz) 20

21 GHz LNA - CMOS 0.13µm Ultra Low Power LNA L pk C m2 M V out C m3 Forward Body Biased Cascode LNA Gain & NF vs Power Consumption [db] 8 6 S 21 NF i d 4 v in in L g M1 0.3V 2 P cons [µw] R pol L s V pol Limited value on Si Peaking Load 21

22 GHz LNA - CMOS 0.13µm Ultra Low Power LNA L pk C m2 M V out C m3 Forward Body Biased Cascode LNA Gain & NF vs Power Consumption [db] 8 6 S 21 NF i d 4 v in in L g M1 0.3V 2 P cons [µw] R pol L s V pol Only 6.8 db@250µw! Limited value on Si Peaking Load 22

23 GHz LNA - CMOS 0.13µm Ultra Low Power LNA L pk C m2 M V out C m3 Forward Body Biased Cascode LNA Gain & NF vs Power Consumption [db] 8 6 S 21 NF i d 4 v in in L g M1 0.3V 2 P cons [µw] R pol L s f T decrease V pol i v d in f f T R s 1 1(2fR s )² Inductive Degeneration Only 6.8 db@250µw! Limited value on Si Peaking Load 23

24 GHz LNA - CMOS 0.13µm Ultra Low Power LNA L pk C m2 M V out C m3 Forward Body Biased Cascode LNA Gain & NF vs Power Consumption [db] 8 6 S 21 NF i d 4 v in in L g M1 0.3V 2 P cons [µw] R pol L s f T decrease V pol i v d in f f T R s 1 1(2fR Limited value on Si s )² Inductive Degeneration Peaking Load Only 6.8 db@250µw! Strong Inversion Techniques 24

25 2 5 Ultra Low Power LNA Select the best suited topology To compensate for the low g m in MI region I I bias M P I d M P I d M P I d out R F MN in R F MNout OR? in R F out in M N in M N M N Single Transistor Stage (STS) Self Biased Inverter (SBI) active load configurations are preferred! 25

26 2 6 Ultra Low Power LNA Select the best suited topology Comparison of the Gain BandWidth (GBW) product 30 Gain (d db) Self Biased Inverter (SBI) 0 1G Single Transistor Stage (STS) GBW STS 10G Frequency (Hz) 100G GBW SBI the one of self biased inverter is the largest! 26

27 2 7 Ultra Low Power LNA Current reuse LNA 24GH 2.4 GHz LNA - CMOS 0.13µm 0.6V VCC VDD 04V 0.4V I d 900µm L pk R F M 2 R F V pol2 C m2 out in out in L M C g C 3 m3 l C m1 M 1 700µm C L g L pk C tune L g V pol1 LNA core buffer Transistors are in MI region to maximise FOM LPLNA 27

28 2 8 Ultra Low Power LNA Current reuse LNA 24GH 2.4 GHz LNA - CMOS 0.13µm 100µW@0.5V 0.6V 15 VCC VDD 15dB gain V I d 5 L pk (db) 0 S 21 R F M 2 V pol2 C m2 out S 11 in L g C l M 1 C m1 C tune M 3 C m3 4.8dB NF -15 6,5 NF@0.6V NF@0.5V NF@0.4V freq (GHz) V pol1 LNA core buffer Noise Fugure (db) ,5 5 4, ,1 2,2 2,3 2,4 2,5 2,6 2,7 2,8 2,9 freq (GHz) 28

29 2 9 Ultra Low Power LNA Current reuse LNA 24GH 2.4 GHz LNA - CMOS 0.13µm 100µW@0.5V in L g VCC 0.4V R F C l 0.6V I d M 2 M 1 C m1 V pol2 VDD L pk M 3 C m2 out C m3 [db] Gain & NF vs Power Consumption C tune S 21 NF P cons [µw] V pol1 Still 13.4dB@60µW! 29

30 3 0 Ultra Low Power LNA Current reuse LNA 24GH 2.4 GHz LNA - CMOS 0.13µm 100µW@0.5V in L g VCC 0.4V R F C l 0.6V I d M 2 M 1 C m1 V pol2 VDD L pk M 3 C m2 out C m3 [db] Gain & NF vs Power Consumption C tune S 21 NF P cons [µw] V pol1 f T decrease Still 13.4dB@60µW! i. d C C tune gst Capacitive feedback v in C gdt 2 30

31 3 1 Ultra Low Power LNA Current reuse LNA 24GH 2.4 GHz LNA - CMOS 0.13µm 100µW@0.5V in L g VCC 0.4V R F C l 0.6V I d M 2 M 1 C m1 V pol2 VDD L pk M 3 C m2 out C m3 [db] Gain & NF vs Power Consumption C tune S 21 NF P cons [µw] V pol1 f T decrease Still 13.4dB@60µW! id Ctune v in C gdt C gst. 2 Capacitive feedback Suited for MI operation 31

32 3 2 Ultra Low Power LNA Comparison with the state of art 30 FOM LNA [13] 1 [14] Gv IIP abs 3 f mw RF FOM LNA [11] [12] 1 ( F 1) P abs cons mw [12] 2 GHz P DC (µw) [10] A. Shameli A novel Ultra Low Power Low Noise Amplifier using Differential Inductor Feedback, IEEE ESSCIRC, Montreux, Switzerland, Sep. 2006, pp [11] B. G. Perumana, A fully monolithic 260-μW, 1-GHz subthreshold low noise amplifier, IEEE MiWCL, Vol. 15, N. 6, pp , June [12] H. Lee, A 3 GHz subthreshold CMOS low noise amplifier, IEEE RFIC Symposium, San Francisco, CA, USA, June 2006, pp [13] V. Aaron, «A subthreshold low-noise amplifier optimized for ultra-low -power applications in the ISM band, IEEE MTT, Vol. 56, N 2, pp , feb [14] J. Li, S. Hassan A 0.7 V 850µW CMOS LNA for UHF RFID reader, MOTL, Vol. 52, N 12, pp , dec [15] C.J. Jeong, W. Qu, Y. Sun, D.Y. Soon, S.K. Han, S.G. Lee A 1.5 V, 140 µa CMOS Ultra Low Power Common Gate LNA, IEEE RFIC, Baltimore, USA, June 2011, pp

33 3 3 Ultra Low Power LNA Comparison with the state of art This work Cascode FOM LNA 2 1 [13] 1 (g m.f T /I D ) max 10 1 [15] [14] G [10] v IIP abs 3 f mw RF FOM LNA [11] [12] 1 ( F 1) P abs cons mw [12] 2 GHz P DC (µw) [10] A. Shameli A novel Ultra Low Power Low Noise Amplifier using Differential Inductor Feedback, IEEE ESSCIRC, Montreux, Switzerland, Sep. 2006, pp [11] B. G. Perumana, A fully monolithic 260-μW, 1-GHz subthreshold low noise amplifier, IEEE MiWCL, Vol. 15, N. 6, pp , June [12] H. Lee, A 3 GHz subthreshold CMOS low noise amplifier, IEEE RFIC Symposium,, San Francisco, CA, USA, June 2006, pp [13] V. Aaron, «A subthreshold low-noise amplifier optimized for ultra-low -power applications in the ISM band, IEEE MTT, Vol. 56, N 2, pp , feb [14] J. Li, S. Hassan A 0.7 V 850µW CMOS LNA for UHF RFID reader, MOTL, Vol. 52, N 12, pp , dec [15] C.J. Jeong, W. Qu, Y. Sun, D.Y. Soon, S.K. Han, S.G. Lee A 1.5 V, 140 µa CMOS Ultra Low Power Common Gate LNA, IEEE RFIC, Baltimore, USA, June 2011, pp

34 3 4 Ultra Low Power LNA Comparison with the state of art This work SBI This work Cascode FOM LNA 30 Dedicated MI design Circuit technique 1 (g m.f T /I D ) max [13] 2 2 [13] [15] [14] G [10] v IIP abs 3 f mw RF FOM LNA [11] [12] 1 ( F 1) P abs cons mw [12] 2 GHz P DC (µw) [10] A. Shameli A novel Ultra Low Power Low Noise Amplifier using Differential Inductor Feedback, IEEE ESSCIRC, Montreux, Switzerland, Sep. 2006, pp [11] B. G. Perumana, A fully monolithic 260-μW, 1-GHz subthreshold low noise amplifier, IEEE MiWCL, Vol. 15, N. 6, pp , June [12] H. Lee, A 3 GHz subthreshold CMOS low noise amplifier, IEEE RFIC Symposium,, San Francisco, CA, USA, June 2006, pp [13] V. Aaron, «A subthreshold low-noise amplifier optimized for ultra-low -power applications in the ISM band, IEEE MTT, Vol. 56, N 2, pp , feb [14] J. Li, S. Hassan A 0.7 V 850µW CMOS LNA for UHF RFID reader, MOTL, Vol. 52, N 12, pp , dec [15] C.J. Jeong, W. Qu, Y. Sun, D.Y. Soon, S.K. Han, S.G. Lee A 1.5 V, 140 µa CMOS Ultra Low Power Common Gate LNA, IEEE RFIC, Baltimore, USA, June 2011, pp

35 3 5 OUTLINE Context From analog to RF Metric Low Noise Amplifier Implementation Conclusions & Perspectives 35

36 3 6 Case of study LNA Conclusions & Perspectives RF Building Block Design Methodology Circuit performances Capacitive divider RF Circuit technique Optimize FOM vs Power FOM circuit G. f FOM V RF LPLNA ( F 1 ). Pcons Self Biased Inverter Best suited topology FOM transistor g m. T FOM LPLNA MOS ID f Active Device biasing MI region 36

37 3 7 Conclusions & Perspectives RF Building Block Design Methodology To do Mixer, Oscillator Circuit performances 65nm 28nm RF Circuit technique Optimize FOM vs Power FOM circuit Best suited topology FOM transistor Active Device biasing 37

38 3 8 Conclusions & Perspectives RF CMOS biasing in future nodes FOM RFblock@transistor versus technology scaling? FOM LPLNA =g m.f T /I D FOM LPLNA =g m.f T /I D 28nm 28nm???? 130nm OR?? 130nm WI MI SI WI MI SI A matter of Device Modelling 38