CIRF Circuit Intégré Radio Fréquence. Low Noise Amplifier. Delaram Haghighitalab Hassan Aboushady Université Paris VI

Transcription

1 CIRF Circuit Intégré Radio Fréquence Low Noise Amplifier Delaram Haghighitalab Hassan Aboushady Université Paris VI

2 Multidisciplinarity of radio design H. Aboushady University of Paris VI

3 References M. Perrott, High Speed Communication Circuits and Systems, M.I.T.OpenCourseWare, Massachusetts Institute of Technology, D. Leenaerts, J. van der Tang, and C. Vaucher, Circuit design for RF transceivers, Kluwer academic publishers, H. Aboushady University of Paris VI

4 LNA : 1 st block of an RF Receiver Heterodyne Homodyne (Direct conversion) Low-IF 4

5 LNA Requirements: Noise Noise Factor : F = SNR in SNR out Noise Figure : NF = 10 log 10 (F) Si F1 G1 F2 G2 F3 G3 So Friis Equation : F = 1+ ( F 1 1) + ( F 1) ( F 1) ( F 1) 2 G G G G G 1 n 2... G n 1 LNA Requirements to reduce the RF receiver overall Noise Factor: Low Noise Factor, F 1 High Gain, G 1 5 University of Paris VI

6 LNA Requirements: Linearity Vi ω1 ω2 A IP 3,1 α 1 2 A IP3 ω x(t) 1 2 A IP3,1 ΔP + y(t) db IIP 3 dbm = + A IP 3,2 β 2 α A IP3,2 ω1 ω2 α β + A ω 2ω1-ω2 2 ω2 -ω1 P in dbm A IP 3,3 γ IP3,3 ΔP Vo +... LNA Requirements to improve the RF receiver overall linearity: High A IP3,1 Low α 1 University of Paris VI 6

7 Outline Impedance Matching Noise Calculations LNA Design Systematic LNA Design Procedure H. Aboushady University of Paris VI

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19 Outline Impedance Matching Noise Calculations LNA Design Systematic LNA Design Procedure H. Aboushady University of Paris VI

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34 Outline Impedance Matching Noise Calculations LNA Design Systematic LNA Design Procedure H. Aboushady University of Paris VI

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37 Outline Impedance Matching Noise Calculations LNA Design Systematic LNA Design Procedure H. Aboushady University of Paris VI

38 Common Source Amplifier A = g. Z v m out Rout Cgd Vout Vin M1 - Parasitic capacitance Cgd between input and output nodes. - Low Gain - Complex Load Impedance ( Zout = Rout r0 1 jωc par ) D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 38

39 Common Source Cascode with Inductive Load Benefits of Cascode - Isolation between input and output nodes - Higher Gain M2 Lout Vout Vin M1 Purpose of Inductive Load - Real Load Impedance can be obtained 1 jω C ( Zout = r0 cascode jω0lout 0 par ) 39 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI

40 Biasing Current Mirror Rref Lout Vout M3 M2 R Vin M1 Current Mirror - The current in M1 is fixed by Rref and the ratio (W1/L1)/(W3/L3). - R is to increase the impedance seen by the input signal. 40 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI

41 Matching Input Impedance Rref Lout Vout M3 M2 R Vin Lg M1 Inductive Degeneration Ldeg - Lg compensates the complex impedance due to Cgs1. - Ldeg adjusts the real part of the input impedance to 50 Ω. 41 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI

42 Ldeg and Lg (1) Input Impedance Z 1 gm ( L C in s) = + s( Ldeg + Lg ) + scgs Matching Zin to 50Ω R s = g C m gs L deg For a Real ω0 ω 0 = 1 (L + L ) g deg C gs D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI gs deg 42

43 Ldeg and Lg (2) Re{Zin} For different Ldeg values Lg Re{Zin} independent of Lg D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 43

44 Ldeg and Lg (2) Re{Zin} For different Ldeg values Lg Re{Zin} independent of Lg Im{Zin} Lg Ldeg for: Re{Zin}=50 Lg for: Im{Zin}=0 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 44

45 NF of a MOS Transistor Techno. 0.35µm c= - 0.4j γ = 2/3 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 45

46 NF Characterization F = N o( total ) SNR SNR = i o N = S i S o N o( source) N i( source) o( total ) + N = o( added ) S ( S i i N. G) i( source) N o( total ) = N G. N o( total ) i( source) No( total ) No( source ) + No( added ) F = = = 1+ N N o( source ) o( source ) N N o( added ) o( source ) 1) No(added) : Output Reffered Noise due to the LNA. 2) No(source): Output Reffered Noise due to the source. 46 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI

47 Noise Sources Résistance R R i 2 R = 4kT R D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI

48 Noise Sources Résistance Transistor R R i 2 R = 4kT R i 2 d = 4kT γ g d 0 Δf i 2 g = 4kT δ g gs Δf D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 48

49 Noise Sources Résistance Transistor Inductance R R Csub Ls Rsub Rsub Rs Rs i 2 R = 4kT R i 2 d = 4kT γ g d 0 Δf i 2 g = 4kT δ g gs Δf D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 49

50 Noise Sources Resistance Transistor Inductance R R Csub Ls Rsub Rsub Rs Rs i 2 R = 4kT R i 2 d = 4kT γ g d 0 Δf F = 1+ N N o( added ) o( source ) i 2 g = 4kT δ g gs Δf N o(added ) NF = f ( G. N i, i N o(source) 2 d H d, i 2 g H g, i 2 R H R, i 2 Rs H Rs, i 2 Rsub H Rsub ) D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 50

51 Noise Sources I I in Hd ( s) = I I out in ( s) ( s) 51 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI

52 Characterization Gain : Vin Circuit out Gain ( s) = Vout( s) Vin( s) Input Impedance: Vin Iin Circuit out Zin ( s) = Vin( s) Iin( s) Noise Factor: in Circuit out F = 1+ N N o( added ) o( source ) D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 52

53 Design Procedure Transistors Length: Minimum L to reduce parasitic capacitances. Width: Ids calculated for NFmin. Layout: Maximum number of fingers to reduce Gate resistance. Inductors Ldeg : Adjusted for Re {Zin} = 50 Ω. Lg : Adjusted for Im {Zin} = 0 Ω. Lout : Adjusted for the desired Zout and Gain. D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 53

54 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 54 University of Paris VI

55 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caractérisa+on de NF, Gain, Zin 55 University of Paris VI

56 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances L L out deg et L g pour : valeurs initiales Re{ Z } 50 in Ids++ No Calculate NF NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 56 University of Paris VI

57 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 57 University of Paris VI

58 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF I++ Non NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 58 University of Paris VI

59 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 59 University of Paris VI

60 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 60 University of Paris VI

61 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances Ids++ No Calculate NF NF min? Yes Ldeg for Re{Zin}=50 Lg for Im{Zin}=0 Impedance Matching Gain Adjustment No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 61 University of Paris VI

62 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 62 University of Paris VI

63 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Choice of Lout : A = G. Z Z v out = m f ( L out out ) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 63 University of Paris VI

64 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids- min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracteriza+on of NF, Gain, Zin 64 University of Paris VI

65 Design Example I: A 2.4GHz LNA in 130 nm CMOS Technologie Vdd Résistance de source (Rs) Fréquence centrale (f0) Gain Résultats de la procédure proposée W (um) L (um) Vgs (V) Spécifications Vds (V) Ids(m A) M M M um 1.2 V 50 Ω 2.4 GHz 15 db R= 100 KΩ, Rref = KΩ, Ldeg = nh, Lg = nh, Lout = 3 nh D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 65

66 Estimated and Simulated Gain and NF Gain (db) NF (db) ELDO D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI

67 Simulated S Parameters S21 (db) S11 (db) F (Hz) 2.4 GHz = db 2.4 GHz = db D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 67

68 Simulated IIP3 Fondamentale IM3 IIP3= dbm D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 68

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